Log in

Relevant bibliographies by topics / Execution thread / Journal articles

To see the other types of publications on this topic, follow the link: Execution thread.

Journal articles on the topic 'Execution thread'

Author: Grafiati

Published: 30 May 2022

Last updated: 19 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Execution thread.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Chen, Caisen, Yangxia Xiang, Yuqin DengLiu, and Zeyun Zhou. "Research on Cache Timing Attack Against RSA with Sliding Window Exponentiation Algorithm." International Journal of Interdisciplinary Telecommunications and Networking 8, no. 2 (2016): 88–95. http://dx.doi.org/10.4018/ijitn.2016040108.

Full text

Abstract:

The vulnerabilities of the RSA cryptographic algorithm are analyzed, and it is not securely implemented. As the simultaneous multithreading could enable multiple execution threads to share the execution resources of a superscalar between the chipper process and the spy process, the shared access to memory caches provides an easily used high bandwidth covert channel between threads, allowing that a malicious thread can monitor the execution of another thread. This paper targets at RSA algorithm which is implemented with sliding window exponentiation algorithm via OpenSSL, the attacker can monit

APA, Harvard, Vancouver, ISO, and other styles

2

Hamidi, Beqir, and Lindita Hamidi. "Synchronization Possibilities and Features in Java." European Journal of Interdisciplinary Studies 1, no. 1 (2015): 75. http://dx.doi.org/10.26417/ejis.v1i1.p75-84.

Full text

Abstract:

In this paper we have discussed one of the greatest features of the general purpose computer programming language –Java. This paper represents concepts of Synchronization possibilities and features in Java. Today's operating systems support concept of "Multitasking". Multitasking achieved by executing more than one task at a same time. Tasks runs on threads. Multitasking runs more than one task at a same time. Multitasking which means doing many things at the same time is one of the most fundamental concepts in computer engineering and computer science because the processor execute given tasks

APA, Harvard, Vancouver, ISO, and other styles

3

Hamidi, Beqir, and Lindita Hamidi. "Synchronization Possibilities and Features in Java." European Journal of Formal Sciences and Engineering 6, no. 2 (2023): 124–36. http://dx.doi.org/10.2478/ejfe-2023-0019.

Full text

Abstract:

Abstract In this paper we have discussed one of the greatest features of the general-purpose computer programming language –Java. This paper represents concepts of Synchronization possibilities and features in Java. Today’s operating systems support concept of “Multitasking”. Multitasking achieved by executing more than one task at a same time. Tasks runs on threads. Multitasking runs more than one task at a same time. Multitasking which means doing many things at the same time is one of the most fundamental concepts in computer engineering and computer science because the processor execute gi

APA, Harvard, Vancouver, ISO, and other styles

4

Ramanauskaite, Simona, Asta Slotkiene, Kornelija Tunaityte, Ivan Suzdalev, Andrius Stankevicius, and Saulius Valentinavicius. "Reducing WCET Overestimations in Multi-Thread Loops with Critical Section Usage." Energies 14, no. 6 (2021): 1747. http://dx.doi.org/10.3390/en14061747.

Full text

Abstract:

Worst-case execution time (WCET) is an important metric in real-time systems that helps in energy usage modeling and predefined execution time requirement evaluation. While basic timing analysis relies on execution path identification and its length evaluation, multi-thread code with critical section usage brings additional complications and requires analysis of resource-waiting time estimation. In this paper, we solve a problem of worst-case execution time overestimation reduction in situations when multiple threads are executing loops with the same critical section usage in each iteration. T

APA, Harvard, Vancouver, ISO, and other styles

5

Bergstra, Jan A., and Cornelis A. Middelburg. "Maurer Computers with Single-Thread Control." Fundamenta Informaticae 80, no. 4 (2007): 333–62. https://doi.org/10.3233/fun-2007-80401.

Full text

Abstract:

We investigate basic issues concerning stored threads and their execution, building upon Maurer's model for computers and the thread algebra of Bergstra et al. We show among other things that a single thread can control the execution on a Maurer machine of any executable finite-state thread stored in the memory of the Maurer machine. We also relate stored threads with programs as considered in the program algebra of Bergstra et al. The work is intended as a preparation for the development of a formal approach to model micro-architectures and to verify their correctness and anticipated speed-up

APA, Harvard, Vancouver, ISO, and other styles

6

Kavi, Krishna, Joseph Arul, and Roberto Giorgi. "Execution and Cache Performance of the Scheduled Dataflow Architecture." JUCS - Journal of Universal Computer Science 6, no. (10) (2000): 948–67. https://doi.org/10.3217/jucs-006-10-0948.

Full text

Abstract:

This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar and superspeculative architectures. This trend allows for better performance at the expense of an increased hardware complexity and a brute-force solution to the memory-wall problem. Our research substantially deviates from this trend by exploring a simpler, yet powerful execution paradigm that is based on dataflow concepts. A program is partitioned into functional execution threads, which are perfectly suited for our

APA, Harvard, Vancouver, ISO, and other styles

7

Bergstra, Jan A., and Cornelis Middelburg. "Probabilistic Thread Algebra." Scientific Annals of Computer Science XXV, no. 2 (2015): 211–43. https://doi.org/10.7561/SACS.2015.2.211.

Full text

Abstract:

We add probabilistic features to basic thread algebra and its extensions with thread-service interaction and strategic interleaving. Here, threads represent the behaviours produced by instruction sequences under execution and services represent the behaviours exhibited by the components of execution environments of instruction sequences. In a paper concerned with probabilistic instruction sequences, we proposed several kinds of probabilistic instructions and gave an informal explanation for each of them. The probabilistic features added to the extension of basic thread algebra with thread-serv

APA, Harvard, Vancouver, ISO, and other styles

8

Karasik, O. N., and A. A. Prihozhy. "ADVANCED SCHEDULER FOR COOPERATIVE EXECUTION OF THREADS ON MULTI-CORE SYSTEM." «System analysis and applied information science», no. 1 (May 4, 2017): 4–11. http://dx.doi.org/10.21122/2309-4923-2017-1-4-11.

Full text

Abstract:

Three architectures of the cooperative thread scheduler in a multithreaded application that is executed on a multi-core system are considered. Architecture A0 is based on the synchronization and scheduling facilities, which are provided by the operating system. Architecture A1 introduces a new synchronization primitive and a single queue of the blocked threads in the scheduler, which reduces the interaction activity between the threads and operating system, and significantly speed up the processes of blocking and unblocking the threads. Architecture A2 replaces the single queue of blocked thre

APA, Harvard, Vancouver, ISO, and other styles

9

Metzler, Patrick, Neeraj Suri, and Georg Weissenbacher. "Extracting safe thread schedules from incomplete model checking results." International Journal on Software Tools for Technology Transfer 22, no. 5 (2020): 565–81. http://dx.doi.org/10.1007/s10009-020-00575-y.

Full text

Abstract:

Abstract Model checkers frequently fail to completely verify a concurrent program, even if partial-order reduction is applied. The verification engineer is left in doubt whether the program is safe and the effort toward verifying the program is wasted. We present a technique that uses the results of such incomplete verification attempts to construct a (fair) scheduler that allows the safe execution of the partially verified concurrent program. This scheduler restricts the execution to schedules that have been proven safe (and prevents executions that were found to be erroneous). We evaluate th

APA, Harvard, Vancouver, ISO, and other styles

10

YONG, XIE, and HSU WEN-JING. "ALIGNED MULTITHREADED COMPUTATIONS AND THEIR SCHEDULING WITH PERFORMANCE GUARANTEES." Parallel Processing Letters 13, no. 03 (2003): 353–64. http://dx.doi.org/10.1142/s0129626403001331.

Full text

Abstract:

This paper considers the problem of scheduling dynamic parallel computations to achieve linear speedup without using significantly more space per processor than that required for a single processor execution. Earlier research in the Cilk project proposed the "strict" computational model, in which every dependency goes from a thread x only to one of x's ancestor threads, and guaranteed both linear speedup and linear expansion of space. However, Cilk threads are stateless, and the task graph that Cilk language expresses is series-parallel graph, which is a proper subset of arbitrary task graph.

APA, Harvard, Vancouver, ISO, and other styles

11

Patrick, Metzler, Suri Neeraj, and Weissenbacher Georg. "Extracting Safe Thread Schedules from Incomplete Model Checking Results." International Journal on Software Tools for Technology Transfer, 2020 11636 (October 2, 2019): 153–71. https://doi.org/10.1007/978-3-030-30923-7_9.

Full text

Abstract:

Model checkers frequently fail to completely verify a con- current program, even if partial-order reduction is applied. The verifica- tion engineer is left in doubt whether the program is safe and the effort towards verifying the program is wasted. We present a technique that uses the results of such incomplete ver- ification attempts to construct a (fair) scheduler that allows the safe execution of the partially verified concurrent program. This scheduler restricts the execution to schedules that have been proven safe (and prevents executions that were found to be erroneous). We evaluate the

APA, Harvard, Vancouver, ISO, and other styles

12

Hirata, Hiroaki, and Atsushi Nunome. "Decoupling Computation and Result Write-Back for Thread-Level Parallelization." International Journal of Software Innovation 8, no. 3 (2020): 19–34. http://dx.doi.org/10.4018/ijsi.2020070102.

Full text

Abstract:

Thread-level speculation (TLS) is an approach to enhance the opportunity of parallelization of programs. A TLS system enables multiple threads to begin the execution of tasks in parallel even if there may be the dependency between tasks. When any dependency violation is detected, the TLS system enforces the violating thread to abort and re-execute the task. So, the frequency of aborts is one of the factors that damage the performance of the speculative execution. This article proposes a new technique named the code shelving, which enables threads not to need to abort. It is available not only

APA, Harvard, Vancouver, ISO, and other styles

13

Tatas, Konstantinos, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, and Stephan Wong. "Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs." Parallel Processing Letters 18, no. 02 (2008): 291–306. http://dx.doi.org/10.1142/s0129626408003399.

Full text

Abstract:

This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an

APA, Harvard, Vancouver, ISO, and other styles

14

Ródenas, David, Xavier Martorell, Eduard Ayguadé, et al. "Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture." Journal of Embedded Computing 2, no. 2 (2006): 141–55. https://doi.org/10.3233/emc-2006-00030.

Full text

Abstract:

This paper evaluates and analyzes multilevel parallelism on a chip multiprocessor (CMP) architecture. The environment is based on the experimental IBM BG/Cyclops architecture, where we have run the multi–zone parallel benchmarks. Multilevel parallelism is spawned using the Nanos OpenMP execution environment. We have performed the analysis with different execution parameters in order to evaluate different hardware threads distributions, cache utilization, and thread grouping configurations. Our results demonstrate that a large number of thread groups and good balancing algorithms are critical f

APA, Harvard, Vancouver, ISO, and other styles

15

Mohammed, Maysoon A. "An Improved Dynamic Slicing Algorithm to Prioritize a Concurrent Multi-threading in Operating System." Iraqi Journal of Industrial Research 10, no. 3 (2023): 11–21. http://dx.doi.org/10.53523/ijoirvol10i3id331.

Full text

Abstract:

One of the issues with multi-threading in operating systems is the concurrency of operations or threads. In a multithreaded process on a single processor, the processor can switch execution resources between threads, enabling concurrent execution. Concurrency indicates that more than one thread is making progress, but the threads are not actually running simultaneously. The switching between threads occurs rapidly enough that the threads might appear to run simultaneously. In this paper, three related strategies for prioritizing multi-threading are presented: ACE-thread, Semaphore coprocessor,

APA, Harvard, Vancouver, ISO, and other styles

16

Hong, Kijae, Kyoungmin Kim, Young-Koo Lee, Yang-Sae Moon, Sourav S. Bhowmick, and Wook-Shin Han. "Themis: A GPU-Accelerated Relational Query Execution Engine." Proceedings of the VLDB Endowment 18, no. 2 (2024): 426–38. https://doi.org/10.14778/3705829.3705856.

Full text

Abstract:

GPU-accelerated relational query execution engines have parallelized the execution of a pipeline, a sequence of operators. For the parallelization, the engines evenly partition the tuples in a table that will be scanned by the pipeline's first operator (a scan), and each thread executes the pipeline for the tuples in a partition. However, this approach leads to load imbalances since an operator returns a varying number of output tuples per input tuple, particularly under non-uniform data distributions such as skewed join key values. The load imbalances are classified into intra- and inter-warp

APA, Harvard, Vancouver, ISO, and other styles

17

Sinharoy, Balaram. "Compiler Optimization to Improve Data Locality for Processor Multithreading." Scientific Programming 7, no. 1 (1999): 21–37. http://dx.doi.org/10.1155/1999/235625.

Full text

Abstract:

Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle), processors stall on cache misses for a significant portion of its execution time. Multithreaded processors has been proposed in the literature to reduce the processor stall time due to cache misses. Although multithreading improves processor utilization, it may also increase cache miss rates, because in a multithreaded processor multiple threads share the same cache, which effective

APA, Harvard, Vancouver, ISO, and other styles

18

Tian, Zhenzhou, Qing Wang, Cong Gao, Lingwei Chen, and Dinghao Wu. "Plagiarism Detection of Multi-threaded Programs Using Frequent Behavioral Pattern Mining." International Journal of Software Engineering and Knowledge Engineering 30, no. 11n12 (2020): 1667–88. http://dx.doi.org/10.1142/s0218194020400252.

Full text

Abstract:

Software dynamic birthmark techniques construct birthmarks using the captured execution traces from running the programs, which serve as one of the most promising methods for obfuscation-resilient software plagiarism detection. However, due to the perturbation caused by non-deterministic thread scheduling in multi-threaded programs, such dynamic approaches optimized for sequential programs may suffer from the randomness in multi-threaded program plagiarism detection. In this paper, we propose a new dynamic thread-aware birthmark FPBirth to facilitate multi-threaded program plagiarism detection

APA, Harvard, Vancouver, ISO, and other styles

19

Paraman, Padma Priya Dharishini, and Prakriya V. Ramana Murthy. "Analysis of benchmark program results of worst case execution time for multithreaded programs." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 2 (2023): 990. http://dx.doi.org/10.11591/ijeecs.v29.i2.pp990-1005.

Full text

Abstract:

<span lang="EN-US">Worst case execution time (WCET) estimation by static analyzers is being investigated with keen interest in view of their importance in designing applications for embedded systems that have real- time requirements. Recent work reported on improving precision of estimates of WCET of multithreaded programs, by improving precision of shared instruction cache analysis, shows significant improvement in WCET estimates. An abstraction of a multithreaded program as Hoare’s communicating sequential processes (CSP) specification program is realized to enable higher precision in

APA, Harvard, Vancouver, ISO, and other styles

20

Padma, Priya Dharishini Paraman, and V. Ramana Murthy Prakriya. "Analysis of benchmark program results of worst case execution time for multithreaded programs." Analysis of benchmark program results of worst case execution time for multithreaded programs 29, no. 2 (2023): 990–1005. https://doi.org/10.11591/ijeecs.v29.i2.pp990-1005.

Full text

Abstract:

Worst case execution time (WCET) estimation by static analyzers is being investigated with keen interest in view of their importance in designing applications for embedded systems that have real- time requirements. Recent work reported on improving precision of estimates of WCET of multithreaded programs, by improving precision of shared instruction cache analysis, shows significant improvement in WCET estimates. An abstraction of a multithreaded program as Hoare’s communicating sequential processes (CSP) specification program is realized to enable higher precision in microarchitectural

APA, Harvard, Vancouver, ISO, and other styles

21

Ootsu, Kanemitsu, Hirohito Ogawa, Takashi Yokota, and Takanobu Baba. "Program Execution Path-Based Speculative Thread Partitioning." Transactions of the Institute of Systems, Control and Information Engineers 22, no. 6 (2009): 209–19. http://dx.doi.org/10.5687/iscie.22.209.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Arandi, Samer, George Matheou, Costas Kyriacou, and Paraskevas Evripidou. "Data-Driven Thread Execution on Heterogeneous Processors." International Journal of Parallel Programming 46, no. 2 (2017): 198–224. http://dx.doi.org/10.1007/s10766-016-0486-6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Moiseenko, Evgenii, Matteo Meluzzi, Innokentii Meleshchenko, Ivan Kabashnyi, Anton Podkopaev, and Soham Chakraborty. "Relaxed Memory Concurrency Re-executed." Proceedings of the ACM on Programming Languages 9, POPL (2025): 2149–75. https://doi.org/10.1145/3704908.

Full text

Abstract:

Defining a formal model for concurrency in programming languages that addresses conflicting requirements from programmers, compilers, and architectures has been a long-standing research question. It is widely believed that traditional axiomatic per-execution models that reason about individual executions do not suffice to address these conflicting requirements. Consequently, several multi-execution models were proposed that reason about multiple executions together. Although multi-execution models were major breakthroughs in satisfying several desired properties, these models are complicated,

APA, Harvard, Vancouver, ISO, and other styles

24

Chen, Yuting. "Platform Independent Analysis of Probabilities on Multithreaded Programs." International Journal of Software Innovation 1, no. 3 (2013): 48–65. http://dx.doi.org/10.4018/ijsi.2013070104.

Full text

Abstract:

A concurrent program is intuitively associated with probability: the executions of the program can produce nondeterministic execution program paths due to the interleavings of threads, whereas some paths can always be executed more frequently than the others. An exploration of the probabilities on the execution paths is expected to provide engineers or compilers with support in helping, either at coding phase or at compile time, to optimize some hottest paths. However, it is not easy to take a static analysis of the probabilities on a concurrent program in that the scheduling of threads of a c

APA, Harvard, Vancouver, ISO, and other styles

25

Bylina, Beata, and Jaroslaw Bylina. "An Experimental Evaluation of the OpenMP Thread Mapping for LU Factorisation on Xeon Phi Coprocessor and on Hybrid CPU-MIC Platform." Scalable Computing: Practice and Experience 19, no. 3 (2018): 259–74. http://dx.doi.org/10.12694/scpe.v19i3.1373.

Full text

Abstract:

Efficient thread mapping relies upon matching the behaviour of the application with system characteristics. The main aim of this paper is to evaluate the influence of the OpenMP thread mapping on the computation performance of the matrix factorisations on Intel Xeon Phi coprocessor and hybrid CPU-MIC platforms. The authors consider parallel LU factorisations with and without pivoting, both from MKL (Math Kernel Library) library. The results show that the choice of thread affinity, the number of threads and the execution mode have a measurable impact on the performance and the scalability of th

APA, Harvard, Vancouver, ISO, and other styles

26

Zaideen, Nur Hafizah, Muhammad Azman Habeeb Mohamed, Nor Asilah Wati Abdul Hamid, Norazrin Ariffin, Mohamed Faris Laham, and Zurita Ismail. "Enhancing Transcriptomic Analysis by Influencing De Novo Assembly Using Parallel Computing." International Journal of Innovative Computing 14, no. 2 (2024): 81–88. http://dx.doi.org/10.11113/ijic.v14n2.483.

Full text

Abstract:

The efficient and accurate assembly of genomic data is a computationally intensive process that demands significant computational resources. Traditional sequential approaches often struggle to handle genomic data sets increasing volume and complexity, leading to prolonged execution times and suboptimal results. The study aims to leverage parallel computing capabilities by employing the ABySS and Velvet Assembler tools on the MD2 Pineapple dataset hosted on the Quanta server. By systematically evaluating the performance of these tools across varying thread counts, the study seeks to identify op

APA, Harvard, Vancouver, ISO, and other styles

27

H. Malave, Sachin, and Subhash K. Shinde. "Symbiotic Organisms Search Optimization to Predict Optimal Thread Count for Multi-threaded Applications." International Journal on Recent and Innovation Trends in Computing and Communication 10, no. 12 (2022): 83–91. http://dx.doi.org/10.17762/ijritcc.v10i12.5889.

Full text

Abstract:

Multicore systems have emerged as a cost-effective option for the growing demands for high-performance, low-energy computing. Thread management has long been a source of concern for developers, as overheads associated with it reduce the overall throughput of the multicore processor systems. One of the most complex problems with multicore processors is determining the optimal number of threads for the execution of multithreaded programs. To address this issue, this paper proposes a novel solution based on a modified symbiotic organism search (MSOS) algorithm which is a bio-inspired algorithm us

APA, Harvard, Vancouver, ISO, and other styles

28

Bouksiaa, Mohamed Said Mosli, Francois Trahay, Alexis Lescouet, et al. "Using Differential Execution Analysis to Identify Thread Interference." IEEE Transactions on Parallel and Distributed Systems 30, no. 12 (2019): 2866–78. http://dx.doi.org/10.1109/tpds.2019.2927481.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Fujisawa, Kohei, Atsushi Nunome, Kiyoshi Shibayama, and Hiroaki Hirata. "Design Space Exploration for Implementing a Software-Based Speculative Memory System." International Journal of Software Innovation 6, no. 2 (2018): 37–49. http://dx.doi.org/10.4018/ijsi.2018040104.

Full text

Abstract:

To enlarge the opportunities for parallelizing a sequentially coded program, the authors have previously proposed speculative memory (SM). With SM, they can start the parallel execution of a program by assuming that it does not violate the data dependencies in the program. When the SM system detects a violation, it recovers the computational state of the program and restarts the execution. In this article, the authors explore the design space for implementing a software-based SM system. They compared the possible choices in the following three viewpoints: (1) which waiting system of suspending

APA, Harvard, Vancouver, ISO, and other styles

30

Zhou, Qiang-Wei, Jia-Nan Li, Rong-Cai Zhao, Lin Han, and Xin Wang. "Compilation Optimization of DCU-oriented OpenMP Thread Scheduling." Journal of Physics: Conference Series 2558, no. 1 (2023): 012003. http://dx.doi.org/10.1088/1742-6596/2558/1/012003.

Full text

Abstract:

Abstract OpenMP is one of the mainstream parallel programming models in recent years. After version 4.0, OpenMP introduced a new target instruction to increase the functionality of heterogeneous programming, called OpenMP Offload. For the domestic heterogeneous platform DCU, the thread scheduling algorithm under OpenMP parallel computing has low performance in the default mode, which does not take the best advantage of GPU parallel computing and has wasted resources. To address this problem, this paper performs algorithm improvement at the compiler level, analyzes the available resources of th

APA, Harvard, Vancouver, ISO, and other styles

31

Cavus, Mustafa, Mohammed Shatnawi, Resit Sendag, and Augustus K. Uht. "Fast Key-Value Lookups with Node Tracker." ACM Transactions on Architecture and Code Optimization 18, no. 3 (2021): 1–26. http://dx.doi.org/10.1145/3452099.

Full text

Abstract:

Lookup operations for in-memory databases are heavily memory bound, because they often rely on pointer-chasing linked data structure traversals. They also have many branches that are hard-to-predict due to random key lookups. In this study, we show that although cache misses are the primary bottleneck for these applications, without a method for eliminating the branch mispredictions only a small fraction of the performance benefit is achieved through prefetching alone. We propose the Node Tracker (NT), a novel programmable prefetcher/pre-execution unit that is highly effective in exploiting in

APA, Harvard, Vancouver, ISO, and other styles

32

Huang, Kaijie, and Jie Cao. "Parallel Differential Evolutionary Particle Filtering Algorithm Based on the CUDA Unfolding Cycle." Wireless Communications and Mobile Computing 2021 (October 15, 2021): 1–12. http://dx.doi.org/10.1155/2021/1999154.

Full text

Abstract:

Aiming at the problem of low statute efficiency of prefix sum execution during the execution of the parallel differential evolutionary particle filtering algorithm, a filtering algorithm based on the CUDA unfolding cyclic prefix sum is proposed to remove the thread differentiation and thread idleness existing in the parallel prefix sum by unfolding the cyclic method and unfolding the thread bundle method, optimize the cycle, and improve the prefix sum execution efficiency. By introducing the parallel strategy, the differential evolutionary particle filtering algorithm is implemented in paralle

APA, Harvard, Vancouver, ISO, and other styles

33

Jghef, Yousif Sufyan, Marwan Aziz Mohammed, Abdulqadir Ismail Abdullah, Nashwan Adnan Othman, Sazan Kamal Sulaiman, and Husam Barjas Bofaoor. "Enhanced techniques to measure the execution time of distributed and cloud computing systems." ITM Web of Conferences 64 (2024): 01017. http://dx.doi.org/10.1051/itmconf/20246401017.

Full text

Abstract:

ICT giants include cloud computing and distributed systems. Researchers have ignored the idea of merging distributed systems and cloud computing to examine millisecond execution times and megabyte capacity. The system used Google’s API to download files to the cloud. The system sent files to the principal server. Now there are two ways to calculate execution time accurately. The first scenario uses threads to construct clients and servers. Second, pool threads are used. This article examines file capacity and execution time. The system demonstrated how cloud computing influences distributed sy

APA, Harvard, Vancouver, ISO, and other styles

34

Gibadullin, Ruslan Farshatovich. "Thread-safe Control Calls in Enriched Client Applications." Программные системы и вычислительные методы, no. 4 (April 2022): 1–19. http://dx.doi.org/10.7256/2454-0714.2022.4.39029.

Full text

Abstract:

When the first version of the .NET Framework was released, there was a pattern in enriched client applications that focused on message processing loops, where an embedded queue was used to pass execution units from worker threads. A generalized ISynchronizeInvoke solution was then developed in which the source thread could queue a delegate to the destination thread and, as an optional option, wait for that delegate to complete. After asynchronous page support was introduced into the ASP.NET architecture, the ISynchronizeInvoke pattern did not work because asynchronous ASP.NET pages are not map

APA, Harvard, Vancouver, ISO, and other styles

35

DU, Yan-Ning, Yin-Liang ZHAO, Bo HAN, and Yuan-Cheng LI. "Data Structure Directed Thread Partitioning Method and Execution Model." Journal of Software 24, no. 10 (2014): 2432–59. http://dx.doi.org/10.3724/sp.j.1001.2013.04353.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Kang, Jihun, and Heonchang Yu. "GPGPU Task Scheduling Technique for Reducing the Performance Deviation of Multiple GPGPU Tasks in RPC-Based GPU Virtualization Environments." Symmetry 13, no. 3 (2021): 508. http://dx.doi.org/10.3390/sym13030508.

Full text

Abstract:

In remote procedure call (RPC)-based graphic processing unit (GPU) virtualization environments, GPU tasks requested by multiple-user virtual machines (VMs) are delivered to the VM owning the GPU and are processed in a multi-process form. However, because the thread executing the computing on general GPUs cannot arbitrarily stop the task or trigger context switching, GPU monopoly may be prolonged owing to a long-running general-purpose computing on graphics processing unit (GPGPU) task. Furthermore, when scheduling tasks on the GPU, the time for which each user VM uses the GPU is not considered

APA, Harvard, Vancouver, ISO, and other styles

37

Fauzan, Hermawan, Riyanarto Sarno, and Ahmad Saikhu. "Accelerating real-time deterministic discovery through single instruction multiple data graphical processor unit for executing distributed event logs." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 4 (2024): 4214. http://dx.doi.org/10.11591/ijece.v14i4.pp4214-4227.

Full text

Abstract:

With the rapid expansion of process mining implementation in global enterprises distributed across numerous branches, there is a critical requirement to develop an application qualified for real-time operation with fast and precise data integration. To address this challenge, computational parallelism emerges as a feasible solution to accelerate data analytics, with graphical processor unit (GPU) computing currently trending for achieving parallelism acceleration. In this study, we developed a process mining application to optimize parallel and distributed process discovery through a combinati

APA, Harvard, Vancouver, ISO, and other styles

38

Kyriacou, Costas, Paraskevas Evripidou, and Pedro Trancoso. "CacheFlow: Cache Optimizations for Data Driven Multithreading." Parallel Processing Letters 16, no. 02 (2006): 229–44. http://dx.doi.org/10.1142/s0129626406002599.

Full text

Abstract:

Data-Driven Multithreading is a non-blocking multithreading model of execution that provides effective latency tolerance by allowing the computation processor do useful work, while a long latency event is in progress. With the Data-Driven Multithreading model, a thread is scheduled for execution only if all of its inputs have been produced and placed in the processor's local memory. Data-driven sequencing leads to irregular memory access patterns that could affect negatively cache performance. Nevertheless, it enables the implementation of short-term optimal cache management policies. This pap

APA, Harvard, Vancouver, ISO, and other styles

39

Eilers, Marco, Thibault Dardinier, and Peter Müller. "CommCSL: Proving Information Flow Security for Concurrent Programs using Abstract Commutativity." Proceedings of the ACM on Programming Languages 7, PLDI (2023): 1682–707. http://dx.doi.org/10.1145/3591289.

Full text

Abstract:

Information flow security ensures that the secret data manipulated by a program does not influence its observable output. Proving information flow security is especially challenging for concurrent programs, where operations on secret data may influence the execution time of a thread and, thereby, the interleaving between different threads. Such internal timing channels may affect the observable outcome of a program even if an attacker does not observe execution times. Existing verification techniques for information flow security in concurrent programs attempt to prove that secret data does no

APA, Harvard, Vancouver, ISO, and other styles

40

Guo, JunXia, Zheng Li, CunFeng Shi, and RuiLian Zhao. "Thread Scheduling Sequence Generation Based on All Synchronization Pair Coverage Criteria." International Journal of Software Engineering and Knowledge Engineering 30, no. 01 (2020): 97–118. http://dx.doi.org/10.1142/s0218194020500059.

Full text

Abstract:

Testing multi-thread programs becomes extremely difficult because thread interleavings are uncertain, which may cause a program getting different results in each execution. Thus, Thread Scheduling Sequence (TSS) is a crucial factor in multi-thread program testing. A good TSS can obtain better testing efficiency and save the testing cost especially with the increase of thread numbers. Focusing on the above problem, in this paper, we discuss a kind of approach that can efficiently generate TSS based on the concurrent coverage criteria. First, we give a definition of Synchronization Pair (SP) as

APA, Harvard, Vancouver, ISO, and other styles

41

WANG, SHENGYUE, PEN-CHUNG YEW, and ANTONIA ZHAI. "CODE TRANSFORMATIONS FOR ENHANCING THE PERFORMANCE OF SPECULATIVELY PARALLEL THREADS." Journal of Circuits, Systems and Computers 21, no. 02 (2012): 1240008. http://dx.doi.org/10.1142/s0218126612400087.

Full text

Abstract:

As technology advances, microprocessors that integrate multiple cores on a single chip are becoming increasingly common. How to use these processors to improve the performance of a single program has been a challenge. For general-purpose applications, it is especially difficult to create efficient parallel execution due to the complex control flow and ambiguous data dependences. Thread-level speculation and transactional memory provide two hardware mechanisms that are able to optimistically parallelize potentially dependent threads. However, a compiler that performs detailed performance trade-

APA, Harvard, Vancouver, ISO, and other styles

42

Bergstra, Jan A., and Cornelis Middelburg. "Thread Extraction for Polyadic Instruction Sequences." Scientific Annals of Computer Science XXI, no. 2 (2011): 283–310. https://doi.org/10.5281/zenodo.12720926.

Full text

Abstract:

In this paper, we study the phenomenon that instruction sequences are split into fragments which somehow produce a joint behaviour. In order to bring this phenomenon better into the picture, we formalize a simple mechanism by which several instruction sequence fragments can produce a joint behaviour. We also show that, even in the case of this simple mechanism, it is a non-trivial matter to explain by means of a translation into a single instruction sequence what takes place on execution of a collection of instruction sequence fragments.

APA, Harvard, Vancouver, ISO, and other styles

43

Fauzan, Hermawan, Riyanarto Sarno, and Ahmad Saikhu. "Accelerating real-time deterministic discovery through single instruction multiple data graphical processor unit for executing distributed event logs." Accelerating real-time deterministic discovery through single instruction multiple data graphical processor unit for executing distributed event logs 14, no. 4 (2024): 4214–27. https://doi.org/10.11591/ijece.v14i4.pp4214-4227.

Full text

Abstract:

With the rapid expansion of process mining implementation in global enterprises distributed across numerous branches, there is a critical requirement to develop an application qualified for real-time operation with fast and precise data integration. To address this challenge, computational parallelism emerges as a feasible solution to accelerate data analytics, with graphical processor unit (GPU) computing currently trending for achieving parallelism acceleration. In this study, we developed a process mining application to optimize parallel and distributed pr

APA, Harvard, Vancouver, ISO, and other styles

44

Rivas, Mario Aldea, and Michael González Harbour. "Operating system support for execution time budgets for thread groups." ACM SIGAda Ada Letters XXVII, no. 2 (2007): 67–71. http://dx.doi.org/10.1145/1316002.1316017.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Kim, Seung Hun, Dohoon Kim, Changmin Lee, Won Seob Jeong, Won Woo Ro, and Jean-Luc Gaudiot. "A Performance-Energy Model to Evaluate Single Thread Execution Acceleration." IEEE Computer Architecture Letters 14, no. 2 (2015): 99–102. http://dx.doi.org/10.1109/lca.2014.2368144.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Liu, Shuyang, Doug Lea, and Jens Palsberg. "Soundness of Predictive Concurrency Analyses." Proceedings of the ACM on Programming Languages 9, OOPSLA1 (2025): 590–616. https://doi.org/10.1145/3720435.

Full text

Abstract:

A predictive analysis takes an execution trace as input and discovers concurrency bugs without accessing the program source code. A sound predictive analysis reports no false positives, which sounds like a property that can be defined easily, but which has been defined in many different ways in previous work. In this paper, we unify, simplify, and generalize those soundness definitions for analyses that discover concurrency bugs that can be represented as a consecutive sequence of events. Our soundness definition is graph based, separates thread-local properties and whole-execution properties,

APA, Harvard, Vancouver, ISO, and other styles

47

Dr., Abraham Tomvie Goodhead, and Vincent Samuel Kikile. "Parallel Sorting of Randomly Generated Grid Jobs on a Single-Processor System." International Journal of Mathematics and Computer Research 12, no. 11 (2024): 4577–85. https://doi.org/10.5281/zenodo.14195521.

Full text

Abstract:

Improvements in computer technologies continue to shape the presence and the future of modernization, driven by the need for faster and more efficient processing, most chip manufacturers have abandoned the single-processor system and turned attention to other hardware technologies like the multicore system. However, should the baby (single-processor system) be thrown away with the bathwater?  Parallelization which defines the era of the multicore if properly exploited on single-processor systems can improve performance. This work exploits thread-level parallelism on the single processor s

APA, Harvard, Vancouver, ISO, and other styles

48

Gandhi, Indra, Kannan G., and P. K. Jawahar. "Real-time enhanced efficient thread level parallelism scheme for performance improvement in heterogeneous edge computing." Multidisciplinary Science Journal 6, no. 9 (2024): 2024145. http://dx.doi.org/10.31893/multiscience.2024145.

Full text

Abstract:

In the era of technology, there is a need to rely on new high performance Heterogeneous embedded computing device to process a huge amount of data for various smart applications. Packing different architecture processor into a system on chip provides a substantial potential improvement in computing horsepower, but the maximum processing power of this heterogeneous edge computing processor can only be harnessed if the target software is actually configured to utilize all the processing elements. The proposed Enhanced Efficient thread level parallelism (EETLP) is implemented using CUDA in CPU-GP

APA, Harvard, Vancouver, ISO, and other styles

49

Choi, Kiho, Daejin Park, and Jeonghun Cho. "SSCFM: Separate Signature-Based Control Flow Error Monitoring for Multi-Threaded and Multi-Core Environments." Electronics 8, no. 2 (2019): 166. http://dx.doi.org/10.3390/electronics8020166.

Full text

Abstract:

Soft error is a key challenge in computer systems. Without soft error mitigation, control flow error (CFE) can lead to system crash. Signature-based CFE monitoring scheme is a representative technique for detecting CFEs during runtime. However, most of the signature-based CFE monitoring schemes proposed thus far are based on a single thread. Currently, the widely used multi-threaded and multi-core environments have greatly improved the performance of the computing system, but, if the these schemes are applied in these environments, performance improvement is difficult to achieve, or rather per

APA, Harvard, Vancouver, ISO, and other styles

50

Xue, Xiaozhen, Sima Siami-Namini, and Akbar Siami Namin. "Testing Multi-Threaded Applications Using Answer Set Programming." International Journal of Software Engineering and Knowledge Engineering 28, no. 08 (2018): 1151–75. http://dx.doi.org/10.1142/s021819401850033x.

Full text

Abstract:

We introduce a technique to formally represent and specify race conditions in multithreaded applications. Answer set programming (ASP) is a logic-based knowledge representation paradigm to formally express belief acquired through reasoning in an application domain. The transparent and expressiveness representation of problems along with powerful non-monotonic reasoning power enable ASP to abstractly represent and solve some certain classes of NP hard problems in polynomial times. We use ASP to formally express race conditions and thus represent potential data races often occurred in multithrea

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!