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Journal articles on the topic 'Extensible processor'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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1

Martin, Grant. "What is a configurable, extensible processor?" ACM SIGDA Newsletter 38, no. 16 (August 15, 2008): 1. http://dx.doi.org/10.1145/1862846.1862847.

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Martin, Grant. "What is a configurable, extensible processor?" ACM SIGDA Newsletter 38, no. 17 (September 2008): 1. http://dx.doi.org/10.1145/1862849.1862850.

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3

Gonzalez, R. E. "Xtensa: a configurable and extensible processor." IEEE Micro 20, no. 2 (2000): 60–70. http://dx.doi.org/10.1109/40.848473.

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4

Martin, Grant. "Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors." Journal of Signal Processing Systems 53, no. 1-2 (November 29, 2007): 113–27. http://dx.doi.org/10.1007/s11265-007-0153-7.

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5

Sun, F., S. Ravi, A. Raghunathan, and N. K. Jha. "Custom-Instruction Synthesis for Extensible-Processor Platforms." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 2 (February 2004): 216–28. http://dx.doi.org/10.1109/tcad.2003.822133.

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Misko, Joshua, Shrikant S. Jadhav, and Youngsoo Kim. "Extensible Embedded Processor for Convolutional Neural Networks." Scientific Programming 2021 (April 21, 2021): 1–12. http://dx.doi.org/10.1155/2021/6630552.

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Convolutional neural networks (CNNs) require significant computing power during inference. Smart phones, for example, may not run a facial recognition system or search algorithm smoothly due to the lack of resources and supporting hardware. Methods for reducing memory size and increasing execution speed have been explored, but choosing effective techniques for an application requires extensive knowledge of the network architecture. This paper proposes a general approach to preparing a compressed deep neural network processor for inference with minimal additions to existing microprocessor hardw

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Noori, Hamid, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, and Morteza Saheb Zamani. "An architecture framework for an adaptive extensible processor." Journal of Supercomputing 45, no. 3 (February 1, 2008): 313–40. http://dx.doi.org/10.1007/s11227-008-0174-4.

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Dutheil, Julien Y., Sylvain Gaillard, and Eva H. Stukenbrock. "MafFilter: a highly flexible and extensible multiple genome alignment files processor." BMC Genomics 15, no. 1 (2014): 53. http://dx.doi.org/10.1186/1471-2164-15-53.

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9

Bauer, L., M. Shafique, and J. Henkel. "Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 10 (October 2008): 1295–308. http://dx.doi.org/10.1109/tvlsi.2008.2002430.

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10

Sano, Kentaro, Luzhou Wang, and Satoru Yamamoto. "Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation." ACM SIGARCH Computer Architecture News 38, no. 4 (September 14, 2010): 80–86. http://dx.doi.org/10.1145/1926367.1926381.

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Li, Lin, Shengbing Zhang, and Juan Wu. "Design of Deep Learning VLIW Processor for Image Recognition." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 38, no. 1 (February 2020): 216–24. http://dx.doi.org/10.1051/jnwpu/20203810216.

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In order to adapt the application demands of high resolution images recognition and efficient processing of localization in aviation and aerospace fields, and to solve the problem of insufficient parallelism in existing researches, an extensible multiprocessor cluster deep learning processor architecture based on VLIW is designed by optimizing the computation of each layer of deep convolutional neural network model. Parallel processing of feature maps and neurons, instruction level parallelism based on very long instruction word (VLIW), data level parallelism of multiprocessor clusters and pip

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Cetin, E., R. C. S. Morling, and I. Kale. "An extensible complex fast Fourier transform processor chip for real-time spectrum analysis and measurement." IEEE Transactions on Instrumentation and Measurement 47, no. 1 (1998): 95–99. http://dx.doi.org/10.1109/19.728798.

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13

Lagadec, Loïc, Damien Picard, Youenn Corre, and Pierre-Yves Lucas. "Experiment Centric Teaching for Reconfigurable Processors." International Journal of Reconfigurable Computing 2011 (2011): 1–14. http://dx.doi.org/10.1155/2011/952560.

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This paper presents a setup for teaching configware to master students. Our approach focuses on experiment and leaning-by-doing while being supported by research activity. The central project we submit to students addresses building up a simple RISC processor, that supports an extensible instructions set thanks to its reconfigurable functional unit. The originality comes from that the students make use of the Biniou framework. Biniou is a research tool which approach covers tasks ranging from describing the RFU, synthesizing it as VHDL code, and implementing applications over it. Once done, st

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WAGGY, SCOTT B., ALEC KUCALA, and SEDAT BIRINGEN. "PARALLEL IMPLEMENTATION OF A NAVIER–STOKES SOLVER: TURBULENT EKMAN LAYER DIRECT SIMULATION." International Journal of Computational Methods 11, no. 05 (October 2014): 1350070. http://dx.doi.org/10.1142/s0219876213500709.

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A massively parallel direct numerical solution procedure for the turbulent Ekman layer is presented. The simulations study the dynamics of turbulence in this flow by solving the incompressible Navier–Stokes equations with Coriolis and buoyancy terms. The governing equations are integrated via a semi-implicit time advancement algorithm which is massively parallelized using the Portable, Extensible Toolkit for Scientific Computation (PETSc) libraries. Accuracy of the numerical scheme was validated by comparisons of simulation results with the hydrodynamic linear stability theory for Poiseuille f

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Wait, Eric, Mark Winter, and Andrew R. Cohen. "Hydra image processor: 5-D GPU image analysis library with MATLAB and python wrappers." Bioinformatics 35, no. 24 (June 26, 2019): 5393–95. http://dx.doi.org/10.1093/bioinformatics/btz523.

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Abstract Summary Light microscopes can now capture data in five dimensions at very high frame rates producing terabytes of data per experiment. Five-dimensional data has three spatial dimensions (x, y, z), multiple channels (λ) and time (t). Current tools are prohibitively time consuming and do not efficiently utilize available hardware. The hydra image processor (HIP) is a new library providing hardware-accelerated image processing accessible from interpreted languages including MATLAB and Python. HIP automatically distributes data/computation across system and video RAM allowing hardware-acc

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Huang, LinYun, Young-Pil Lee, Yong-Seon Moon, and Young-Chul Bae. "Noble Implementation of Motor Driver with All Programmable SoC for Humanoid Robot or Industrial Device." International Journal of Humanoid Robotics 14, no. 04 (November 16, 2017): 1750028. http://dx.doi.org/10.1142/s0219843617500281.

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Currently, as the requirements for simple implementations in the motor control technologies increase, System-on-Chip (SoC) device such as Zynq All Programmable SoC was devised to meet those requirements. Because this CPU and FPGA can be assembled into one SoC device, we can consolidate motor-control functions and additional processing tasks into a single SoC device. The control algorithms, networking and other tasks, are off-loaded to the programmable logic that can include multiple control cores and multiple control system. This SoC system with a single chip can allow the hardware design with

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Li, Hong Yi, Cheng Yang, Xiao Yu Wu, and Ya Ning Wu. "A Kind of Video Abstracting System Base on Hadoop." Applied Mechanics and Materials 687-691 (November 2014): 2186–91. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2186.

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Digital video, as a kind of large-scale resource, plays an important role in internet’s multimedia resources. Resource consuming is one of the major issues for extracting data from digital video. However, if it is possible to know the outline of a video by browsing several pictures describing it, that will save us a huge amount of time. Up till now, it is not common for video processing system using cloud environment (except video transcoding system). This demo shows an extensible video processing system based on Apache Hadoop cloud environment. Our system utilizes FFmpeg video encoder and Ope

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18

Vlahopoulos, Nickolas, and Michael M. Bernitsas. "Three-Dimensional Nonlinear Dynamics of Nonintegral Riser Bundle." Journal of Ship Research 35, no. 01 (March 1, 1991): 40–57. http://dx.doi.org/10.5957/jsr.1991.35.1.40.

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The dynamic behavior of a nonintegral riser bundle is studied parametrically. The dynamics of each component-riser is analyzed by a three-dimensional, nonlinear, large deflection, small strain model with coupled bending and torsion. Component-risers are slender, thin-walled, extensible or inextensible tubular beam-columns, subject to response and deformation dependent hydrodynamic loads. The con-nector equations of equilibrium are used to derive the connector forces and moments. Substructuring can thus be achieved even though in three dimensions connectors do not impose linearly dependent defl

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19

CASEAU, YVES, FRANÇOIS-XAVIER JOSSET, and FRANÇOIS LABURTHE. "CLAIRE: combining sets, search and rules to better express algorithms." Theory and Practice of Logic Programming 2, no. 6 (November 2002): 769–805. http://dx.doi.org/10.1017/s1471068401001363.

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This paper presents a programming language which includes paradigms that are usually associated with declarative languages, such as sets, rules and search, into an imperative (functional) language. Although these paradigms are separately well known and are available under various programming environments, the originality of the CLAIRE language comes from the tight integration, which yields interesting run-time performances, and from the richness of this combination, which yields new ways in which to express complex algorithmic patterns with few elegant lines. To achieve the opposite goals of a

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20

Saadawi, Gilan M., and James H. Harrison. "Definition of an XML Markup Language for Clinical Laboratory Procedures and Comparison with Generic XML Markup." Clinical Chemistry 52, no. 10 (October 1, 2006): 1943–51. http://dx.doi.org/10.1373/clinchem.2006.071449.

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Abstract Background: Clinical laboratory procedure manuals are typically maintained as word processor files and are inefficient to store and search, require substantial effort for review and updating, and integrate poorly with other laboratory information. Electronic document management systems could improve procedure management and utility. As a first step toward building such systems, we have developed a prototype electronic format for laboratory procedures using Extensible Markup Language (XML). Methods: Representative laboratory procedures were analyzed to identify document structure and d

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21

LOIDL, HANS-WOLFGANG, PHILIP W. TRINDER, and CARSTEN BUTZ. "TUNING TASK GRANULARITY AND DATA LOCALITY OF DATA PARALLEL GPH PROGRAMS." Parallel Processing Letters 11, no. 04 (December 2001): 471–86. http://dx.doi.org/10.1142/s0129626401000737.

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The performance of data parallel programs often hinges on two key coordination aspects: the computational costs of the parallel tasks relative to their management overhead — task granularity; and the communication costs induced by the distance between tasks and their data — data locality. In data parallel programs both granularity and locality can be improved by clustering, i.e. arranging for parallel tasks to operate on related sub-collections of data. The GPH parallel functional language automatically manages most coordination aspects, but also allows some high-level control of coordination

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22

Arsenault, Kristi R., Sujay V. Kumar, James V. Geiger, Shugong Wang, Eric Kemp, David M. Mocko, Hiroko Kato Beaudoing, et al. "The Land surface Data Toolkit (LDT v7.2) – a data fusion environment for land data assimilation systems." Geoscientific Model Development 11, no. 9 (September 5, 2018): 3605–21. http://dx.doi.org/10.5194/gmd-11-3605-2018.

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Abstract. The effective applications of land surface models (LSMs) and hydrologic models pose a varied set of data input and processing needs, ranging from ensuring consistency checks to more derived data processing and analytics. This article describes the development of the Land surface Data Toolkit (LDT), which is an integrated framework designed specifically for processing input data to execute LSMs and hydrological models. LDT not only serves as a preprocessor to the NASA Land Information System (LIS), which is an integrated framework designed for multi-model LSM simulations and data assi

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23

Kamal, Mehdi, Ali Afzali-Kusha, Saeed Safari, and Massoud Pedram. "Design of NBTI-resilient extensible processors." Integration 49 (March 2015): 22–34. http://dx.doi.org/10.1016/j.vlsi.2014.12.001.

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24

Shalaby, Nadia, Andy Bavier, Yitzchak Gottlieb, Scott Karlin, Larry Peterson, Xiaohu Qie, Tammo Spalink, and Mike Wawrzoniak. "Building extensible routers using network processors." Software: Practice and Experience 35, no. 12 (2005): 1155–94. http://dx.doi.org/10.1002/spe.667.

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25

Xiao, Chenglong, and Emmanuel Casseau. "Exact custom instruction enumeration for extensible processors." Integration 45, no. 3 (June 2012): 263–70. http://dx.doi.org/10.1016/j.vlsi.2011.11.011.

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26

Xiao, Chenglong, Shanshan Wang, Wanjun Liu, and Emmanuel Casseau. "Parallel custom instruction identification for extensible processors." Journal of Systems Architecture 76 (May 2017): 149–59. http://dx.doi.org/10.1016/j.sysarc.2016.11.011.

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27

Fei, Y., S. Ravi, A. Raghunathan, and N. K. Jha. "A Hybrid Energy-Estimation Technique for Extensible Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 5 (May 2004): 652–64. http://dx.doi.org/10.1109/tcad.2004.826546.

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28

Fei Sun, S. Ravi, A. Raghunathan, and N. K. Jha. "Application-specific heterogeneous multiprocessor synthesis using extensible processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 9 (September 2006): 1589–602. http://dx.doi.org/10.1109/tcad.2005.858269.

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29

Chen, Xiaoyong, Douglas L. Maskell, and Yang Sun. "Fast Identification of Custom Instructions for Extensible Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 2 (February 2007): 359–68. http://dx.doi.org/10.1109/tcad.2006.883915.

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30

Li, T., W. Jigang, Y. Deng, T. Srikanthan, and X. Lu. "Accelerating identification of custom instructions for extensible processors." IET Circuits, Devices & Systems 5, no. 1 (2011): 21. http://dx.doi.org/10.1049/iet-cds.2010.0073.

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31

Bonzini, P., and L. Pozzi. "Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 10 (October 2008): 1259–67. http://dx.doi.org/10.1109/tvlsi.2008.2001863.

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32

Goyal, Puneet, and Narayan Chaturvedi. "Multiple Output Complex Instruction Matching Algorithm for Extensible Processors." International Journal of Computer Applications 49, no. 21 (July 31, 2012): 31–35. http://dx.doi.org/10.5120/7897-1240.

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33

Yazdanbakhsh, Amir, Mehdi Kamal, Sied Mehdi Fakhraie, Ali Afzali-Kusha, Saeed Safari, and Massoud Pedram. "Implementation-aware selection of the custom instruction set for extensible processors." Microprocessors and Microsystems 38, no. 7 (October 2014): 681–91. http://dx.doi.org/10.1016/j.micpro.2014.05.007.

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34

LUKAC, RASTISLAV, PAVOL GALAJDA, and ALENA GALAJDOVA. "LUM PROCESSOR WITH NEURAL DECISION." International Journal of Pattern Recognition and Artificial Intelligence 20, no. 05 (August 2006): 747–62. http://dx.doi.org/10.1142/s0218001406004934.

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This paper focuses on impulsive noise filtering and outliers rejection in gray-scale images. The proposed method combines neural networks, lower-upper-middle (LUM) smoothers and adaptive switching operations to produce a high-quality enhanced image. Extensive experimentation reported in this paper indicates that the proposed method is sufficiently robust, achieves an excellent balance between noise suppression and signal-detail preservation, and outperforms some well-known filters both subjectively and objectively.

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SCHAFFER, KEVIN, and ROBERT A. WALKER. "USING HARDWARE MULTITHREADING TO OVERCOME BROADCAST/REDUCTION LATENCY IN AN ASSOCIATIVE SIMD PROCESSOR." Parallel Processing Letters 18, no. 04 (December 2008): 491–509. http://dx.doi.org/10.1142/s0129626408003533.

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The latency of broadcast/reduction operations has a significant impact on the performance of SIMD processors. This is especially true for associative programs, which make extensive use of global search operations. Previously, we developed a prototype associative SIMD processor that uses hardware multithreading to overcome the broadcast/reduction latency. In this paper we show, through simulations of the processor running an associative program, that hardware multithreading is able to improve performance by increasing system utilization, even for processors with hundreds or thousands of process

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KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

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Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel

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37

Sun, Fei, Srivaths Ravi, Anand Raghunathan, and Niraj K. Jha. "A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 11 (November 2007): 2035–45. http://dx.doi.org/10.1109/tcad.2007.906457.

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38

Kamal, Mehdi, Ali Afzali-Kusha, Saeed Safari, and Massoud Pedram. "Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors." ACM Journal on Emerging Technologies in Computing Systems 10, no. 3 (April 2014): 1–25. http://dx.doi.org/10.1145/2567665.

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39

Sari, Aitzan, and Mihalis Psarakis. "A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors." Journal of Circuits, Systems and Computers 26, no. 08 (April 11, 2017): 1740009. http://dx.doi.org/10.1142/s0218126617400096.

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Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in th

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40

Greer, Bruce, John Harrison, Greg Henry, Wei Li, and Peter Tang. "Scientific Computing on the Itanium® Processor." Scientific Programming 10, no. 4 (2002): 329–37. http://dx.doi.org/10.1155/2002/193478.

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The 64-bit Intel® Itanium® architecture is designed for high-performance scientific and enterprise computing, and the Itanium processor is its first silicon implementation. Features such as extensive arithmetic support, predication, speculation, and explicit parallelism can be used to provide a sound infrastructure for supercomputing. A large number of high-performance computer companies are offering Itanium® -based systems, some capable of peak performance exceeding 50 GFLOPS. In this paper we give an overview of the most relevant architectural features and provide illustrations of how these

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41

Hua, Jing, Yingqiong Peng, Yilu Xu, Kun Cao, and Jing Jia. "Makespan Minimization for Multiprocessor Real-Time Systems under Thermal and Timing Constraints." Journal of Circuits, Systems and Computers 28, no. 09 (August 2019): 1950145. http://dx.doi.org/10.1142/s0218126619501457.

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With the continued scaling of the CMOS device, the exponential increase in power density has strikingly elevated the temperature of on-chip systems. In this paper, the problem of allocating and scheduling frame-based real-time applications is addressed to multiprocessors to minimize the makespan under the thermal and timing constraints. The proposed algorithms consist of offline and online components. The offline component assigns the applications accepted at static time to processors in a way that the finish time of processors are balanced. The online component firstly selects the processor w

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42

Dixon, Matthew, Jörg Lotze, and Mohammad Zubair. "A portable, extensible and fast stochastic volatility model calibration using multi and many-core processors." Concurrency and Computation: Practice and Experience 28, no. 3 (November 20, 2015): 866–77. http://dx.doi.org/10.1002/cpe.3727.

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43

Kamal, Mehdi, Ali Afzali-Kusha, Saeed Safari, and Massoud Pedram. "Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions." ACM Transactions on Design Automation of Electronic Systems 21, no. 2 (January 28, 2016): 1–25. http://dx.doi.org/10.1145/2830566.

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Faraci, Giuseppe, Alfio Lombardo, and Giovanni Schembra. "A Processor-Sharing Scheduling Strategy for NFV Nodes." Journal of Electrical and Computer Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/3583962.

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The introduction of the two paradigms SDN and NFV to “softwarize” the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR), a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs) according to the state of the queues associated with the outp

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Günzel, Mario, Christian Hakert, Kuan-Hsun Chen, and Jian-Jia Chen. "HEART: H ybrid Memory and E nergy- A ware R eal- T ime Scheduling for Multi-Processor Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–23. http://dx.doi.org/10.1145/3477019.

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Dynamic power management (DPM) reduces the power consumption of a computing system when it idles, by switching the system into a low power state for hibernation. When all processors in the system share the same component, e.g., a shared memory, powering off this component during hibernation is only possible when all processors idle at the same time. For a real-time system, the schedulability property has to be guaranteed on every processor, especially if idle intervals are considered to be actively introduced. In this work, we consider real-time systems with hybrid shared-memory architectures,

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46

Yin, G., and Y. M. Zhu. "On W.P.1 Convergence of A Parallel Stochastic Approximation Algorithm." Probability in the Engineering and Informational Sciences 3, no. 1 (January 1989): 55–75. http://dx.doi.org/10.1017/s0269964800000978.

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To find zeros or locate maximum values of a regression function with noisy measurements, a commonly used algorithm is the RM or KW procedure. In various applications, the dimensionality of the problems involved might be quite large. As a result, enormous memory space and extensive computation time may be needed. Motivated by the recent progress in stochastic approximation methods for decentralized and distributed computing, a parallel stochastic approximation algorithm is developed in this paper. The essence is to take advantage of state-space decompositions, and to exploit the opportunities p

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47

Mahmood, Ausif. "Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures." VLSI Design 4, no. 1 (January 1, 1996): 59–68. http://dx.doi.org/10.1155/1996/91035.

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The development of multi-processor architectures requires extensive behavioral simulations to verify the correctness of design and to evaluate its performance. A high level language can provide maximum flexibility in this respect if the constructs for handling concurrent processes and a time mapping mechanism are added. This paper describes a novel technique for emulating hardware processes involved in a parallel architecture such that an object-oriented description of the design is maintained. The communication and synchronization between hardware processes is handled by splitting the process

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48

Ababneh, Ismail M., Saad Bani-Mohammad, and Motasem Al Smadi. "Corner-Boundary Processor Allocation for 3D Mesh-Connected Multicomputers." International Journal of Cloud Applications and Computing 5, no. 1 (January 2015): 1–13. http://dx.doi.org/10.4018/ijcac.2015010101.

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This research paper presents a new contiguous allocation strategy for 3D mesh-connected multicomputers. The proposed strategy maintains a list of maximal free sub-meshes and gives priority to allocating corner and boundary free sub-meshes. The goal of corner and boundary allocation is to decrease the number of leftover free sub-meshes and increase their sizes, which is expected to reduce processor fragmentation and improve overall system performance. The proposed strategy, which is referred to as Turning Corner-Boundary Free List (TCBFL) strategy, is compared, using extensive simulation experi

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NICOL, DAVID M., and WEIZHEN MAO. "ON BOTTLENECK PARTITIONING OF k-ARY n-CUBES." Parallel Processing Letters 06, no. 03 (September 1996): 389–99. http://dx.doi.org/10.1142/s0129626496000376.

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Graph partitioning is a topic of extensive interest, with applications to parallel processing. In this context graph nodes typically represent computation, and edges represent communication. One seeks to distribute the workload by partitioning the graph so that every processor has approximately the same workload, and the communication cost (measured as a function of edges exposed by the partition) is minimized. Measures of partition quality vary; in this paper we consider a processor’s cost to be the sum of its computation and communication costs, and consider the cost of a partition to be the

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Mikheev, Andrei, and Liubov Liubushkina. "Russian morphology: An engineering approach." Natural Language Engineering 1, no. 3 (September 1995): 235–60. http://dx.doi.org/10.1017/s135132490000019x.

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AbstractMorphological analysis, which is at the heart of the processing of natural language requires computationally effective morphological processors. In this paper an approach to the organization of an inflectional morphological model and its application for the Russian language are described. The main objective of our morphological processor is not the classification of word constituents, but rather an efficient computational recognition of morpho-syntactic features of words and the generation of words according to requested morpho-syntactic features. Another major concern that the process

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