Relevant bibliographies by topics / Fault-tolerant adder

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Fault-tolerant adder'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "Fault-tolerant adder"

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BKondalkar, Mangesh, Arunkumar P Chavan, and P. Narashimaraja. "Improved Fault Tolerant Sparse KOGGE Stone ADDER." International Journal of Computer Applications 75, no. 10 (August 23, 2013): 36–41. http://dx.doi.org/10.5120/13150-0582.

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N.G, Prashanth, Savitha A. P, M. B. Anandaraju, and Naveen K. B. "Design of Efficient Reversible Fault tolerant Adder/Subtractor." International Journal of Computer Applications 74, no. 9 (July 26, 2013): 23–28. http://dx.doi.org/10.5120/12913-9845.

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Purkayastha, Tamoghna, Tanay Chattopadhyay, and Debashis De. "Planar fault-tolerant quantum cellular automata full adder." Nanomaterials and Energy 7, no. 1 (June 2018): 9–15. http://dx.doi.org/10.1680/jnaen.17.00007.

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Mahajan, Rita. "Design of Fault Tolerant Full Adder and Full Subtractor." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (April 30, 2018): 292–301. http://dx.doi.org/10.22214/ijraset.2018.4053.

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Kumar, Dharmendra, and Debasis Mitra. "Design of a practical fault-tolerant adder in QCA." Microelectronics Journal 53 (July 2016): 90–104. http://dx.doi.org/10.1016/j.mejo.2016.04.004.

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Sen, Bibhash, Siddhant Ganeriwal, and Biplab K. Sikdar. "Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA." ISRN Electronics 2013 (June 16, 2013): 1–9. http://dx.doi.org/10.1155/2013/850267.

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Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.
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Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.
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Mohammadi, Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sanchez, and Matteo Sonza Reorda. "A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors." ACM Journal on Emerging Technologies in Computing Systems 13, no. 2 (March 10, 2017): 1–13. http://dx.doi.org/10.1145/2988234.

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Kumar, Pankaj, and Rajender Kumar Sharma. "Real-time fault tolerant full adder design for critical applications." Engineering Science and Technology, an International Journal 19, no. 3 (September 2016): 1465–72. http://dx.doi.org/10.1016/j.jestch.2016.05.001.

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Farazkish, Razieh. "A new quantum-dot cellular automata fault-tolerant full-adder." Journal of Computational Electronics 14, no. 2 (February 25, 2015): 506–14. http://dx.doi.org/10.1007/s10825-015-0668-2.

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Dissertations / Theses on the topic "Fault-tolerant adder"

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Khalus, Vladislav Ivanovich. "T-COUNT OPTIMIZATION OF QUANTUM CARRY LOOK-AHEAD ADDER." UKnowledge, 2019. https://uknowledge.uky.edu/ece_etds/141.

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With the emergence of quantum physics and computer science in the 20th century, a new era was born which can solve very difficult problems in a much faster rate or problems that classical computing just can't solve. In the 21st century, quantum computing needs to be used to solve tough problems in engineering, business, medical, and other fields that required results not today but yesterday. To make this dream come true, engineers in the semiconductor industry need to make the quantum circuits a reality. To realize quantum circuits and make them scalable, they need to be fault tolerant, therefore Clifford+T gates need to be implemented into those circuits. But the main issue is that in the Clifford+T gate set, T gates are expensive to implement. Carry Look-Ahead addition circuits have caught the interest of researchers because the number of gate layers encountered by a given qubit in the circuit (or the circuit's depth) is logarithmic in terms of the input size n. Therefore, this thesis focuses on optimizing previous designs of out-of-place and in-place Carry Look-Ahead Adders to decrease the T-count, sum of all T and T Hermitian transpose gates in a quantum circuit.
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Hajkazemi, Mohammad Hossein. "FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for High-Performance Processor." Thesis, 2013. http://hdl.handle.net/1828/4802.

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This thesis introduces an alternative Fault-Tolerant Power-Aware Hybrid Adder (or simply FARHAD) for high-performance processors. FARHAD, similar to earlier studies, relies on performing add operations twice to detect errors. Unlike previous studies, FARHAD uses an aggressive adder to produce the initial outcome and a low-power adder to generate the second outcome, referred to as the checker. FARHAD uses checkpoints, a feature already available to high-performance processors, to recover from errors. FARHAD achieves the high energy-efficiency of time-redundant solutions and the high performance of resource-redundant adders. We evaluate FARHAD from power and performance points of view using a subset of SPEC’2K benchmarks. Our evaluations show that FARHAD outperforms an alternative time-redundant solution by 20%. FARHAD reduces the power dissipation of an alternative resource-redundant adder by 40% while maintaining performance.
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Book chapters on the topic "Fault-tolerant adder"

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Mukherjee, Atin, and Anindya Sundar Dhar. "Design of a Fault-Tolerant Conditional Sum Adder." In Progress in VLSI Design and Test, 217–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31494-0_25.

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Bharani Surya, S., C. Gokul Prasad, S. Raghul, and N. Mohankumar. "Evolving Reversible Fault-Tolerant Adder Architectures and Their Power Estimation." In Lecture Notes in Electrical Engineering, 533–40. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2612-1_51.

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Sundararajan, Gopalakrishnan. "Fault Tolerance in Carbon Nanotube Transistors Based Multi Valued Logic." In Carbon Nanotubes - Redefining the World of Electronics [Working Title]. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.95361.

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This Chapter presents a solution for fault-tolerance in Multi-Valued Logic (MVL) circuits comprised of Carbon Nano-Tube Field Effect Transistors (CNTFET). This chapter reviews basic primitives of MVL and describes ternary implementations of CNTFET circuits. Finally, this chapter describes a method for error correction called Restorative Feedback (RFB). The RFB method is a variant of Triple-Modular Redundancy (TMR) that utilizes the fault masking capabilities of the Muller C element to provide added protection against noisy transient faults. Fault tolerant properties of Muller C element is discussed and error correction capability of RFB method is demonstrated in detail.
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Sahoo, Sampa, Bibhudatta Sahoo, Ashok Kumar Turuk, and Sambit Kumar Mishra. "Real Time Task Execution in Cloud Using MapReduce Framework." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 190–209. IGI Global, 2017. http://dx.doi.org/10.4018/978-1-5225-1721-4.ch008.

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Cloud Computing era comes with the advancement of technologies in the fields of processing, storage, bandwidth network access, security of internet etc. The development of automatic applications, smart devices and applications, sensor based applications need huge data storage and computing resources and need output within a particular time limit. Now users are becoming more sensitive towards, delay in applications they are using. So, a scalable platform like Cloud Computing is required that can provide huge computing resource, and data storage required for processing such applications. MapReduce framework is used to process huge amounts of data. Data processing on a cloud based on MapReduce would provide added benefits such as fault tolerant, heterogeneous, ease of use, free and open, efficient. This chapter discusses about cloud system model, real-time MapReduce framework, Cloud based MapReduce framework examples, quality attributes of MapReduce scheduling and various MapReduce scheduling algorithm based on quality attributes.
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Cardinale, Yudith, Joyce El Haddad, Maude Manouvrier, and Marta Rukoz. "Transactional-Aware Web Service Composition." In Handbook of Research on Service-Oriented Systems and Non-Functional Properties, 116–41. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-61350-432-1.ch006.

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Web Service (WS) composition consists in combining several WSs into a Composite WS (CWS), which becomes a value-added process. In order to provide reliable and fault-tolerant CWSs, several transactional-aware composition approaches have been proposed. However, as far as we know, no real classification survey of such approaches exists. This is the contribution of this chapter. Our classification distinguishes the more relevant and recent propositions in two groups: approaches based on WS transactional properties and the ones also integrating QoS criteria to the composition process. All these studied approaches are compared according to several criteria: the transactional model used or proposed, the control flow model used or automatically generated, the mechanism proposed to verify the transactional property of the composition, the step(s) of the composition process involved in, and the protocols or the standard languages used or extended. This classification allows underlining the lacks and the future directions which should be studied.
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Conference papers on the topic "Fault-tolerant adder"

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Bose, Avishek, and Hafiz Md Hasan Babu. "Optimized designs of reversible fault tolerant BCD adder and fault tolerant reversible carry skip BCD adder." In 2015 18th International Conference on Computer and Information Technology (ICCIT). IEEE, 2015. http://dx.doi.org/10.1109/iccitechn.2015.7488068.

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gupta, Sonal, Ashish Jasuja, and Rahul shandilya. "Real-time fault tolerant full adder using fault localization." In 2018 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS). IEEE, 2018. http://dx.doi.org/10.1109/sceecs.2018.8546908.

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Kumar, Pankaj, and Rajender Kumar Sharma. "Double fault tolerant full adder design using fault localization." In 2017 3rd International Conference on Computational Intelligence & Communication Technology (CICT). IEEE, 2017. http://dx.doi.org/10.1109/ciact.2017.7977345.

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Biernat, Janusz. "The Complexity of Fault-Tolerant Adder Structures." In 2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX. IEEE, 2008. http://dx.doi.org/10.1109/depcos-relcomex.2008.60.

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Mukherjee, Atin, and Anindya Sundar Dhar. "Double-fault tolerant architecture design for digital adder." In 2014 IEEE Students' Technology Symposium (TechSym). IEEE, 2014. http://dx.doi.org/10.1109/techsym.2014.6807932.

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Gupta, Sonal, Shweta Meena, and Vahiuddin Syed Khaja. "Real-Time Double Fault Tolerant Full Adder Design Using Fault Detection." In 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS). IEEE, 2018. http://dx.doi.org/10.1109/iccons.2018.8662961.

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Palsodkar, Prachi, Prasanna Palsodkar, and Rupali Giri. "Multiple Error Self Checking-Repairing Fault Tolerant Adder-Multiplier." In 2018 IEEE 6th Region 10 Humanitarian Technology Conference (R10-HTC). IEEE, 2018. http://dx.doi.org/10.1109/r10-htc.2018.8629854.

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Mitra, Sajib Kumar, and Ahsan Raja Chowdhury. "Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis." In 2012 25th International Conference on VLSI Design. IEEE, 2012. http://dx.doi.org/10.1109/vlsid.2012.93.

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Malipatil, Somashekhar, Avinash Gour, and Vikas Maheshwari. "Fault Tolerant Reversible Full Adder Design Using Gate Diffusion Input." In 2020 International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE). IEEE, 2020. http://dx.doi.org/10.1109/icstcee49637.2020.9276774.

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Mukherjee, Atin, and Anindya Sundar Dhar. "Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture." In 2012 International Symposium on Electronic System Design (ISED). IEEE, 2012. http://dx.doi.org/10.1109/ised.2012.21.

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