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Journal articles on the topic 'Fault-tolerant adder'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 February 2022

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1

BKondalkar, Mangesh, Arunkumar P Chavan, and P. Narashimaraja. "Improved Fault Tolerant Sparse KOGGE Stone ADDER." International Journal of Computer Applications 75, no. 10 (August 23, 2013): 36–41. http://dx.doi.org/10.5120/13150-0582.

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2

N.G, Prashanth, Savitha A. P, M. B. Anandaraju, and Naveen K. B. "Design of Efficient Reversible Fault tolerant Adder/Subtractor." International Journal of Computer Applications 74, no. 9 (July 26, 2013): 23–28. http://dx.doi.org/10.5120/12913-9845.

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3

Purkayastha, Tamoghna, Tanay Chattopadhyay, and Debashis De. "Planar fault-tolerant quantum cellular automata full adder." Nanomaterials and Energy 7, no. 1 (June 2018): 9–15. http://dx.doi.org/10.1680/jnaen.17.00007.

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4

Mahajan, Rita. "Design of Fault Tolerant Full Adder and Full Subtractor." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (April 30, 2018): 292–301. http://dx.doi.org/10.22214/ijraset.2018.4053.

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5

Kumar, Dharmendra, and Debasis Mitra. "Design of a practical fault-tolerant adder in QCA." Microelectronics Journal 53 (July 2016): 90–104. http://dx.doi.org/10.1016/j.mejo.2016.04.004.

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6

Sen, Bibhash, Siddhant Ganeriwal, and Biplab K. Sikdar. "Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA." ISRN Electronics 2013 (June 16, 2013): 1–9. http://dx.doi.org/10.1155/2013/850267.

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Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

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7

Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.

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8

Mohammadi, Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sanchez, and Matteo Sonza Reorda. "A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors." ACM Journal on Emerging Technologies in Computing Systems 13, no. 2 (March 10, 2017): 1–13. http://dx.doi.org/10.1145/2988234.

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9

Kumar, Pankaj, and Rajender Kumar Sharma. "Real-time fault tolerant full adder design for critical applications." Engineering Science and Technology, an International Journal 19, no. 3 (September 2016): 1465–72. http://dx.doi.org/10.1016/j.jestch.2016.05.001.

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10

Farazkish, Razieh. "A new quantum-dot cellular automata fault-tolerant full-adder." Journal of Computational Electronics 14, no. 2 (February 25, 2015): 506–14. http://dx.doi.org/10.1007/s10825-015-0668-2.

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11

C M, Aiswarya, and Shanil Mohamed N. "Design of a Modified Carry Select Adder with Single Fault Tolerant Architecture." IJARCCE 6, no. 6 (June 30, 2017): 474–79. http://dx.doi.org/10.17148/ijarcce.2017.6684.

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12

Valinataj, Mojtaba. "Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors." Microelectronics Reliability 55, no. 12 (December 2015): 2845–57. http://dx.doi.org/10.1016/j.microrel.2015.08.017.

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13

Raj, Marshal, Lakshminarayanan Gopalakrishnan, and Seok-Bum Ko. "Fast Quantum-Dot Cellular Automata Adder/Subtractor Using Novel Fault Tolerant Exclusive-or Gate and Full Adder." International Journal of Theoretical Physics 58, no. 9 (June 15, 2019): 3049–64. http://dx.doi.org/10.1007/s10773-019-04184-7.

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14

Roohi, Arman, Ronald F. DeMara, and Navid Khoshavi. "Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder." Microelectronics Journal 46, no. 6 (June 2015): 531–42. http://dx.doi.org/10.1016/j.mejo.2015.03.023.

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15

Pittala, Sureshkumar, and Sasikala Duraisamy. "A CMOS Based Self Repair Fault Tolerant Adder for Low Power Biomedical Systems." Universal Journal of Electrical and Electronic Engineering 7, no. 6 (December 2020): 307–14. http://dx.doi.org/10.13189/ujeee.2020.070602.

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16

Himanshu Shekhar, Prof. Deepa Gianchandani. "Survey on Fault Tolerance Startgies for Advance Microelectronics Chip." International Journal on Recent and Innovation Trends in Computing and Communication 7, no. 1 (January 31, 2019): 01–04. http://dx.doi.org/10.17762/ijritcc.v7i1.5217.

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In the complex advance microelectronics based system, handling units are managing gadgets of littler size, which are delicate to the transient faults. A framework should be fabricated that will perceive the presence of faults and fuses strategies to will endure these faults without troublesome the typical activity A transient fault happens in a circuit caused by the electromagnetic commotions, astronomical beams, crosstalk and power supply clamor. It is extremely hard to recognize these faults amid disconnected testing. Subsequently a region effective fault tolerant full adder for testing and fixing of transient and changeless faults happened in single and multi-net is proposed. Furthermore, the proposed design can likewise identify and fix perpetual faults. This structure acquires much lower equipment overheads with respect to the conventional equipment design. In this paper, talk about various fault tolerant methodology for CMOS and ICs.

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17

Ban, Tian, and Gutemberg G. S. Junior. "Critical Gates Identification for Fault-Tolerant Design in Math Circuits." Journal of Electrical and Computer Engineering 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/5684902.

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Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of an error in the output of a circuit. These critical gates should be hardened first under the area constraint of design criteria. Indeed, output bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors. The 74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach.

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18

BinTalib, Ghashmi H., and Aiman H. El-Maleh. "Hybrid and Double Modular Redundancy (DMR)-Based Fault-Tolerant Carry Look-Ahead Adder Design." Arabian Journal for Science and Engineering 46, no. 9 (May 27, 2021): 8969–81. http://dx.doi.org/10.1007/s13369-021-05708-2.

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19

Farazkish, Razieh, and Fatemeh Khodaparast. "Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata." Microprocessors and Microsystems 39, no. 6 (August 2015): 426–33. http://dx.doi.org/10.1016/j.micpro.2015.04.004.

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20

Bilal, Bisma, Suhaib Ahmed, and Vipan Kakkar. "Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing." International Journal of Theoretical Physics 57, no. 5 (February 6, 2018): 1356–75. http://dx.doi.org/10.1007/s10773-018-3664-z.

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21

Mohammadi, Shahram, Reza Omidi, and Mohammad Lotfinejad. "Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes." Journal of Electronic Testing 36, no. 4 (June 3, 2020): 555–63. http://dx.doi.org/10.1007/s10836-020-05887-0.

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22

Biernat, Janusz. "Fast fault-tolerant adders." International Journal of Critical Computer-Based Systems 1, no. 1/2/3 (2010): 117. http://dx.doi.org/10.1504/ijccbs.2010.031709.

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23

Bin Talib, Ghashmi H., Aiman H. El-Maleh, and Sadiq M. Sait. "Design of Fault Tolerant Adders: A Review." Arabian Journal for Science and Engineering 43, no. 12 (September 25, 2018): 6667–92. http://dx.doi.org/10.1007/s13369-018-3556-9.

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24

Zhang, Xiao Jie, You Long Chen, and Xiao Ping Zhang. "The Study of the Relation Between Faulty Tolerant Bound and Control Allocation." Advanced Materials Research 433-440 (January 2012): 4077–81. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4077.

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Fault tolerant control can improve the safety of aircraft under control surface failures. Sometime the redundancy method losses its effectiveness when the actuator is impaired severely. Under this condition the fault tolerant method can not be used to compensate failures. The paper proposes a method to find the bound by analysis and computer by moment for fault tolerant control. And give the effect on control allocation. At last the fault tolerant bound is added to control allocation as one of limit conditions.

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25

Valinataj, Mojtaba, Mahboobeh Mirshekar, and Hamid Jazayeri. "Novel low-cost and fault-tolerant reversible logic adders." Computers & Electrical Engineering 53 (July 2016): 56–72. http://dx.doi.org/10.1016/j.compeleceng.2016.06.008.

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26

Azza, Hechmi Ben, Mongi Moujahed, Mohamed Jemli, and Mohamed Boussak. "Implementation of Improved Sliding Mode Observer and Fault Tolerant Control for a PMSM Drive." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1750032. http://dx.doi.org/10.1142/s0218126617500323.

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This paper presents the development and experimentation of Fault-Tolerant Control (FTC) for sensorless Permanent Magnet Synchronous Motor (PMSM) drive with stator resistance tuning. In the fault-tolerant inverter, a redundant leg is added to replace the faulted leg. Consequently, the proposed inverter is a modified topology inverter with fault-tolerant capability, which can be configured as 3-phase 8-switch inverter. The detection of the faulty leg is based only on the output inverter currents measurement. To make toggle to a redundant leg in case of fault occurrence, a Fault Detection and Isolation (FDI) algorithm is proposed in this paper. Experimental results are presented using a 1.4[Formula: see text]kW, three poles three-phases PMSM. These results show that the proposed FDI algorithm is able to detect and to isolate the open-phase fault in PMSM drive.

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27

Zhou, Ri-Gui, Yan-Cheng Li, and Man-Qun Zhang. "Novel designs for fault tolerant reversible binary coded decimal adders." International Journal of Electronics 101, no. 10 (September 5, 2013): 1336–56. http://dx.doi.org/10.1080/00207217.2013.832388.

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28

Shen, Yanxia, Beibei Miao, Dinghui Wu, and Kader Ali Ibrahim. "Fault-Tolerant Control Strategy for Neutral-Point-Clamped Three-Level Inverter." Journal of Control Science and Engineering 2018 (February 1, 2018): 1–9. http://dx.doi.org/10.1155/2018/5126404.

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A fault-tolerant control technique is discussed for the Neutral-Point-Clamped (NPC) three-level inverter, which ensures that the NPC inverter operates normally even under device failures. A two-level leg is added to the NPC inverter; when the device open circuit fault occurs, the load of this faulty phase is connected to the neutral point of this two-level leg through the bidirectional thyristors. An improved Space Vector Pulse Width Modulation (SVPWM) strategy called “addition and subtraction substitution SVPWM” is proposed to effectively suppress fluctuation in capacitor neutral-point voltages by readjusting the sequence and action time of voltage vectors. The fault-tolerant topology in this paper has the advantages of fewer switching devices and lower circuit costs. Experimental results show that the proposed fault-tolerant system can operate in balance of capacitor neutral-point voltages at full output power and the reliability of the inverter is greatly enhanced.

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29

Ahmadpour, Seyed-Sajad, and Mohammad Mosleh. "New designs of fault-tolerant adders in quantum-dot cellular automata." Nano Communication Networks 19 (March 2019): 10–25. http://dx.doi.org/10.1016/j.nancom.2018.11.001.

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30

Bharathi, M. "Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders." International Journal of VLSI Design & Communication Systems 3, no. 2 (April 30, 2012): 85–98. http://dx.doi.org/10.5121/vlsic.2012.3208.

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31

Litinski, Daniel, and Felix von Oppen. "Lattice Surgery with a Twist: Simplifying Clifford Gates of Surface Codes." Quantum 2 (May 4, 2018): 62. http://dx.doi.org/10.22331/q-2018-05-04-62.

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We present a planar surface-code-based scheme for fault-tolerant quantum computation which eliminates the time overhead of single-qubit Clifford gates, and implements long-range multi-target CNOT gates with a time overhead that scales only logarithmically with the control-target separation. This is done by replacing hardware operations for single-qubit Clifford gates with a classical tracking protocol. Inter-qubit communication is added via a modified lattice surgery protocol that employs twist defects of the surface code. The long-range multi-target CNOT gates facilitate magic state distillation, which renders our scheme fault-tolerant and universal.

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32

Yang, Pu, Zhangxi Liu, Yuxia Wang, and Dejie Li. "Adaptive Sliding Mode Fault-Tolerant Control for Uncertain Systems with Time Delay." International Journal of Automation Technology 14, no. 2 (March 5, 2020): 337–45. http://dx.doi.org/10.20965/ijat.2020.p0337.

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In this work, an adaptive sliding mode fault-tolerant controller is proposed for a class of uncertain systems with time delay. The integral term is added to the traditional sliding surface to improve the robustness of the control system, and then a type of special sliding surface is designed to cancel the reaching mode based on global sliding mode method. Without the need for fault detection and isolation, an adaptive law is proposed to estimate the value of actuator faults, and an adaptive sliding mode fault-tolerant controller is designed to guarantee the asymptotic stability of sliding dynamics. Finally, the presented control scheme is applied to the position control of a Qball-X4 quad-rotor UAV model to verify the effectiveness.

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33

Ahmadpour, Seyed‐Sajad, Mohammad Mosleh, and Saeed Rasouli Heikalabad. "Robust QCA full‐adders using an efficient fault‐tolerant five‐input majority gate." International Journal of Circuit Theory and Applications 47, no. 7 (May 27, 2019): 1037–56. http://dx.doi.org/10.1002/cta.2634.

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34

Zhang, Han, and Wanzhong Zhao. "Two-way H∞ control method with a fault-tolerant module for steer-by-wire system." Proceedings of the Institution of Mechanical Engineers, Part C: Journal of Mechanical Engineering Science 232, no. 1 (October 7, 2016): 42–56. http://dx.doi.org/10.1177/0954406216673672.

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To improve the maneuverability, stability, and reliability of the steer-by-wire system, a two-way H∞ control method with a fault-tolerant module is proposed in this paper. First, a two-way H∞ control scheme is proposed. Two controllers are designed in this scheme: one is used as a feedback controller as a general practice to stabilize the system and detect the tracking error; the other is used as a feed forward controller to make the output of the system follow the driver’s steering intention rapidly and precisely. Second, a fault-tolerant module aiming at front wheel angle sensor which is an important feedback signal to the system is added to improve the reliability of the system. A revised Kalman filter is applied in the fault-tolerant module to reconfigure the front wheel angle as a reference value and a substitute when the sensor fails, thus replacing hardware redundancy by software redundancy in a cost-effective way. Lastly, simulations by Matlab/Simulink and CarSim software and hardware-in-the-loop experiments are conducted and effectiveness of the proposed control method is demonstrated by simulation and experimental results and numerical analyses.

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35

Valinataj, Mojtaba. "Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters." Microelectronics Reliability 96 (May 2019): 7–20. http://dx.doi.org/10.1016/j.microrel.2019.03.003.

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36

Theilliol, Didier, Cédric Join, and Youmin Zhang. "Actuator Fault Tolerant Control Design Based on a Reconfigurable Reference Input." International Journal of Applied Mathematics and Computer Science 18, no. 4 (December 1, 2008): 553–60. http://dx.doi.org/10.2478/v10006-008-0048-1.

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Actuator Fault Tolerant Control Design Based on a Reconfigurable Reference InputThe prospective work reported in this paper explores a new approach to enhance the performance of an active fault tolerant control system. The proposed technique is based on a modified recovery/trajectory control system in which a reconfigurable reference input is considered when performance degradation occurs in the system due to faults in actuator dynamics. An added value of this work is to reduce the energy spent to achieve the desired closed-loop performance. This work is justified by the need of maintaining a reliable system in a dynamical way in order to achieve a mission by an autonomous system, e.g., a launcher, a satellite, a submarine, etc. The effectiveness is illustrated using a three-tank system for slowly varying reference inputs corrupted by actuators faults.

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37

Zhou, Yan, Huiying Liu, and Jing Li. "L1 Adaptive for Aircraft Lateral Fault Tolerant Control with Actuator Failure." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 37, no. 5 (October 2019): 935–42. http://dx.doi.org/10.1051/jnwpu/20193750935.

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When aircraft is laterally controlled, actuator failure may cause matched/unmatched uncertainties. In order to deal with the uncertainty, a fault-tolerant controller is designed by using L1 adaptive control method. An aircraft lateral model was established by considering faults and disturbances, the effects of the uncertainty and interference were counteracted by using L1 adaptive controller in order to ensure the rapid adaptation and robustness, and then the stability and transient performance of the closed-loop system were proven through Lyapunov method. In the case of multiplicative fault, additive fault and stuck fault, the uncertainties of model parameter were added to simulate simultaneously. Simulation results showed that the present control method in both single-fault mode and hybrid-failure mode could ensure the uniform bounded control signal and parameter estimation, effectively eliminates the effect of the faults and had the good fault tolerance and robustness.

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38

Lv, Zhichao, and Guangqiang Wu. "A Novel Method for Clutch Pressure Sensor Fault Diagnosis." Vehicles 2, no. 1 (March 5, 2020): 191–209. http://dx.doi.org/10.3390/vehicles2010011.

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As a crucial output component, a clutch pressure sensor is of great importance on monitoring and controlling a whole transmission system and a whole vehicle status, both of which play important roles in the safety and reliability of a vehicle. With the help of fault diagnosis, the fault state prediction of a pressure sensor is realized, and this lays the foundation for further fault-tolerant control. In this paper, a fault diagnosis method of Dual Clutch Transmission (DCT) is designed. Firstly, a Variable Force Solenoid (VFS) valve model is established. A feed-forward input system is added to correct the first-order inertial link of the sensor on the second step. Finally, the parameters of the established system model are identified by using the measured data of the actual transmission and the Genetic Algorithm (GA). An identified model is then used for designing a fault observer. The constant output faults of 0, 3, and 5 V, pulse fault, and bias fault that enterprises are concerned with are selected to simulate and verify the fault observer under four different operating conditions. The results show that the designed fault observer has great fault diagnosis performance.

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39

Sato, Yuji, and Mikiko Sato. "Parallelization and sustainability of distributed genetic algorithms on many-core processors." International Journal of Intelligent Computing and Cybernetics 7, no. 1 (March 4, 2014): 2–23. http://dx.doi.org/10.1108/ijicc-06-2013-0033.

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Purpose – The purpose of this paper is to propose a fault-tolerant technology for increasing the durability of application programs when evolutionary computation is performed by fast parallel processing on many-core processors such as graphics processing units (GPUs) and multi-core processors (MCPs). Design/methodology/approach – For distributed genetic algorithm (GA) models, the paper proposes a method where an island's ID number is added to the header of data transferred by this island for use in fault detection. Findings – The paper has shown that the processing time of the proposed idea is practically negligible in applications and also shown that an optimal solution can be obtained even with a single stuck-at fault or a transient fault, and that increasing the number of parallel threads makes the system less susceptible to faults. Originality/value – The study described in this paper is a new approach to increase the sustainability of application program using distributed GA on GPUs and MCPs.

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40

Xu, Chun, Yue Lin, Ya Nan Gao, and Song Tao Fan. "Analysis and Simulation on Clock Resynchronization in Time Triggered Architecture." Applied Mechanics and Materials 556-562 (May 2014): 4408–11. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.4408.

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An improved clock synchronization algorithm for time triggered architecture has been proposed in this paper. A single reference real time is added in the system, so periodically calibration to real time can be achieved. This algorithm is based on the classical Welch-Lynch[1] fault tolerant clock synchronization process. Systematic clock drift problem has been solved by using the algorithm. Formal analysis is presented, and verification is taken on Matlab/Simulink platform. Simulation result has verified the performance of the algorithm, and the clock difference is bounded as expected.

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41

Poorhosseini, Mehrdad, and Ali Reza Hejazi. "A Fault-Tolerant and Efficient XOR Structure for Modular Design of Complex QCA Circuits." Journal of Circuits, Systems and Computers 27, no. 07 (March 26, 2018): 1850115. http://dx.doi.org/10.1142/s0218126618501153.

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Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

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42

R, Saranya, Pradeep C, Neena Baby, and Radhakrishnan R. "FPGA Synthesis of Reconfigurable Modules for FIR Filter." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 2 (July 1, 2015): 63. http://dx.doi.org/10.11591/ijres.v4.i2.pp63-70.

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Reconfigurable computing for DSP remains an active area to explore as the need for incorporation with more conventional DSP technologies turn out to be obvious. Conventionally, the majority of the work in the area of reconfigurable computing is aimed on fine grained FPGA devices. Over the years, the focus is shifted from bit level granularity to a coarse grained composition. FIR filter remains and persist to be an important building block in various DSP systems. It computes the output by multiplying input samples with a set of coefficients followed by addition. Here multipliers and adders are modeled using the concept of divide and conquer. For developing a reconfiguarble FIR filter, different tap filters are designed as separate reconfigurable modules. Furthermore, there is an additional concern for making the system fault tolerant. A fault detection mechanism is introduced to detect the faults based on the nature of operands. The reconfigurable modules are structurally modeled in Verilog HDL and simulated and synthesized using Xilinx ISE 14.2. A comparison of the device utilization of reconfigurable modules is also presented in this paper by implementing the design on various Virtex FPGA devices.

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43

Jeong, Eunjin, Dowhan Jeong, and Soonhoi Ha. "Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems." ACM Transactions on Design Automation of Electronic Systems 26, no. 5 (June 5, 2021): 1–38. http://dx.doi.org/10.1145/3447680.

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Existing software development methodologies mostly assume that an application runs on a single device without concern about the non-functional requirements of an embedded system such as latency and resource consumption. Besides, embedded software is usually developed after the hardware platform is determined, since a non-negligible portion of the code depends on the hardware platform. In this article, we present a novel model-based software synthesis framework for parallel and distributed embedded systems. An application is specified as a set of tasks with the given rules for execution and communication. Having such rules enables us to perform static analysis to check some software errors at compile-time to reduce the verification difficulty. Platform-specific programs are synthesized automatically after the mapping of tasks onto processing elements is determined. The proposed framework is expandable to support new hardware platforms easily. The proposed communication code synthesis method is extensible and flexible to support various communication methods between devices. In addition, the fault-tolerant feature can be added by modifying the task graph automatically according to the selected fault-tolerance configurations by the user. The viability of the proposed software development methodology is evaluated with a real-life surveillance application that runs on six processing elements.

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Yin, Aihan, Ziliang Tan, Tong Chen, Weibin Lin, and Qiutong Wu. "Flexible quantum protocol for nearest private query." Modern Physics Letters A 36, no. 04 (January 8, 2021): 2150023. http://dx.doi.org/10.1142/s0217732321500231.

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Nearest private query (NPQ) allows user to query which element in the database is the nearest to his private data without revealing any private information and this query is typically used for location query services. However, the previous NPQ protocol only involved the implementation of its functions and ignored the user’s private experience. In addition, the average number of key bits obtained by the user is only determined by the size of the database. In order to improve the flexibility and practicality of the protocol, we proposed a flexible protocol for nearest private query based on quantum oblivious key distribution (QOKD). The parameter [Formula: see text] was added to the prepared quantum state. The average number of the key bits Alice obtained can locate on any fixed value by adjusting the parameter [Formula: see text] whatever the database size was. In addition, our protocol is flexible and fault-tolerant.

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Orts, F., G. Ortega, and E. M. E.M. Garzon. "Efficient reversible quantum design of sig-magnitude to two's complement converters." Quantum Information and Computation 20, no. 9&10 (August 2020): 747–65. http://dx.doi.org/10.26421/qic20.9-10-3.

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Despite the great interest that the scientific community has in quantum computing, the scarcity and high cost of resources prevent to advance in this field. Specifically, qubits are very expensive to build, causing the few available quantum computers are tremendously limited in their number of qubits and delaying their progress. This work presents new reversible circuits that optimize the necessary resources for the conversion of a sign binary number into two's complement of N digits. The benefits of our work are two: on the one hand, the proposed two's complement converters are fault tolerant circuits and also are more efficient in terms of resources (essentially, quantum cost, number of qubits, and T-count) than the described in the literature. On the other hand, valuable information about available converters and, what is more, quantum adders, is summarized in tables for interested researchers. The converters have been measured using robust metrics and have been compared with the state-of-the-art circuits. The code to build them in a real quantum computer is given.

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Lokesh A, Dr, Mr Maria Navin J R, Mr Balaji K, and Mr Pradeep M. "Designing and analyzing highly scalable and reliable of full fledged parallel algorithm for computing strongly connected com-ponents to analyze social graphs." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 374. http://dx.doi.org/10.14419/ijet.v7i2.12.11354.

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With the recent advent of Big Data, developing efficient distributed algorithms for computing Strongly Connected Components of a large dataset has received increasing interests. For example, social networks, information networks and communication networks such as the communities of people that have formed on those networks, what community a person belongs or finding cyclic de-pendencies in the graph.Apache Giraph is an open-source implementation of Google’s Pregel. It is an iterative and real-time graph processing engine designed to be scalable, fault tolerant and highly efficient. This framework provides an accurate platform for the development of parallel algorithms in a distributed environ-ment. It adopts a vertex-centric programming model inspired by Bulk Synchronous Parallel model. A strongly connected component is a maximal sub graph in which all vertices are reachable from every other vertex. Maximal means that it is the largest possible sub graph. It is not possible to find another vertex anywhere in the graph such that it could be added to the sub graph and all the verti-ces in the sub graph would still be connected. In a directed graph G, a pair of vertices u and v are said to be strongly connected to each other if there is a path in each direction between them. Here, we have implemented a parallel algorithm which is based on the new paradigm of graph decomposi-tion for computing strongly connected components. The final outcome mainly focuses on the reduc-tion of total communication costs.

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PARHAMI, BEHROOZ. "PERIODICALLY REGULAR CHORDAL RINGS ARE PREFERABLE TO DOUBLE-RING NETWORKS." Journal of Interconnection Networks 09, no. 01n02 (March 2008): 99–126. http://dx.doi.org/10.1142/s0219265908002187.

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The susceptibility of ring networks to disconnection as a result of one or two node/link failures has led to a number of proposals to increase the robustness of such networks. One class of proposals, discussed primarily in the networking and communication communities, but also advocated for use in parallel and distributed systems, involves the provision of a second ring to improve system throughput during normal operation and to make alternate paths available in the event of node or link failures. With regard to the advantages just listed, chordal rings are quite similar to double-ring networks, and periodically regular chordal (PRC) rings offer the added benefit of smaller node degree compared with node-symmetric chordal rings of comparable diameters. In this paper, we note that certain double-ring networks are isomorphic to suitably constructed PRC rings, while other varieties correspond to PRC rings that closely approximate their static and dynamic attributes. These results, combined with greater flexibility and other advantages for the PRC-ring family of networks, demonstrate that PRC rings are preferable to double-ring networks in virtually all application contexts. A byproduct of our observations on the relationships among double-ring networks, generalized Petersen graphs, and PRC rings is that by amalgamating known results for these network classes, many more tools and techniques become applicable to the analysis and synthesis of robust ring networks for parallel and distributed computing. As examples of new results that can be developed with this viewpoint, we present near-optimal and fault-tolerant routing algorithms for our PRC ring networks.

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"Design of a Fault Tolerant Razor Flip Flop Sklansky Adder for Delay Reduction in FIR Filter." International Journal of Innovative Technology and Exploring Engineering 8, no. 9 (July 10, 2019): 2647–51. http://dx.doi.org/10.35940/ijitee.i8986.078919.

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Basically, to reduce the failure rate in the system, we need to introduce the fault tolerant system. Because of multiple faults occurred in the system, the system will increase the area. To employ the adder architecture, different algorithms are used in digital signal processing. By introducing the fault tolerant system, the reliability of the proposed system will increase. So in this paper we introduced the design of fault tolerant razor flip flop using SKLANSKY adder for delay reduction in FIR filter. The razor flip flop will increase the energy efficiency of proposed system. This flip flop will store the information by latching the circuit. The SKLANSKY adder is the part of arithmetic logic unit. In proposed system, all bits are summed and followed to the fault tolerance system,. This fault tolerance system will detect the error and give efficient output. Hence compared to existed system, the proposed system gives high performance and accuracy in terms of delay.

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"Improved Fault Tolerant ALU Architecture." International Journal of Engineering and Advanced Technology 8, no. 6 (August 30, 2019): 1477–84. http://dx.doi.org/10.35940/ijeat.f8131.088619.

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The birth to IC technology by Moore became driving force behind civilization and it spent almost 45 years successfully without any scruple in mind. It affected life of a mankind and brought pivotal moment in civilization. Now technology is hitting atomic levels and soon limits will be touched. Therefore time has come to rethink for an alternative solution that may slow down exponential rate demonstrated by Moore. Reversible computing is emerging as a superior technology and soon will be future of all smart computing applications. Although renowned physicists and computer scientists have investigated remarkable results in reversible logic based arithmetic logic unit (ALU) designing still research in the field of reversible ALU with add on fault tolerance is under progress and there is scope of further optimization. This paper aims in investigation of improved fault tolerant ALU architecture using parity preserving fault tolerant reversible adder (FTRA), double Feynman and conservative Fredkin gates. Performance evaluation of proposed architecture is done in respect of functionality, garbage lines, ancillary lines, quantum cost and number of gates. The quantum cost of all gates is verified using RCViewer+ tool. The proposed architecture is coded in Verilog HDL, Synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2.

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"FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures." International Journal of Engineering and Advanced Technology 9, no. 4 (April 30, 2020): 549–51. http://dx.doi.org/10.35940/ijeat.d7062.04942.

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The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies

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