Journal articles: 'Field effect transistor MOSFET'

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Hashim, Muhaimin Bin Mohd, AHM Zahirul ALAM, and Naimah Binti Darmis. "EFFECT OF FERRO ELECTRIC THICKNESS ON NEGATIVE CAPACITANCE FET (NCFET)." IIUM Engineering Journal 22, no. 1 (January 30, 2021): 339–46. http://dx.doi.org/10.31436/iiumej.v22i1.1814.

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Conventional Field Effect Transistor (FET) are well known to require at least 60mV/decade at 300K change in the channel potential to change the current by a factor of 10. Due to this, 60mV/decade becomes the bottleneck of this day transistor. A comprehensive study of the Negative Capacitance Field Effect Transistor (NCFETis presented. This paper shows the effect of ferroelectric material in MOSFET structure by replacing the insulator in the conventional MOSFET. It should be possible to obtain a steeper subthreshold swing (SS) compared to the one without a ferroelectric material layer, thus breaking the fundamental limit on the operating voltage of MOSFET. 27% of the subthreshold slope reduction is observed by introducing ferroelectric in the dielectric layer compared to the conventional MOSFETs. Hence, the power dissipation in MOSFET can be mitigated and shine to a new technology of a low voltage/low power transistor operation. ABSTRAK: Transistor Kesan Medan Konvensional (FET) terkenal memerlukan sekurang-kurangnya 60mV / dekad pada 300K perubahan pada saluran yang berpotensi untuk mengubah arus dengan faktor 10. Oleh kerana itu, 60mV / dekad menjadi hambatan transistor hari ini. Kajian komprehensif mengenai Negative Capacitance Field Effect Transistor (NCFETis dikemukakan. Makalah ini menunjukkan kesan bahan ferroelektrik dalam struktur MOSFET dengan mengganti penebat dalam MOSFET konvensional. Sebaiknya dapatkan swing swing subthreshold (SS) yang lebih curam berbanding dengan satu tanpa lapisan bahan ferroelektrik, sehingga melanggar had asas pada voltan operasi MOSFET. 27% pengurangan cerun subthreshold diperhatikan dengan memperkenalkan ferroelektrik di lapisan dielektrik berbanding dengan MOSFET konvensional. Oleh itu, pelesapan daya dalam MOSFET dapat dikurangkan dan bersinar dengan teknologi baru operasi transistor voltan rendah / kuasa rendah.

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Natarajamoorthy, Mathan, Jayashri Subbiah, Nurul Ezaila Alias, and Michael Loong Peng Tan. "Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design." Journal of Nanotechnology 2020 (April 30, 2020): 1–7. http://dx.doi.org/10.1155/2020/7608279.

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The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

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Dinh, Hien Sy, and Trung Hoang Huynh. "SIMULATING CURRENT - VOLTAGE CHARACTERISTICS OF MOLECULAR TRANSISTOR FIELD EFFECT TRANSISTOR." Science and Technology Development Journal 12, no. 13 (July 15, 2009): 5–12. http://dx.doi.org/10.32508/stdj.v12i13.2389.

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Molecular Field Effect Transistor (MFET) is a promising alternative candidate of traditional MOSFET in future due to its small size, low power consumption and high speed. In this work, we introduce a model of three-terminal MFET. The structure of the MFET is in shape like traditional MOSFET, but its conductive channel is replaced by a benzene-1,4-dithiolate molecule. We use non-equilibrium Green's function method to compute transport function of charges and ultimately, the current-voltage (1-V) characteristics. The program is written by using graphic user guide (GUI) in Matlab. We have found significant difference of I-V characteristics between MOSFET and MFET. In addition, impacts of types of material, temperature, and bias on I-V characteristics of the MFET have been considered. Using GUI in Matlab, obtained results of simulations are intuitively displayed.

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Gu, Jie, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang, et al. "Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs." Nanomaterials 11, no. 2 (January 26, 2021): 309. http://dx.doi.org/10.3390/nano11020309.

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A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

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NASTAUSHEV, Yu V., T. A. GAVRILOVA, M. M. KACHANOVA, O. V. NAUMOVA, I. V. ANTONOVA, V. P. POPOV, L. V. LITVIN, D. V. SHEGLOV, A. V. LATYSHEV, and A. L. ASEEV. "FIELD EFFECT NANOTRANSISTOR ON ULTRATHIN SILICON-ON-INSULATOR." International Journal of Nanoscience 03, no. 01n02 (February 2004): 155–60. http://dx.doi.org/10.1142/s0219581x04001936.

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Peculiarities of the fabrication of field effect transistor (FET) at nanoscaled size on ultrathin silicon-on-insulator (SOI) was studied in details. Two types of FET transistor were successfully realized: in-plane-gate FET (IPGFET) with 40 nm minimum channel size and multichannel top-gate MOSFET on silicon-on-insulator. The deep submicron top-gate of Ti/Au embraces each of the conductive oxidized silicon wires placed with 400 nm pitch. The type and concentration of carries in a conductive channel of the ultrathin SOI was controlled by a bottom gate. The fabricated transistors demonstrated high transconductance and low threshold voltage. Some results of electron properties of the nano-FET transistors are presented.

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Hamieh, S. "Improving the RF Performance of Carbon Nanotube Field Effect Transistor." Journal of Nanomaterials 2012 (2012): 1–7. http://dx.doi.org/10.1155/2012/724121.

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Compact model of single-walled semiconducting carbon nanotube field-effect transistors (CNTFETs) implementing the calculation of energy conduction subband minima under VHDLAMS simulator is used to explore the high-frequency performance potential of CNTFET. The cutoff frequency expected for a MOSFET-like CNTFET is well below the performance limit, due to the large parasitic capacitance between electrodes. We show that using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance.

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Islam, Md Rabiul, Md Kamrul Hasan, Md Abdul Mannan, M. Tanseer Ali, and Md Rokib Hasan. "Gate Length Effect on Gallium Nitride Based Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor." AIUB Journal of Science and Engineering (AJSE) 18, no. 2 (August 31, 2019): 73–80. http://dx.doi.org/10.53799/ajse.v18i2.43.

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We have investigated the performance of Gallium Nitride (GaN) based Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Atlas Device Simulation Framework -Silvaco has been used to access Non-Equilibrium Green Function to distinguish the transfer characteristics curve, ON state current (ION), OFF-state current (IOFF), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing, Electron Current Density, Conduction Band Energy and Electric Field. The concept of Solid state device physics on the effect of gate length studied for the next generation logic applications. GaN-based DG MOSFETs shows better performance than Si-based Single gate MOSFETs. The proposed device has drawn the attention over conventional SG-MOSFET due to fas switching performance. The device turn on and turn off voltage is respectively VGS=1V(On state) and VGS-0V(OFF State). To validate our simulation tool and model results, previous research model has been investigated using Silvaco Atlas and the results obtained are compared to the previous results.

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Ahn, Tae Jun, and Yun Seop Yu. "Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4252–57. http://dx.doi.org/10.1166/jnn.2021.19388.

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We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

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Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

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Tan, Michael Loong Peng. "Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs." Journal of Nanomaterials 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/831252.

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Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in silicon MOSFET while sustaining the same unit area at higher current density.

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11

Ahn, Tae Jun, and Yun Seop Yu. "Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET." Applied Sciences 11, no. 1 (December 30, 2020): 277. http://dx.doi.org/10.3390/app11010277.

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In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (TILD) and gate channel length (Lg) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as TILD decreases and they increase as Lg increases, and thus there is a strong coupling in M3INV at the range of TILD ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same TILD and Lg. The switching threshold voltage (Vm) and noise margins (NMs) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the Vm variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of Vm, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL.

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Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Ebiike, Yuji, Toshikazu Tanioka, Masayuki Furuhashi, Ai Osawa, and Masayuki Imaizumi. "Characteristics of High-Threshold-Voltage Low-Loss 4H-SiC MOSFETs with Improved MOS Cell Structure." Materials Science Forum 858 (May 2016): 829–32. http://dx.doi.org/10.4028/www.scientific.net/msf.858.829.

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High threshold voltage low loss 600 V 4H-SiC MOSFETs have been fabricated successfully using a re-oxidation technique for gate oxides and an n-type doping in the Junction Field Effect Transistor region of the MOSFET with shrunk MOS cells. The MOSFET has exhibited a high threshold voltage of more than 4 V and a low specific on resistance of 5.2 mΩ·cm2 at 25 °C. The MOSFET has also exhibited a sufficient blocking characteristic at VG of 0 V at 150 °C. High speed switching with low switching losses has been demonstrated successfully using the MOSFET at 150 °C.

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Li, Hui, Renze Yu, Yi Zhong, Ran Yao, Xinglin Liao, and Xianping Chen. "Design of 400 V Miniature DC Solid State Circuit Breaker with SiC MOSFET." Micromachines 10, no. 5 (May 10, 2019): 314. http://dx.doi.org/10.3390/mi10050314.

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Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have the advantages of high-frequency switching capability and the capability to withstand high temperatures, which are suitable for switching devices in a direct current (DC) solid state circuit breaker (SSCB). To guarantee fast and reliable action of a 400 V DC SSCB with SiC MOSFET, circuit design and prototype development were carried out. Taking 400V DC microgrid as research background, firstly, the topology of DC SSCB with SiC MOSFET was introduced. Then, the drive circuit of SiC MOSFET, fault detection circuit, energy absorption circuit, and snubber circuit of the SSCB were designed and analyzed. Lastly, a prototype of the DC SSCB with SiC MOSFET was developed, tested, and compared with the SSCB with Silicon (Si) insulated gate bipolar transistor (IGBT). Experimental results show that the designed circuits of SSCB with SiC MOSFET are valid. Also, the developed miniature DC SSCB with the SiC MOSFET exhibits faster reaction to the fault and can reduce short circuit time and fault current in contrast with the SSCB with Si IGBT. Hence, the proposed SSCB can better meet the requirements of DC microgrid protection.

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Vlasov, Yuri. "Membrane-oxide semiconductor field-effect transistor (MOSFET) sensors." Mikrochimica Acta 104, no. 1-6 (January 1991): 363–77. http://dx.doi.org/10.1007/bf01245522.

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FOBELETS, K., P. W. DING, Y. SHADROKH, and J. E. VELAZQUEZ-PEREZ. "ANALOG AND DIGITAL PERFORMANCE OF THE SCREEN-GRID FIELD EFFECT TRANSISTOR (SGRFET)." International Journal of High Speed Electronics and Systems 18, no. 04 (December 2008): 783–92. http://dx.doi.org/10.1142/s012915640800576x.

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The Screen-Grid Field Effect Transistor (SGrFET) is a planar MOSFET-type device with a gating configuration consisting of metal cylindrical fingers inside the channel perpendicular to the current flow. The SGrFET operates in a MESFET mode using oxide insulated gates. The multi-gate configuration offers advantages for both analog and digital applications, whilst the gate cylinder holes can be exploited for bio-applications. In this manuscript TCAD results are presented on the analog and digital performance of the Screen-Grid Field Effect Transistor. The results are compared to the operation of an SOI-MOSFET and a finFET.

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Okada, Masakazu, Teruaki Kumazawa, Yusuke Kobayashi, Masakazu Baba, and Shinsuke Harada. "Highly Efficient Switching Operation of 1.2 kV-Class SiC SWITCH-MOS." Materials Science Forum 1004 (July 2020): 795–800. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.795.

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A 1.2 kV silicon carbide (SiC) SBD-wall-integrated trench metal oxide semiconductor field effect transistor (MOSFET) (SWITCH-MOS) exhibits potential for solving body-PiN-diode-related problems such as bipolar forward degradation and switching losses among relatively low breakdown voltage 1.2 kV-class SiC MOSFETs. In this study, dynamic characteristics and switching losses of the SWITCH-MOS and conventional MOSFET are compared. The results demonstrate that the SWITCH-MOS exhibits smaller turn-on and reverse recovery losses than a conventional MOSFET at high temperatures. Ruggedness performances such as short circuit and unclamped inductive switching capabilities were evaluated.

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Daves, W., A. Krauss, V. Häublein, A. J. Bauer, and L. Frey. "Electrical Characterization of Lateral 4H-SiC MOSFETs in the Temperature Range of 25 to 600 °C for Harsh Environment Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000108–14. http://dx.doi.org/10.4071/hiten-paper4-wdaves.

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In this work, we investigated lateral 4H-SiC-based metal oxide field-effect transistors (MOSFET) for the use as transducers in harsh environments. Inversion channel (IC) as well as buried channel (BC) MOSFETs were fabricated by means of different epi-layer doping and ion implantation. Stacked SiO2/Si3N4 dielectrics and a sputtered Ti/TaSix/Pt contact metallization were used. The devices were characterized by means of current-voltage and capacitance-voltage testing up to 600 °C. The thermal stability of the transistor characteristics and the factors limiting the MOSFET mobility were analyzed and discussed. The effective barrier height for Fowler-Nordheim tunneling extrapolated at high fields (> 7 MV/cm) decreased of about 1 eV between 25 and 500 °C. At high temperatures, the Poole-Frenkel contribution to the leakage current became significant already in the mid-field range. The prolonged operation of MOSFETs at 500 °C indicated that sufficient MOS reliability can be achieved only by a minimization of the necessary gate bias. The lifetime was ~25 h when a stress field of 3.5 MV/cm was applied at 500 °C. When the stress field was reduced to 0.5 MV/cm, a lifetime > 300 h was found. A degradation of the drain current was observed during the prolonged operation independently of the biasing conditions. This was attributed to a degradation of the ohmic contacts.

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BLALOCK, BENJAMIN J., SORIN CRISTOLOVEANU, BRIAN M. DUFRENE, F. ALLIBERT, and MOHAMMAD M. MOJARRADI. "THE MULTIPLE-GATE MOS-JFET TRANSISTOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 511–20. http://dx.doi.org/10.1142/s0129156402001423.

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A new SOI device, the MOS-JFET, has been developed that combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body. A unique attribute of the MOS-JFET is that it can be viewed as a four gate transistor (two side junction-based gates, the top MOS gate, and the back gate activated by SOI substrate biasing). Each of these four gates can control the conduction characteristics of the transistor. This novel transistor's multiple gate inputs give rise to exciting circuit opportunities for analog, RF, mixed-signal, and digital applications. Measured results of MOS-JFET transistors, fabricated in a conventional partially-depleted SOI technology, demonstrate that the device is fully operational. From the experiments and systematic 2-D simulations, typical regions of operation are identified. These results indicate that optimum performance is reached when the MOS and junction field-effects are combined.

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Lin, Jing-Jenn, Ji-Hua Tao, and You-Lin Wu. "Subthreshold Characteristics of a Metal-Oxide–Semiconductor Field-Effect Transistor with External PVDF Gate Capacitance." Crystals 9, no. 12 (December 14, 2019): 673. http://dx.doi.org/10.3390/cryst9120673.

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An organic ferroelectric capacitor, using polyvinylidene difluoride (PVDF) as the dielectric, was fabricated. By connecting the PVDF capacitor in series to the gate of a commercially purchased metal-oxide–semiconductor field-effect transistor (MOSFET), drain current (ID)–drain voltage (VD) characteristics and drain current (ID)–gate voltage (VG) characteristics were measured. In addition, the subthreshold slopes of the MOSFET were determined from the ID–VG curves. It was found that the subthreshold slope could be effectively reduced by 23% of its original value when the PVDF capacitor was added to the gate of the MOSFET.

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Kang, Seok Jung, Jeong-Uk Park, Kyung Jin Rim, Yoon Kim, Jang Hyun Kim, Garam Kim, and Sangwan Kim. "Analysis of Channel Area Fluctuation Effects of Gate-All-Around Tunnel Field-Effect Transistor." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4409–13. http://dx.doi.org/10.1166/jnn.2020.17792.

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In this manuscript, channel area fluctuation (CAF) effects on turn-on voltage (Von) and subthreshold swing (SS) in gate-all-around (GAA) nanowire (NW) tunnel field-effect transistor (TFET) with multi-bridge-channel (MBC) have been investigated for the first time. These variations occur because oblique etching slope makes various elliptical-shaped channels in MBC-TFET. Since TFET is promising candidates to succeed metal-oxide-semiconductor FETs (MOSFET), these variation effects have been compared to MOSFET. Furthermore, Ge homojunction TFET, one of the solutions to increase on-state current in TFET and improve SS also has been simulated using technology computer-aided design (TCAD) simulation. The results would be worth reference for future study about GAA NW TFETs.

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Zhai, Mingjing, Yuan Yang, Yang Wen, Wenqing Yao, and Yuan Li. "Characterization analysis and gate driver design for 1200 V 10 A SiC MOSFET." Modern Physics Letters B 32, no. 34n36 (December 30, 2018): 1840080. http://dx.doi.org/10.1142/s0217984918400808.

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Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) can work at high switching frequency with low switching loss compared with Si insulated gate bipolar transistor (IGBT). Although Si IGBT and SiC MOSFET have the same MOS-gate structure, the transient characteristics and the gate driver requirements for Si IGBT and SiC MOSFET are different. In order to fully utilize the advantages of SiC MOSFET, the gate driver of SiC MOSFET needs to be optimized to meet some special driving requirements. The paper aims to analyze the characteristics for the new generation of wide band gap semiconductor device SiC MOSFET and proposes a novel gate driver for SiC MOSFET. Meanwhile, the driving protection circuit of SiC MOSFET is also investigated. The performances of the proposed gate driver have been experimentally evaluated by double pulse test (DPT). In addition, the effect of different external capacitors [Formula: see text] and external driving resistances [Formula: see text] on the switch characteristics of SiC MOSFET is analyzed in detail.

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Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (May 20, 2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nanodimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

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Stanković, Srboljub J., R. D. Ilić, M. Petrović, B. Lončar, and A. Vasić. "Radiological Characterization of Semiconductor Materials in Field Effect Transistor Dosimeter by Monte Carlo Method." Materials Science Forum 518 (July 2006): 361–66. http://dx.doi.org/10.4028/www.scientific.net/msf.518.361.

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The use of semiconductor materials in radiation processing, radiation therapy and diagnostics, and detection of cosmic radiation motivated development of numerical methods for its radiological characterization. This paper presents the application of the Monte Carlo method using the FOTELP-2K4 code for radiological characterization of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) dosimeter. The advantages of MOSFET dosimeters include small size, immediate readout, and ease of use for a wide photon energy range. In order to determine the dosimeter response accurately, distribution of the absorbed dose in the MOSFET structure has been investigated. Our results show that the absorbed dose distribution calculated by the presented simulation model compares well with the published data.

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TIWARI, SANDIP, A. KUMAR, and J. J. WELSER. "STRADDLE-GATE TRANSISTOR: A MOSFET IN THE LIMIT OF USEFUL FIELD-EFFECT." International Journal of High Speed Electronics and Systems 10, no. 01 (March 2000): 231–45. http://dx.doi.org/10.1142/s0129156400000271.

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For transistor, the limit of usable field-effect is defined by tunneling between the source and the drain - the mechanism that competes with field-effect as device dimensions shrink to near deBroglie wavelength. This is a more fundamental constraint in the operation of a field-effect transistor than random dopants, oxide thickness, doping magnitudes and depth, gate resistivity, soft-error rates, etc. We describe here a MOSFET structure, the straddle-gate transistor, that uses inversion regions as virtual source and drain, operates within the limits placed by the other constraints, and operates at acceptable power levels with good power gain and output conductance at 10 nm channel lenth. Experimental behavior of the straddle geometry are also described to summarized the advantages accrued using electron injection from the thin inversion regions.

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Sinha, Sanjeet Kumar, and Saurabh Chaudhury. "Effect of Device Parameters on Carbon Nanotube Field Effect Transistor in Nanometer Regime." Journal of Nano Research 36 (November 2015): 64–75. http://dx.doi.org/10.4028/www.scientific.net/jnanor.36.64.

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In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

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Debbarma, M., S. Das, J. Pal, S. Debbarma, R. Paul, P. K. Das, T. Dutta, and K. P. Ghatak. "Gate Capacitance in Quantum Metal-Oxide-Semiconductor Field-Effect Transistor Devices of Technologically Important Materials." Advanced Science, Engineering and Medicine 11, no. 12 (December 1, 2019): 1161–78. http://dx.doi.org/10.1166/asem.2019.2477.

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The Heisenberg's scientific theory of quantum science since its beginning has been proved to be instrumental in unlocking varied vital quantum phenomena. In what follows the Heisenberg's scientific theory has been used to derive the expressions for the gate capacitance in Quantum MOSFET Devices manufactured from completely different technologically vital nonstandard materials by formulating the 2D electron statistics under very low temperature so that the Fermi function tends to unity. For numerical computations we take Cd3As2, the best quality very high mobility semiconductor and non-linear optical (e.g., CdGeAs2) compounds from which quantum MOSFET devices are made of by using all types of anisotropies of band structures in addition to splitting of bands due to large fields of the crystals inside the frame work of Kane's matrix methodology that successively generates new two dimensional electron energy versus wave vector relation for both low and very large externally applied electric field of force respectively. Under many special conditions, the corresponding statistics and therefore the gate capacitance for the quantum MOSFETs, whose e–ks equation (e is carrier energy and ks is the 2D wave vector) are defined by various models of III–V semiconducting samples originally derived by Kane create special cases of our extended formalism. It's been found taking quantum MOSFETs of CdGeAs2, InAs, InSb, Hg1–xCdxTe and In1–xGaxAs yP1–y lattice matched to InP that the gate capacitance at the electrical quantum limit will exhibit monotonic increasing function with changing field at the surface, the applied voltage at the gate for each of the compounds and therefore the actual results have one to one correspondence with the energy band constants showing an inclination of asymptotic results at comparatively large values of the independent variables for all the cases. The gradient rates for all curves change from one material to a different material. With decreasing alloy composition, the gate capacitance will increase for each of quantum confined MOSFETs made of various alloy compounds. For the aim of coherent presentation we've got conjointly planned the periodical Fermi energy at high field of force limits and gate voltage for few quantum confined MOSFETs.

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Rathore, Pradeep Kumar, Brishbhan Singh Panwar, and Jamil Akhtar. "A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique." Microelectronics International 32, no. 2 (May 5, 2015): 81–95. http://dx.doi.org/10.1108/mi-11-2014-0048.

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Purpose – The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors. Design/methodology/approach – This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge. Findings – The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits. Originality/value – The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

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Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.

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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing.

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Kumar, Nandhaiahgari Dinesh, Rajendra Prasad Somineni, and CH Raja Kumari. "Design and analysis of different full adder cells using new technologies." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (July 1, 2020): 116. http://dx.doi.org/10.11591/ijres.v9.i2.pp116-124.

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<span>CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.</span>

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John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.

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Takakubo, Kawori, and Hajime Takakubo. "Improvement of Subthreshold MOSFET Characteristics Employing Field Effect Bipolar Transistor." IEEJ Transactions on Electronics, Information and Systems 129, no. 8 (2009): 1490–98. http://dx.doi.org/10.1541/ieejeiss.129.1490.

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Hasan, Md Sakib, Samira Shamsir, Mst Shamim Ara Shawkat, Frances Garcia, and Syed K. Islam. "Multivariate Regression Polynomial: A Versatile and Efficient Method for DC Modeling of Different Transistors (MOSFET, MESFET, HBT, HEMT and G4FET)." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840016. http://dx.doi.org/10.1142/s0129156418400165.

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This work presents multivariate regression polynomial as a versatile and efficient method for DC modeling of modern transistors with very different underlying physics including MOSFET (metal-oxide-semiconductor field-effect transistor), MESFET (metal–semiconductor field-effect transistor), HBT (heterojunction bipolar transistor), HEMT (High-electron-mobility transistor) and a novel silicon-on-insulator four-gate transistors (G4FET). A set of available data from analytic solution, TCAD simulation, and experimental measurements for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. The developed model expresses the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of training data set. The continuity of the resulting polynomial and its first and second order derivatives make it particularly suitable for implementation in a circuit simulator. The model also provides a method for further simplification based on prior knowledge of the underlying physical mechanism and shows excellent predictive capability for different kinds of devices. This can be very useful for modeling deep-submicron emerging devices for which any closed-form analytical solution is not yet available.

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Vimala, P., and N. R. Nithin Kumar. "Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor." Journal of Nano Research 64 (November 2020): 115–22. http://dx.doi.org/10.4028/www.scientific.net/jnanor.64.115.

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The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

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Ahn, Tae Jun, and Yun Seop Yu. "Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs." Micromachines 11, no. 10 (September 24, 2020): 887. http://dx.doi.org/10.3390/mi11100887.

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The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

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KUMAR, K. KEERTI, and N. BHEEMA RAO. "POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450109. http://dx.doi.org/10.1142/s0218126614501096.

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In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

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Vimala, Palanichamy, and T. S. Arun Samuel. "Effect of Gate Engineering and Channel Length Variation in Surrounding Gate MOSFETs." Journal of Nano Research 63 (June 2020): 134–43. http://dx.doi.org/10.4028/www.scientific.net/jnanor.63.134.

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In this paper, the digital and analog performance for Double Material Gate Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (DM SG MOSFET) has been analyzed. A detailed study of DM SG MOSFET is performed for different channel length ratio's. The comparison analysis on surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried with respect to the silicon dioxide and hafnium dioxide based device. It has been found from the simulation results that HfO2 dielectric used DM SG TFET provides better performance than SiO2 dielectric used DM SG TFET. Also it has been observed from the presented results that the transconductance is 45.32 at 1:3 channel length ratio for DG SG MOSFET.

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Kamajaya, Leonardo, Fitri Fitri, and Herman Hariyadi. "Rancang bangun sensor PH menggunakan gold – extended gate field effect transistor." JURNAL ELTEK 18, no. 1 (July 31, 2020): 78. http://dx.doi.org/10.33795/eltek.v18i1.216.

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ABSTRAK Banyak peneliti telah mengembangkan berbagai jenis biosensor, salah satunya sensor pH memanfaatkan MOSFET. Penelitian awal digunakan ISFET sebagai pendeteksi derajat keasamaan, seiring perkembangan teknologi digunakan EGFET sebagai media pendeteksi pH. Karena kelebihan dari EGFET yang lebih stabil dan tahan terhadap gangguan dari luar. Penelitian ini bertujuan untuk mengetahui performansi dari sensor pH berbasis Gold-EGFET dengan tingkat ketebalan lapisan membrane sensor yang berbeda pada pengukuran menggunakan pH buffer yang berbeda. Penelitian ini akan menguji tingkat sensitivitas dan linearitas dari pengukuran pH dengan ketebalan lapisan deteksi dari membrane sensor. ABSTRACT Many researchers have developed various types of biosensors, one of which is a pH sensor utilizing MOSFET. Initial research used ISFET as a detector of the degree of acidity, along with technological developments used EGFET as a pH detection medium because the advantages of EGFET are more stable and resistant to outside interference. This study aims to determine the performance of a Gold-EGFET-based pH sensor with a different level of membrane sensor thickness on measurements using different pH buffers. This study will test the sensitivity and linearity of the pH measurement with the thickness of the detection layer of the sensor membrane.

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Cui, Mei Ting, Jin Yuan Li, Xiao Liang Yang, and Yu Jie Du. "The Effect of Circuit Parameters on Reverse Biased Safe Operating Area of SiC MOSFET." Materials Science Forum 954 (May 2019): 170–75. http://dx.doi.org/10.4028/www.scientific.net/msf.954.170.

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In recent years, silicon carbide (SiC) and other wide band gap semiconductors have become one of the strategic commanding heights in the global high-technology field. Silicon Carbide (SiC) metal-oxide-semiconductor field effect transistor (MOSFET) has shown excellent electrical properties. When applying SiC MOSFET, the safe operation area (SOA) need to be considered. In this paper, the effect of circuit parameters on RBSOA of SiC MOSFET is researched. Firstly, the principle of RBSOA is introduced. Secondly, the equivalent circuit of the single-pulse test circuit is shown to study on the effect of gate resistance and gate voltage on RBSOA. Thirdly, the simulation of variable parameters are done to research the variation trend. Finally, experiments are done to verify the results which can make an important influence on safe operation of SiC MOSFET and help choose suitable circuit parameters.

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Kyaw, Wut Hmone, and May Nwe Myint Aye. "Simulation of Energy Bands for Metal and Semiconductor Junction." Journal La Multiapp 1, no. 2 (June 21, 2020): 7–13. http://dx.doi.org/10.37899/journallamultiapp.v1i2.107.

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This paper presents the metal-semiconductor band structure analysis for metal-oxide semiconductor field effect transistor (MOSFET). The energy bands were observed at metal-semiconductor and semiconductor-metal junctions. The simulation results show energy variations by using gallium-nitride (GaN) material. Gallium nitride based MOSFETs have some special material properties and wide band-gap. From the energy band, the condition of contact potential, conduction and valence band-edges can be analyzed. The computerized simulation results for getting the band layers are investigated with MATLAB programming language.

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Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.

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AbstractTraditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.

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Vimala, Palanichamy, and N. R. Nithin Kumar. "Explicit Quantum Drain Current Model for Symmetric Double Gate MOSFETs." Journal of Nano Research 61 (February 2020): 88–96. http://dx.doi.org/10.4028/www.scientific.net/jnanor.61.88.

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In this article, an analytical model for Double gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET) is developed including Quantum effects. The Schrodinger–Poisson’s equation is used to develop the analytical Quantum model using Variational method. A mathematical expression for inversion charge density is obtained and the model was developed with quantum effects by means of oxide capacitance for different channel thickness and gate oxide thickness. Based on inversion charge density model the compact model is developed for transfer characteristics, transconductance and C-V curves of DG MOSFETs. The results of the model are compared to the simulated results. The comparison shows the accuracy of the proposed model.

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Chaudhry, Amit, and Nath Roy. "A comparative study of hole and electron inversion layer quantization in MOS structures." Serbian Journal of Electrical Engineering 7, no. 2 (2010): 185–93. http://dx.doi.org/10.2298/sjee1002185c.

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In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.

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Yano, Hiroshi, Yuki Oshiro, Dai Okamoto, Tomoaki Hatayama, and Takashi Fuyuki. "Instability of 4H-SiC MOSFET Characteristics due to Interface Traps with Long Time Constants." Materials Science Forum 679-680 (March 2011): 603–6. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.603.

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Instability of metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics was evaluated by DC and pulse current-voltage (I-V) measurements. MOSFETs with nirided gate oxides were fabricated on C-face 4H-SiC. Their interfaces have near interface traps (NITs) with long time constants, depending on the cooling down process after nitridation. Such devices exhibited a large hysteresis in DC I-V and a large transient current in pulse I-V measurements. These phenomena can be explained by the charge state of NITs due to capture/emission of electrons in the channel.

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Mukherjee, Kalparupa, Carlo De Santi, Matteo Borga, Karen Geens, Shuzhen You, Benoit Bakeroot, Stefaan Decoutere, et al. "Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization." Materials 14, no. 9 (April 29, 2021): 2316. http://dx.doi.org/10.3390/ma14092316.

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The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

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Kumar, Shashi, Gaddiella Diengdoh Ropmay, Pradeep Kumar Rathore, Peesapati Rangababu, and Jamil Akhtar. "Fabrication and testing of PMOS current mirror-integrated MEMS pressure transducer." Sensor Review 40, no. 2 (November 23, 2019): 141–51. http://dx.doi.org/10.1108/sr-07-2019-0182.

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Purpose This paper aims to describe the fabrication, packaging and testing of a resistive loaded p-channel metal-oxide-semiconductor field-effect transistor-based (MOSFET-based) current mirror-integrated pressure transducer. Design/methodology/approach Using the concept of piezoresistive effect in a MOSFET, three identical p-channel MOSFETs connected in current mirror configuration have been designed and fabricated using the standard polysilicon gate process and microelectromechanical system (MEMS) techniques for pressure sensing application. The channel length and width of the p-channel MOSFETs are 100 µm and 500 µm, respectively. The MOSFET M1 of the current mirror is the reference transistor that acts as the constant current source. MOSFETs M2 and M3 are the pressure-sensing transistors embedded on the diaphragm near the mid of fixed edge and at the center of the square diaphragm, respectively, to experience both the tensile and compressive stress developed due to externally applied input pressure. A flexible square diaphragm having a length of approximately 1,000 µm and thickness of 50 µm has been realized using deep-reactive ion etching of silicon on the backside of the wafer. Then, the fabricated sensor chip has been diced and mounted on a TO8 header for the testing with pressure. Findings The experimental result of the pressure sensor chip shows a sensitivity of approximately 0.2162 mV/psi (31.35 mV/MPa) for an input pressure of 0-100 psi. The output response shows a good linearity and very low-pressure hysteresis. In addition, the pressure-sensing structure has been simulated using the parameters of the fabricated pressure sensor and from the simulation result a pressure sensitivity of approximately 0.2283 mV/psi (33.11 mV/MPa) has been observed for input pressure ranging from 0 to 100 psi with a step size of 10 psi. The simulated and experimentally tested pressure sensitivities of the pressure sensor are in close agreement with each other. Originality/value This current mirror readout circuit-based MEMS pressure sensor is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

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Najam, Faraz, and Yun Yu. "Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope." Electronics 7, no. 11 (October 24, 2018): 275. http://dx.doi.org/10.3390/electronics7110275.

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The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades its subthreshold slope. To avoid the corner effect, a new type of device with dual material gates is presented. The new device, termed the dual-gate (DG) LTEFT (DG-LTFET), avoids the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over the LTFET. The DG-LTFET was evaluated for different device parameters and bench-marked against the LTFET. This work presents the optimum configuration of the DG-LTFET in terms of device dimensions and doping levels to determine the best subthreshold, ON current, and ambipolar performance.

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Dhar, Sarit, Shurui Wang, John R. Williams, Sokrates T. Pantelides, and Leonard C. Feldman. "Interface Passivation for Silicon Dioxide Layers on Silicon Carbide." MRS Bulletin 30, no. 4 (April 2005): 288–92. http://dx.doi.org/10.1557/mrs2005.75.

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AbstractSilicon carbide is a promising semiconductor for advanced power devices that can outperform Si devices in extreme environments (high power, high temperature, and high frequency). In this article, we discuss recent progress in the development of passivation techniques for the SiO2/4H-SiC interface critical to the development of SiC metal oxide semiconductor field-effect transistor (MOSFET) technology. Significant reductions in the interface trap density have been achieved, with corresponding increases in the effective carrier (electron) mobility for inversion-mode 4H-SiC MOSFETs. Advances in interface passivation have revived interest in SiC MOSFETs for a potentially lucrative commercial market for devices that operate at 5 kV and below.

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Kim, Young, Jin Lee, Geon Kim, Taesik Park, HuiJung Kim, Young Cho, Young Park, and Myoung Lee. "Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors." Electronics 7, no. 10 (October 2, 2018): 227. http://dx.doi.org/10.3390/electronics7100227.

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In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar metal-oxide semiconductor field-effect transistor (MOSFET) and silicon on insulator (SOI) structures, even though they have the same doping profile. Two major features of the PiFET are potential condensation and potential modulation by a buried insulator. The potential modulation near the drain region can control the electric field in the overlapped region of the drain and gate, because it causes a high gate-fringing field. Therefore, we suggest guidelines with respect to the optimal PiFET structure.

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Song, Young Suh, Sungmin Hwang, Kyung Kyu Min, Taejin Jang, Yunho Choi, Junsu Yu, Jong-Ho Lee, and Byung-Gook Park. "Electrical and Thermal Performances of Omega-Shaped-Gate Nanowire Field Effect Transistors for Low Power Operation." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4092–96. http://dx.doi.org/10.1166/jnn.2020.17787.

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In this paper, we proposed Omega-Shaped-Gate Nanowire Field Effect Transistor (ONWFET) with different gate coverage ratio (GCR). In order to investigate electrical and self-heating characteristics of the proposed devices, on-current, off-current, subthreshold swing (SS), and operating temperature were examined by using 3D TCAD simulator and compared with nanowire MOSFET (NW-MOSFET). As a result, a possibility of reducing off-current and operating temperature was demonstrated by using the ONWFET with 40% GCR. Therefore, the ONWFET can save power consumption and serve as low power application such as battery-powered portable electronic devices.

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Journal articles on the topic 'Field effect transistor MOSFET'

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