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Journal articles on the topic 'Field-programmable-gate-array pulse width modulation'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Arias, Ricardo, Hernán Mediote, and Hernán Tacca. "Flash FPGA-Based Numerical Pulse-Width Modulator." Advances in Power Electronics 2011 (April 4, 2011): 1–6. http://dx.doi.org/10.1155/2011/215376.

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A pulse-width modulator to drive three-phase AC motors is described. It performs a numerical modulation technique, also known as optimum or calculated modulation, but, in order to reduce hardware resources, a hybrid approach merging that calculated modulation with proportional modulation is proposed. The modulator is tested in a flash-based field programmable gate array (FPGA) implementation.

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2

Muzakkir, Mas’ud Adamu*, Ahmend Danzomo*** Bashir, Agadi Danladi** Tonga, Ahmed** Abubakar, and Hassan* Zakariyya. "FIELD PROGRAMMABLE GATE ARRAY BASED PULSE WIDTH MODULATION CONTROLLER." International Journal of Engineering Sciences & Research Technology 5, no. 2 (2016): 789–98. https://doi.org/10.5281/zenodo.46521.

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A pulse width modulation (PWM) signal controller is implemented in a digital circuit to control the speed of a DC motor. The PWM controller modules are designed by adopting the very high-speed integrated circuit hardware description language (VHDL) and the Xilinx Spartan-3E starter board, field programmable gate array (FPGA). The use of PWM control for DC motors is widely used due to reliable performance. The starting torque, for example, in a DC motor can be higher several orders in magnitude than that for a comparable size AC motor. PWM control for DC motors enables a higher efficient, wide

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3

N., Murali, and Balaji V. "Real Time FPGA Implementation of PWM Chopper Fed Capacitor Run Induction Motor." International Journal of Reconfigurable and Embedded Systems 7, no. 3 (2018): 138–48. https://doi.org/10.11591/ijres.v7.i3.pp138-148.

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This paper presents the performance enhancement of capacitor run induction motor by pulse width modulated AC chopper.The phase angle control faces severe shortfall in the performance improvement for larger triggering angles. In this paper the comparison of phase angle control and sinusoidal pulse width modulation technique is encountered for effective speed control of single phase capacitor run induction motor. The necessary parameters are taken into considerations are higher efficiency, lesser total harmonic distortion and high input power factor. The results are compared by using the simulat

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4

Bonanno, Giovanni. "An Innovative Digital Pulse Width Modulator and Its Field-Programmable Gate Array Implementation." Electronics 14, no. 8 (2025): 1522. https://doi.org/10.3390/electronics14081522.

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Digital pulse-width modulation (DPWM)-based controls are characterized by a non-negligible phase delay due to analog-to-digital (ADC) conversion, sampling time, carrier shape, and algorithm computation time. These delays degrade the performance in closed-loop systems, where the bandwidth must be reduced to avoid instability issues due to the reduced closed-loop phase margin. To mitigate these delays, approaches such as utilizing low-latency ADCs or increasing the sampling frequency have been employed. However, these methods are often costly and do not address the fundamental delay issues inher

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5

Peerzada, Ridwan ul Zaman, and Hussain Abid. "FPGA Controlled High Gain Multiphase Bi-Directional DC-DC Converter (BDC) for Energy Storage of Solar Power." Recent Trends in Control and Converter 6, no. 3 (2023): 26–39. https://doi.org/10.5281/zenodo.10280883.

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<i>The paper is proposing the field programmable gate array (FPGA) controlled non-isolated multiphase Bi-directional DC-DC converter operating under ZVS with pulse width modulation (PWM) technique and presents the simulation results for the same. The converter is designed at high gain in the both buck and boost operations. The algorithim implemented for charging and discharging control is considered efficient for the battery storage systems.</i>

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6

Prabaharan, Nataraj, V. Arun, Padmanaban Sanjeevikumar, Lucian Mihet-Popa, and Frede Blaabjerg. "Reconfiguration of a Multilevel Inverter with Trapezoidal Pulse Width Modulation." Energies 11, no. 8 (2018): 2148. http://dx.doi.org/10.3390/en11082148.

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This paper presents different multi-carrier unipolar trapezoidal pulse width modulation strategies for a reduced switch asymmetrical multilevel inverter. The different strategies are phase disposition, alternative phase opposition and disposition, and carrier overlapping and variable frequency that involve triangular waves as carriers with a unipolar trapezoidal wave as a reference. The reduced switch, asymmetrical multilevel inverter operation was examined for generating the seven-level output voltage using Matlab/Simulink 2009b and the results were verified with a real-time laboratory-based

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7

Murali, N., and V. Balaji. "Real time FPGA Implementation of PWM Chopper Fed Capacitor Run Induction Motor." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (2018): 132. http://dx.doi.org/10.11591/ijres.v7.i3.pp132-142.

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<span>This paper presents the performance enhancement of capacitor run induction motor by pulse width modulated AC chopper.The phase angle control faces severe shortfall in the performance improvement for larger triggering angles. In this paper the comparison of phase angle control and sinusoidal pulse width modulation technique is encountered for effective speed control of single phase capacitor run induction motor. The necessary parameters are taken into considerations are higher efficiency, lesser total harmonic distortion and high input power factor. The results are compared by using

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8

Murali, N., and V. Balaji. "Real time FPGA Implementation of PWM Chopper Fed Capacitor Run Induction Motor." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (2018): 138. http://dx.doi.org/10.11591/ijres.v7.i3.pp138-148.

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<span>This paper presents the performance enhancement of capacitor run induction motor by pulse width modulated AC chopper.The phase angle control faces severe shortfall in the performance improvement for larger triggering angles. In this paper the comparison of phase angle control and sinusoidal pulse width modulation technique is encountered for effective speed control of single phase capacitor run induction motor. The necessary parameters are taken into considerations are higher efficiency, lesser total harmonic distortion and high input power factor. The results are compared by using

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9

Rahim, N. A., and Z. Islam. "Field Programmable Gate Array-Based Pulse-Width Modulation for Single Phase Active Power Filter." American Journal of Applied Sciences 6, no. 9 (2009): 1742–47. http://dx.doi.org/10.3844/ajassp.2009.1742.1747.

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10

Susheela, Nunsavath, and Satish Kumar. "Performance Analysis of FPGA based Diode Clamped Multilevel Inverter Fed Induction Motor Drive using Phase Opposition Disposition Multicarrier Based Modulation Strategy." International Journal of Power Electronics and Drive Systems (IJPEDS) 8, no. 4 (2017): 1512. http://dx.doi.org/10.11591/ijpeds.v8.i4.pp1512-1523.

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<p>Multilevel inverters (MLI) are becoming more popular over the years for medium and high power applications because of its significant merits over two level inverters. This paper presents an implementation of multicarrier based sinusoidal pulse width modulation technique for three phase seven level diode clamped multilevel inverter. This topology is operated under phase opposition disposition pulse width modulation technique. The performance of three phase seven level diode clamped inverter is analyzed for induction motor (IM) load. Simulation is performed using MATLAB/SIMULINK. Experi

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11

Kalaiarasu, Srinivasan, and Sudhakar Natarajan. "Conducted electromagnetic interference mitigation in super-lift Luo-converter for electric vehicle applications." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (2023): 3838. http://dx.doi.org/10.11591/ijece.v13i4.pp3838-3846.

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In this article, a digital chaotic pulse width modulation (DCPWM)-dependent electromagnetic interference (EMI) noise attenuating procedure has been implemented. With the aid of a field programmable gate array (FPGA), a randomized carrier frequency modulation with a fixed duty cycle has been generated through chaotic carrier frequency, and this process is called DCPWM. Conducted EMI suppression is achieved in a 200 kHz, 40 W elementary positive output super lift Luo (EPOSLL) converter using the DCPWM technique. The results are compared and validated with periodic PWM over DCPWM in simulation an

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Srinivasan, Kalaiarasu, and Natarajan Sudhakar. "Conducted electromagnetic interference mitigation in super-lift Luo-converter for electric vehicle applications." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (2023): 3838–46. https://doi.org/10.11591/ijece.v13i4.pp3838-3846.

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In this article, a digital chaotic pulse width modulation (DCPWM)-dependent electromagnetic interference (EMI) noise attenuating procedure has been implemented. With the aid of a field programmable gate array (FPGA), a randomized carrier frequency modulation with a fixed duty cycle has been generated through chaotic carrier frequency, and this process is called DCPWM. Conducted EMI suppression is achieved in a 200 kHz, 40 W elementary positive output super lift Luo (EPOSLL) converter using the DCPWM technique. The results are compared and validated with periodic PWM over DCPWM in simulation an

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13

Figueira, Vinícius, Tiago Costalonga, Victor Fernandes, Jorge de Almeida, Tadeu Nagashima Ferreira, and Vanessa Magri. "Frequency Analysis of Pulse-Width Modulation on All-Digital Transmitters." Journal of Communication and Information Systems 39, no. 2024 (2024): 164–72. http://dx.doi.org/10.14209/jcis.2024.17.

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This work investigates the frequency spectrum in the modulator and up-conversion outputs of a generic all-digital transmitter architecture. Considering the modulator is implemented as a pulse-width modulation (PWM), it is verified that this up-conversion process introduces a series of impulses resembling the spectrum of a unipolar return-to-zero (RZ) waveform in addition to the PWM impulses. Simulations show the minimum bit resolution of PWM signals where the impulses introduced are almost unnoticed, thus their influence is not distinguished from random background noise. An all-digital transmi

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14

Zhu, Yuxuan, Zhibang Song, Dandan Zhao, Junjun An, Congwei Liao, and Shengdong Zhang. "38.3: Compact Gate Driver on Array for Progressive‐mode PWM Micro‐LED Display using LTPS TFTs." SID Symposium Digest of Technical Papers 54, S1 (2023): 246–49. http://dx.doi.org/10.1002/sdtp.16274.

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A compact gate driver on array (GOA) was proposed for Micro‐Light Emitting diodes (Micro‐LED) display based on progressive‐mode pulse‐width modulation (PWM) using low‐temperature‐polysilicon (LTPS) thin‐film transistors (TFTs). Thanks to outputting line‐by‐line scanning (Scan) and emission control signals (EM) to address switching‐and emission‐transistors in Micro‐LED pixel circuit, the proposed GOA circuit enables an increased emission time by 60% with the frame rate of 120 Hz, compared with the conventional GOA circuit of simultaneous operating mode. Furthermore, the pulse‐width of EM signal

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15

Nam, Duong Le, Quang Linh Le, Tien Huy Cong Nguyen, Vu Phuong, and Lam Nguyen Tung. "Field-programmable gate array-based field-oriented control for permanent magnet synchronous motor drive." TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 21, no. 2 (2023): 448–58. https://doi.org/10.12928/telkomnika.v21i2.23560.

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Permanent magnet synchronous motor (PMSM) is a special type of synchronous electric motor that has many applications such as in the manufacturing industry of robots, self-propelled mechanisms, in the medical fiel. In this paper, the permanent magnet synchronous motor motor control structure according to the field-oriented control (FOC) algorithm will be implemented on the <em>field-programmable gate array</em> (FPGA) card. Function blocks in FOC algorithm for example PI controller, space vector pulse width modulation (SVPWM) algorithm will be integrated into individual itegrated circ

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16

Adharul, Muttaqin, Dion Finnadi Stefanus, Abidin Zainul, and Araki Kakeru. "FPGA based synchronous multi-channel PWM generator for humanoid robot." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 249–56. https://doi.org/10.11591/ijece.v11i1.pp249-256.

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In this paper, synchronous multi-channel pulse width modulation (PWM) generator for driving servo motors of humanoid robot was proposed. In an application, the humanoid robot requires smooth and beautiful movement, therefore the PWM signal for each servo motor must be synchronized. Since microcontroller (slave) has no enough channels to generate synchronous PWMs for 32 servo motors, field programmable gate array (FPGA) was used as slave for the humanoid robot. The FPGA was controlled by microcontroller (master) using serial communication. Simulation results show the system can perform serial c

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17

Jeevananthan, S., R. Nandhakumar, and P. Dananjayan. "Inverted sine carrier for fundamental fortification in PWM inverters and FPGA based implementations." Serbian Journal of Electrical Engineering 4, no. 2 (2007): 171–87. http://dx.doi.org/10.2298/sjee0702171j.

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This paper deals with a novel natural sampled pulse width modulation (PWM) switching strategy for voltage source inverter through carrier modification. The proposed inverted sine carrier PWM (ISCPWM) method, which uses the conventional sinusoidal reference signal and an inverted sine carrier, has a better spectral quality and a higher fundamental component compared to the conventional sinusoidal PWM (SPWM) without any pulse dropping. The ISCPWM strategy enhances the fundamental output voltage particularly at lower modulation index ranges while keeping the total harmonic distortion (THD) lower

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18

Quynh, Nguyen Vu, Ying Shieh Kung, Pham Van Dung, Kuan Yuen Liao, and Sheng Wei Chen. "FPGA-Realization of Vector Control for PMSM Drives." Applied Mechanics and Materials 311 (February 2013): 249–54. http://dx.doi.org/10.4028/www.scientific.net/amm.311.249.

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The design and implementation of a vector control for Permanent Magnetic Synchronous Motor (PMSM) based on Field Programmable Gate Array (FPGA) technology is presented in this paper. Firstly, a Space Vector Pulse Width Modulation (SVPWM) scheme, vector control method and PI controller are derived. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. Finally, an experimental system is setup to evaluate the effectiveness and correctness of the proposed vector controller for PMSM drives.

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19

Liu, Rilong, and Renxin Liu. "Design and Implementation of Pulse Width Modulation Driving System for Voice Coil Motor." Modern Applied Science 10, no. 10 (2016): 269. http://dx.doi.org/10.5539/mas.v10n10p269.

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According to the performance requirements of the control system for voice coil motor, a pulse width modulation driving system is designed and implemented based on an integrated power device and a field programmable gate array. LMD18200 is used as the motor driver to design the unit of switch type power driving. With APA300 as the digital controller, the modular design of the digital controller realizes with the Verilog hardware describing language, so it has a good flexibility and portability. The experimental results show that the current loop can rapidly keep track of current changes under t

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20

Zemmouri, A., R. Elgouri, M. Alareqi, M. Benbrahim, and L. Hlou. "Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core." International Journal of Power Electronics and Drive Systems (IJPEDS) 8, no. 1 (2017): 167. http://dx.doi.org/10.11591/ijpeds.v8.i1.pp167-175.

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This paper presents an embedded control application of clock frequency to control the pulse width of the output signals, implemented on field programmable get array. This control allows the creation of lines of Pulse-width modulation depending on the numbers of card outputs, without using the specific "Timers /Counters" blocks; this method is effective to adjust the amount of power supplied to an electrical charge. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. Performance of these design implemented in field programma

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Sutikno, Tole, Wong Jenn Hwa, Auzani Jidin, and Nik Rumzi Nik Idris. "A Simple Approach of Space-vector Pulse Width Modulation Realization Based on Field Programmable Gate Array." Electric Power Components and Systems 38, no. 14 (2010): 1546–57. http://dx.doi.org/10.1080/15325008.2010.482092.

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22

Mazin, Rejab Khalil, and A. Mohammed Laith. "Embedded processor system for controllable period-width multichannel pulse width modulation signals." TELKOMNIKA Telecommunication, Computing, Electronics and Control 19, no. 1 (2021): pp. 220~228. https://doi.org/10.12928/TELKOMNIKA.v19i1.16432.

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This paper proposes a sophisticated embedded processor system configured on zynq-xc7z020 field programmable gate array (FPGA) device for generating four channels pulse width modulation signals with variable duty cycles and periods using embedded design techniques. The main advantages of the technique are the high ability to perform a simultaneous control on period and pulse width of the generated signals and a high system design adaptation to choose the number of input/output channels. Controlling the the period and the pulse width is achieved by injecting a digital signal to the designed syst

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23

Żbik, Mateusz, and Piotr Wieczorek. "Charge-Line Dual-FET High-Repetition-Rate Pulsed Laser Driver." Applied Sciences 9, no. 7 (2019): 1289. http://dx.doi.org/10.3390/app9071289.

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Most modern pulsed laser systems require versatile laser diode drivers. A state-of-the-art pulsed laser driver should provide precise peak power regulation, high repetition rate, and pulse duration control. A new, charge line dual-FET transistor circuit structure was developed to provide all these features. The pulsed modulation current is adjustable up to Imax = 1.2 A, with the laser diode forward voltage acceptable up to UF max = 20 V. The maximum repetition rate is limited by a charge line circuit to frep max = 20 MHz. Compared to the conventional single transistor drivers, the solution pro

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24

Lin, Zhonglin, Tianhong Zhang, and Qi Xie. "Intelligent real-time pressure tracking system using a novel hybrid control scheme." Transactions of the Institute of Measurement and Control 40, no. 13 (2017): 3744–59. http://dx.doi.org/10.1177/0142331217730886.

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In this paper, a novel hybrid control scheme is proposed to improve the control performance in a real-time pressure tracking system using fast on-off solenoid valves. In this novel hybrid control scheme, an original approach named Time Interlaced Modulation (TIM) is developed to replace the traditional Pulse Width Modulation (PWM) approach. Besides using TIM, a new switching method which is referred as seven possible control modes is designed to ensure the proper switching states of the valves. Moreover, a controller with field programmable gate array (FPGA) is chosen to guarantee the real-tim

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25

Muttaqin, Adharul, Stefanus Dion Finnadi, Zainul Abidin, and Kakeru Araki. "FPGA based synchronous multi-channel PWM generator for humanoid robot." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 249. http://dx.doi.org/10.11591/ijece.v11i1.pp249-256.

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In this paper, synchronous multi-channel pulse width modulation (PWM) generator for driving servo motors of humanoid robot was proposed. In an application, the humanoid robot requires smooth and beautiful movement, therefore the PWM signal for each servo motor must be synchronized. Since microcontroller (slave) has no enough channels to generate synchronous PWMs for 32 servo motors, field programmable gate array (FPGA) was used as slave for the humanoid robot. The FPGA was controlled by microcontroller (master) using serial communication. Simulation results show the system can perform serial c

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26

Deng, Xiao, Dingrui Wang, Lipeng Pan, et al. "Static Ice Pressure Measuring System Based on Fiber Loop Ring-Down Spectroscopy and FPGA." Sensors 20, no. 20 (2020): 5927. http://dx.doi.org/10.3390/s20205927.

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Hydraulic engineering built in the cold region, such as reservoirs and hydropower stations, is often threatened by static ice pressure from nature. Therefore, it is of vital significance to research the pressure variation in the growth and melting processes of the ice layer for the design and protection of hydraulic structures in cold regions. This paper introduces an optical fiber sensor system based on the fiber loop ring-down spectroscopy technology and field-programmable gate array (FPGA) pulse modulation technology. An electro-optic modulation scheme that relied on FPGA to generate optica

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Ding, Changchun, Chengming Li, Ziming Wang, et al. "Free Space Optical Communication Networking Technology Based on a Laser Relay Station." Applied Sciences 13, no. 4 (2023): 2567. http://dx.doi.org/10.3390/app13042567.

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Optical communication modulation technology and networking technology are two important technologies for constructing free-space optical (FSO) communication. In this paper, pulse width modulation (PWM) is used to realize free-space optical communication. The process of signal modulation and demodulation is implemented by means of a field programmable gate array (FPGA). An optical communication relay system is constructed to realize communication networking. The binary data bits in the communication process are converted into pulse signals of different widths, the data demodulation process is r

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28

Renukadevi, Govindasamy, and Kalyanasundaram Rajambal. "Field programmable gate array implementation of space‐vector pulse‐width modulation technique for five‐phase voltage source inverter." IET Power Electronics 7, no. 2 (2014): 376–89. http://dx.doi.org/10.1049/iet-pel.2013.0078.

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29

Mohan, V., N. Stalin, and S. Jeevananthan. "A Tactical Chaos based PWM Technique for Distortion Restraint and Power Spectrum Shaping in Induction Motor Drives." International Journal of Power Electronics and Drive Systems (IJPEDS) 5, no. 3 (2015): 383. http://dx.doi.org/10.11591/ijpeds.v5.i3.pp383-392.

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The pulse width modulated voltage source inverters (PWM-VSI) dominate in the modern industrial environment. The conventional PWM methods are designed to have higher fundamental voltage, easy filtering and reduced total harmonic distortion (THD). There are number of clustered harmonics around the multiples of switching frequency in the output of conventional sinusoidal pulse width modulation (SPWM) and space vector pulse width modulation (SVPWM) inverters. This is due to their fixed switching frequency while the variable switching frequency makes the filtering very complex. Random carrier PWM (

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30

Yadav Madd, Santosh, and Dr Nitin Ramesh Bhasme. "An Experimental Investigation on VSI-fed Induction Motor using Xilinx ZYNQ-7000 SoC Controller." Iraqi Journal for Electrical and Electronic Engineering 20, no. 2 (2024): 104–14. http://dx.doi.org/10.37917/ijeee.20.2.9.

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In medium voltage and high-power drive applications, pulse width modulation (PWM) techniques are widely used to achieve effective speed control of AC motors. In real-time, an industrial drive system requires reduced hardware complexity and low computation time. The reliability of the AC drive can be improved with the FPGA (field programmable gate array) hardware equipped with digital controllers. To improve the performance of AC drives, a new FPGA-based Wavect real-time prototype controller (Xilinx ZYNQ-7000 SoC) is used to verify the effectiveness of the controller. These advanced controllers

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Nithya, Ramalingam, and Thiagarajan Anitha. "FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 157–64. https://doi.org/10.11591/ijres.v12.i2.pp157-164.

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The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switch

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Marguč, Jaka, Mitja Truntič, Miran Rodič, and Miro Milanovič. "FPGA Based Real-Time Emulation System for Power Electronics Converters." Energies 12, no. 6 (2019): 969. http://dx.doi.org/10.3390/en12060969.

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This paper deals with an emulation system for Power Electronics Converters (PEC). The emulation of PECs is performed on a Field-Programmable Gate Array (FPGA) capable of hard real-time operation. To obtain such a system, the converter operation is described using a differential equations-based model designed with the graph theory. Differential equation coefficients are changed according to the type of converter and pulse-width modulation (PWM) signals. The tie-set and incidence matrix approach for the converter modelling is performed to describe the converter operation in a general way. Such a

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Qin, Qing Liang. "Study on a New Type of HVDC Flexible Digital Pulse Width Modulated Carrier Frequency Selection." Applied Mechanics and Materials 740 (March 2015): 503–6. http://dx.doi.org/10.4028/www.scientific.net/amm.740.503.

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For multi_level multi_module in the flexible HVDC converter (MMC) module capacitor control algorithm is commonly based on nearest voltage level modulation (NLM), this algorithm requires the decimal part of the input sine wave for analog-to-digital conversion by digital signal (digital pulse modulation, referred to as DPWM),in the choice of hysteretic DPWM control signal is better, if the input triangle carrier wave frequency selection is not good, in each digital signal level will cause the output frequency of DPWM is not stable, some DPWM frequency is too high, and some DPWM has no output. In

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S. "FIELD PROGRAMMABLE GATE ARRAY BASED RF-THI PULSE WIDTH MODULATION CONTROL FOR THREE PHASE NVERTER USING MATLAB MODELSIM COSIMULATION." American Journal of Applied Sciences 9, no. 11 (2012): 1802–12. http://dx.doi.org/10.3844/ajassp.2012.1802.1812.

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Kaliannan, Thenmalar, Johny Renoald Albert, D. Muhamadha Begam, and P. Madhumathi. "Power Quality Improvement in Modular Multilevel Inverter Using for Different Multicarrier PWM." European Journal of Electrical Engineering and Computer Science 5, no. 2 (2021): 19–27. http://dx.doi.org/10.24018/ejece.2021.5.2.315.

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Pulse width modulation (PWM) is a powerful technique employed in analog circuit convert with a microprocessor based digital output. Besides, Pseudo Random Multi Carrier (PRMC) involves in two random PWM strategies to minimize the harmonic order for 9- level cascaded multilevel H-bridge (CHB) inverter and 9-level Modular Multilevel inverter are introduced. The design mainly focuses on the (Pulse Width Modulation) PWM method, in which two nearest voltage levels are approached in estimated output voltage prediction based on the Partial swarm optimization (PSO) algorithm, and it conveys a random v

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Saher, Albatran, A. Smadi Issam, and A. Alsyouf Mohammad. "Experimental Validation of Shared Inverter Topology to Drive Multi AC-Loads." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 2 (2018): 793–805. https://doi.org/10.11591/ijece.v8i2.pp793-805.

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Many reduced-switch-count (RSC) inverter topologies have been proposed in the literature. As the number of switches required to produce a set of voltages in RSC inverters are less than that in conventional inverter, as a result utilizing RSC inverters in a certain system reduces its size and cost. In this paper, a novel RSC shared inverter topology consisting of fifteen switches and capable of driving four three-phase AC-loads independently is proposed and experimentally verified. A carrier-based pulse width modulation (PWM) technique that employs the zero-sequence-signal injection principle i

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37

Ramalingam, Nithya, and Anitha Thiagarajan. "FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 157. http://dx.doi.org/10.11591/ijres.v12.i2.pp157-164.

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The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switch

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Krishna, Remya, Deepak E. Soman, Sasi K. Kottayil, and Mats Leijon. "Synchronous Current Compensator for a Self-Balanced Three-Level Neutral Point Clamped Inverter." Advances in Power Electronics 2014 (April 29, 2014): 1–8. http://dx.doi.org/10.1155/2014/620607.

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This paper presents a synchronous current control method for a three-level neutral point clamped inverter. Synchronous reference frame control based on two decoupled proportional-integral (PI) controllers is used to control the current in direct and quadrature axes. A phase disposition pulse width modulation (PDPWM) method in regular symmetrical sampling is used for generating the inverter switching signals. To eliminate the harmonic content with no phase errors, two first-order low pass filters (LPFs) are used for the dq currents. The simulation of closed-loop control is done in Matlab/Simuli

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Chander, Subhash, Pramod Agarwal, and Indra Gupta. "Design and Implementation of Field Programmable Gate Array based Digital Pulse Width Modulator for Synchronous Buck Converter." Journal of Low Power Electronics 8, no. 2 (2012): 158–69. http://dx.doi.org/10.1166/jolpe.2012.1181.

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Bharatiraja, C., J. L. Munda, N. Sriramsai, and T. Sai Navaneesh. "Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy." International Journal of Power Electronics and Drive Systems (IJPEDS) 7, no. 3 (2016): 892. http://dx.doi.org/10.11591/ijpeds.v7.i3.pp892-900.

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The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduc

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CHEN, Hao, Sanjun LIU, and Guohong LAI. "High-Precision Dead-Time Intellectual Property Core and Its Compensation for Inverters." Wuhan University Journal of Natural Sciences 28, no. 3 (2023): 271–76. http://dx.doi.org/10.1051/wujns/2023283271.

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In the inverter circuit, there exists a specific on-off time in each power transistor. As such, to prevent a short circuit of the two switch devices on the upper and lower bridge arms, a specific dead time must be set in the pulse width modulation (PWM) and the sinusoidal pulse width modulation (SPWM) signals. In this paper, an intellectual property (IP) core that can introduce a high-precision dead time of arbitrary length into PWM or SPWM signals of the inverter is designed to increase the precision, convenience and generalization of dead time control, resulting in a boosted control accuracy

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Abdelkarim, Zemmouri, Barodi Anass, Dahou Hamad, et al. "A microsystem design for controlling a DC motor by pulse width modulation using MicroBlaze soft-core." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1437–48. https://doi.org/10.11591/ijece.v13i2.pp1437-1448.

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This paper proposes a microsystem based on the field programmable gate arrays (FPGA) electronic board. The preliminary objective is to manipulate a programming language to achieve a control part capable of controlling the speed of electric actuators, such as direct current (DC) motors. The method proposed in this work is to control the speed of the DC motor by a purely embedded architecture within the FPGA in order to reduce the space occupied by the circuit to a minimum and to ensure the reliability of the system. The implementation of this system allows the embedded MicroBlaze processor to b

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Wu, Yixiao, and Zhong Wu. "A Generalized Center-Aligned High-Resolution Pulse Width Modulator Implementation Using an Output Serializer in Field Programmable Gate Arrays." Actuators 14, no. 4 (2025): 181. https://doi.org/10.3390/act14040181.

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A digital pulse width modulator (DPWM) is a key component in digital power electronics. Techniques like space vector modulation, along with rising switching frequencies from wide-bandgap power transistors, create a need for a center-aligned high-resolution PWM (CA-HRPWM). However, existing FPGA-based HRPWM designs primarily focus on achieving fine timing resolution and are not fully optimized for multichannel CA-HRPWM implementations. This paper presents a generalized CA-HRPWM design based on the output serializer (OSERDES) module. The design includes comparison values and dead time calculatio

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Qin, Qing Liang, Xiao Hui Yao, and Dian Zhang. "Hysteretic Control Technology in New Flexible HVDC." Applied Mechanics and Materials 740 (March 2015): 495–98. http://dx.doi.org/10.4028/www.scientific.net/amm.740.495.

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The nearest level modulation (NLM) is commonly used in the multi-level multi-module converter (MMC), which need to convert the fractional part of the input sine wave to the digital signal (DPWM). However, the narrow pulse width of digital signal , the frequent change of the digital signal and the frequent instability of output are caused by the sensitive fractional portion of the input, which push Multilevel converter into the position where it has to operate in high frequency and be unstable. In order to solve the problem mentioned above, this paper provides a way called hysteresis comparison

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Ji, Bao Jian, Feng Hong, Wen Jing Ge, and Wei Yang. "Research on Dual Buck Half Bridge Five-Level Inverter for Rooftop Solar System." Applied Mechanics and Materials 99-100 (September 2011): 628–32. http://dx.doi.org/10.4028/www.scientific.net/amm.99-100.628.

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This paper presents a novel design for dual buck half bridge five-level inverter (DBHBFLI), which based on field-programmable gate array (FPGA), and was used for photovoltaic power system. This topology is derived from dual buck half bridge inverter (DBHBI), which has the characteristics of no shoot-through problem, no body diode reverse-recovery problem, and current half-period work mode, these merits are retained in the proposed inverter. FPGA logic device is chosen for the hardware implementation of control circuit. The FPGA controller consists of six main modules: the sine wave generator m

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Ali, Rehab, Hossameldin Eassa, Hesham H. Aly, Mohamed Abaza, and Saleh M. Eisa. "Low Power FPGA Implementation of a Smart Building Free Space Optical Communication System." Photonics 9, no. 6 (2022): 432. http://dx.doi.org/10.3390/photonics9060432.

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Free Space Optical (FSO) communication systems have extensively invaded the speed of smart city evolution due to the current surge in demand for wireless communication spots that can match recent challenges due to high technical leaps in smart city evolution. As the number of users is vastly increasing throughout all networks in the form of machines, devices, and variously distinct objects, FSO is a hugely recommended robust communication system that mitigates a lot of RF disadvantages on the field with no need for licensing, fast rollout time, and low cost. This paper shows an exploit of a Lo

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Hassaine, Linda, and Mohamed Rida Bengourina. "Design and digital implementation of power control strategy for grid connected photovoltaic inverter." International Journal of Power Electronics and Drive Systems (IJPEDS) 10, no. 3 (2019): 1564. http://dx.doi.org/10.11591/ijpeds.v10.i3.pp1564-1574.

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<p class="Abstract">This paper presents the optimization design and a detailed implementation in FPGA (Field-Programmable Gate Array) of a power control strategy. This strategy is based on the phase shift angle of the inverter output voltage with respect to the grid voltage and DSPWM (Digital Sinusoidal Pulse Width Modulation) patterns “Phase shift angle-DSPWM” for an inverter for photovoltaic system connected to the grid. The proposed control can synchronize a sinusoidal inverter output current with a grid voltage and control the power injected into the grid. Detailed development of a d

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Linda, Hassaine, and Rida Bengourina Mohamed. "Design and digital implementation of power control strategy for grid connected photovoltaic inverter." International Journal of Power Electronics and Drive System (IJPEDS) 10, no. 3 (2019): 1564–74. https://doi.org/10.11591/ijpeds.v10.i3.pp1564-1574.

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This paper presents the optimization design and a detailed implementation in FPGA (Field-Programmable Gate Array) of a power control strategy. This strategy is based on the phase shift angle of the inverter output voltage with respect to the grid voltage and DSPWM (Digital Sinusoidal Pulse Width Modulation) patterns “Phase shift angle-DSPWM” for an inverter for photovoltaic system connected to the grid. The proposed control can synchronize a sinusoidal inverter output current with a grid voltage and control the power injected into the grid. Detailed development of a digital control

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Saccenti, Leonardo, Valentina Bianchi, and Ilaria De Munari. "Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices." Applied System Innovation 4, no. 1 (2021): 5. http://dx.doi.org/10.3390/asi4010005.

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In a multiple parallel-connected inverters system, limiting the circulating current phenomenon is mandatory since it may influence efficiency and reliability. In this paper, a new control method aimed at this purpose and conceived to be implemented on a Field Programmable Gate Array (FPGA) device is presented. Each of the inverters, connected in parallel, is conceived to be equipped with an FPGA that controls the Pulse-Width Modulation (PWM) waveform without intercommunication with the others. The hardware implemented is the same for every inverter; therefore, the addition of a new module does

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Aib, A., D. E. Khodja, and S. Chakroune. "Field programmable gate array hardware in the loop validation of fuzzy direct torque control for induction machine drive." Electrical Engineering & Electromechanics, no. 3 (April 23, 2023): 28–35. http://dx.doi.org/10.20998/2074-272x.2023.3.04.

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Introduction. Currently, the direct torque control is very popular in industry and is of great interest to scientists in the variable speed drive of asynchronous machines. This technique provides decoupling between torque control and flux without the need to use pulse width modulation or coordinate transformation. Nevertheless, this command presents two major importunities: the switching frequency is highly variable on the one hand, and on the other hand, the amplitude of the torque and stator flux ripples remain poorly controlled throughout the considered operating speed range. The novelty of

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