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Relevant bibliographies by topics / Field programmable gate arrays Automatic testing

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Academic literature on the topic 'Field programmable gate arrays Automatic testing'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

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Journal articles on the topic "Field programmable gate arrays Automatic testing"

1

Liu, Qian, and Dan Wu. "FPGA Auto Configuration Based on ATE." Applied Mechanics and Materials 121-126 (October 2011): 3310–14. http://dx.doi.org/10.4028/www.scientific.net/amm.121-126.3310.

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FPGAs (Field Programmable Gate Arrays) are highly integrated devices which can be programmed as variable functions. The application-level testing of FPGAs usually include multiple reconfigurations and relevant functional tests respectively through ATEs (Automated Test Equipments). However, test engineers are facing a tough problem to reconfigure FPGAs automatically through an ATE instead of using specific tools and download cables provided by FPGAs manufacturers. This paper takes example for XILINX Virtex-E series, presents two different methods for FPGA auto configuration based on an ATE using JTAG configuration interface and boundary-scan protocol, and accomplishes the entire auto configuration-test procedure by a single ATE.

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Rivera-Acosta, Miguel, Susana Ortega-Cisneros, and Jorge Rivera. "Automatic Tool for Fast Generation of Custom Convolutional Neural Networks Accelerators for FPGA." Electronics 8, no. 6 (June 6, 2019): 641. http://dx.doi.org/10.3390/electronics8060641.

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This paper presents a platform that automatically generates custom hardware accelerators for convolutional neural networks (CNNs) implemented in field-programmable gate array (FPGA) devices. It includes a user interface for configuring and managing these accelerators. The herein-presented platform can perform all the processes necessary to design and test CNN accelerators from the CNN architecture description at both layer and internal parameter levels, training the desired architecture with any dataset and generating the configuration files required by the platform. With these files, it can synthesize the register-transfer level (RTL) and program the customized CNN accelerator into the FPGA device for testing, making it possible to generate custom CNN accelerators quickly and easily. All processes save the CNN architecture description are fully automatized and carried out by the platform, which manages third-party software to train the CNN and synthesize and program the generated RTL. The platform has been tested with the implementation of some of the CNN architectures found in the state-of-the-art for freely available datasets such as MNIST, CIFAR-10, and STL-10.

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Mylonas, Eleftherios, Nikolaos Tzanis, Michael Birbas, and Alexios Birbas. "An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications." Electronics 9, no. 2 (February 9, 2020): 299. http://dx.doi.org/10.3390/electronics9020299.

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Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.

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Liu, Xianping, Xiaodong Ju, Wenxiao Qiao, Junqiang Lu, Baiyong Men, Kai Zhang, and Yongchao Yao. "Research on Test-bench for Sonic Logging Tool." Earth Sciences Research Journal 20, no. 1 (April 30, 2016): 1–4. http://dx.doi.org/10.15446/esrj.v20n1.54141.

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<p>In this paper, the test-bench for sonic logging tool is proposed and designed to realize automatic calibration and testing of the sonic logging tool. The test-bench System consists of Host Computer, Embedded Controlling Board, and functional boards. The Host Computer serves as the Human Machine Interface (HMI) and processes uploaded data. The software running on Host Computer is designed on VC++, which is developed based on multithreading, Dynamic Linkable Library (DLL) and Multiple Document Interface (MDI) techniques. The Embedded Controlling Board uses ARM7 as the microcontroller and communicates with Host Computer via Ethernet. The Embedded Controlling Board software is realized based on embedded uclinux operating system with a layered architecture. The functional boards are designed based on Field Programmable Gate Array (FPGA) and provide test interfaces for the logging tool. The functional board software is divided into independent sub-modules that can repeatedly be used by various functional boards and then integrated those sub-modules in the top layer. With the layered architecture and modularized design, the software system is highly reliable and extensible. With the help of designed system, a test has been conducted quickly and successfully on the electronic receiving cabin of the sonic logging tool. It demonstrated that the system could greatly improve the production efficiency of the sonic logging tool.</p>

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Mohanakrishnan, S., and J. B. Evans. "Automatic implementation of FIR filters on field programmable gate arrays." IEEE Signal Processing Letters 2, no. 3 (March 1995): 51–53. http://dx.doi.org/10.1109/97.372915.

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Saleh, Shukur Bin, Sulaiman Bin Mazlan, Nik Iskandar Bin Hamzah, Ahmad Zahid Zakwan Bin Abdul Karim, Mohd Shamian Bin Zainal, Shipun Anuar Bin Hamzah, Danial Bin Md Nor, and Hazwaj Bin Mhd Poad. "Smart Home Security Access System Using Field Programmable Gate Arrays." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (July 1, 2018): 152. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp152-160.

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Nowadays, the rapid growth of burglary and theft cases over the world has been threatening to the vulnerability of traditional home security systems. Therefore the development home security with intelligent control wherein focus to enhance conventional technique to theadvanced digital security systemand to be more interestinginhome or building owner for preventing intruders in smart home implementation. However, using avariety of type conventional lock doors for security purposes and analog intruder sensor with individual function system is not secure enoughin order to protect the person or company properties. That why the emergence of new technology such as integrated circuit network will apply in Smart Home system for abetter security solution to prevent the houses from theintruder and hazardous fire incident. Therefore, this project is done to design and build a smart system with consist of digital security entry for automatic lock doors and also for activating or deactivate all security sensor in houses which is function for detecting the irregular movement and hot temperature (fire incident) in-house for the domestic residential sector. This product includeswith doors automatic lock system using servo motor and detect irregular movement intruder using PIR motion sensor (HC-SR501) and also measure hot temperature using temperature sensor (LM35). The sensor will transmit theanalog signal to Field Programmable Gate Array (FPGA) the Altera DE2-115 board to be processed and which will then display the status entry after key-in password and activation security system on the LED seven segment displays. The entry login controller will use apush button or switchesavailable on FPGA board that are used to login password for automatic door accessand also able maintained for control home smart security system.

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Kalyan Kumar, L., Aditya S. Ramani, Amol J. Mupid, and V. Kamakoti. "Pseudo-online testing methodologies for various components of field programmable gate arrays." Microprocessors and Microsystems 29, no. 2-3 (April 2005): 99–119. http://dx.doi.org/10.1016/j.micpro.2004.06.006.

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Smith, J. R., and Tian Xia. "High-Resolution Delay Testing of Interconnect Paths in Field-Programmable Gate Arrays." IEEE Transactions on Instrumentation and Measurement 58, no. 1 (January 2009): 187–95. http://dx.doi.org/10.1109/tim.2008.927212.

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Dixit, Arati M., and Harpreet Singh. "A Soft Computing Approach to Crack Detection and Impact Source Identification with Field-Programmable Gate Array Implementation." Advances in Fuzzy Systems 2013 (2013): 1–12. http://dx.doi.org/10.1155/2013/343174.

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The real-time nondestructive testing (NDT) for crack detection and impact source identification (CDISI) has attracted the researchers from diverse areas. This is apparent from the current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposed method can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB’s fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL). The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA) implementation is done using Xilinx’s Spartan 3 FPGA. SynaptiCAD’s Verilog Simulators—VeriLogger PRO and ModelSim—are used as the software simulation and debug environment.

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Zhai, Xiaojun, Faycal Bensaali, and Reza Sotudeh. "Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems." Journal of Electronic Imaging 22, no. 1 (January 15, 2013): 013009. http://dx.doi.org/10.1117/1.jei.22.1.013009.

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Dissertations / Theses on the topic "Field programmable gate arrays Automatic testing"

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Dixon, Bobby Earl Stroud Charles E. "Built-in self-test of the programmable interconnect in field programmable gate arrays." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/FALL/Electrical_and_Computer_Engineering/Thesis/Dixon_Bobby_16.pdf.

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Lerner, Lee W. Stroud Charles E. "Built-In Self-Test for input/output tiles in field programmable gate arrays." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/SPRING/Electrical_and_Computer_Engineering/Thesis/Lerner_Lee_53.pdf.

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Davis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.

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Harris, Jonathan McKinley Stroud Charles E. "Built-in self-test configurations for field programmable gate array cores in systems-on-chip." Auburn, Ala., 2004. http://repo.lib.auburn.edu/EtdRoot/2004/FALL/Electrical_and_Computer_Engineering/Thesis/harri34_43_msthesisjharrisF04.pdf.

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Sarabi, Andisheh. "Logic Synthesis with High Testability for Cellular Arrays." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4752.

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The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.

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Majid, Ashraf Muhammad. "Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39562.

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Methods for Extending High-Performance Automated Test Equipment (ATE) using Multi-Gigahertz FPGA Technologies Ashraf M. Majid 264 Pages Directed by Dr. David Keezer This thesis presents methods for developing multi-function, multi-GHz, FPGAbased test modules designed to enhance the performance capabilities of automated test equipment (ATE). The methods are used to develop a design approach that utilizes a test module structure in two blocks. A core logic block is designed using a multi-GHz FPGA that provides control functions. Another block called the â application specificâ logic block includes components required for specific test functions. Six test functions are demonstrated in this research: high-speed signal multiplexing, loopback testing, jitter injection, amplitude adjustment, and timing adjustment. Furthermore, the test module is designed to be compatible with existing ATE infrastructure, thus retaining full ATE capabilities for standard tests. Experimental results produced by this research provide evidence that the methods are sufficiently capable of enhancing the multi-GHz testing capabilities of ATE and are extendable into future ATE development. The modular approach employed by the methods in this thesis allow for flexibility and future upgradability to even higher frequencies. Therefore the contributions made in this thesis have the potential to be used into the foreseeable future for enhancements to semiconductor test capabilities.

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Potgieter, Juan-Pierre. "Single event upset testing of flash based field programmable gate arrays." Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12520.

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In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities; all this has made circuits more sensitive to various kinds of failures. These trends allowed soft errors, which up until recently was just a concern for space application, to become a major source of system failures of electronic products. The aim of this research paper was to investigate different mitigation techniques that prevent these soft errors in a Video Graphics Array (VGA) controller which is commonly used in projecting images captured by cameras. This controller was implemented on a Flash Based Field Programmable Gate array (FPGA). A test set-up was designed and implemented at NRF iThemba LABS, which was used to conduct the experiments necessary to evaluate the effectiveness of different mitigation techniques. The set-up was capable of handling multiple Device Under Tests (DUT) and had the ability to change the angle of incidence of each DUT. The DUTs were radiated with a 66MeV proton beam while the monitoring equipment observed any errors that had occurred. The results obtained indicated that all the implemented mitigation techniques tested on the VGA system improved the system’s capability of mitigating Single Event Upsets (SEU). The most effective mitigation technique was the OR-AND Multiplexer Single Event Transient (SET) filter technique. It was thus shown that mitigation techniques are viable options to prevent SEU in a VGA controller. The permanent SEU testing set-up which was designed and manufactured and was used to conduct the experiments, proved to be a practical option for further microelectronics testing at iThemba LABS.

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Vemula, Sudheer Stroud Charles E. "Built-in self-test for input/output cells in field programmable gate arrays." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/VEMULA_SUDHEER_17.pdf.

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Van, Aardt Stefan. "Total ionizing dose and single event upset testing of flash based field programmable gate arrays." Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12548.

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The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private individuals and researchers to launch satellites, has led to an increased interest in commercial off the shelf components. The metal oxide semiconductor (MOS) structures of FPGAs however, are sensitive to radiation effects which can lead to decreased reliability of the device. In order to successfully implement a FPGA based system in a radiation environment, such as on-board a satellite, the single event upset (SEU) and total ionizing dose (TID) characteristics of the device must first be established. This research experimentally determines a research procedure which could accurately determine the SEU cross sections and TID characteristics of various mitigation techniques as well as control circuits implemented in a ProASIC3 A3P1000 FPGA. To gain an understanding of the SEU effects of the implemented circuits, the test FPGA was irradiated by a 66MeV proton beam at the iTemba LABS facility. Through means of irradiation, the SEU cross section of various communication, motor control and mitigation schemes circuits, induced by high energy proton strikes was investigated. The implementation of a full global triple modular redundancy (TMR) and a combination of TMR and a AND-OR multiplexer filter was found to most effectively mitigate SEUs in comparison to the other techniques. When comparing the communication and motor control circuits, the high frequency I2C and SPI circuits experienced a higher number of upsets when compared to a low frequency servo motor control circuit. To gain a better understanding of the absorbed dose effects, experimental TID testing was conducted by irradiating the test FPGA with a cobalt-60 (Co-60) source. An accumulated absorbed dose resulted in the fluctuation of the device supply current and operating voltages as well as resulted in output errors. The TMR and TMR filtering combination mitigation techniques again were found to be the most effective methods of mitigation.

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Van, Heerden Hein. "The design and testing of a superconducting programmable gate array." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1644.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.
This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design was assembled incorporating a routing architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final chip is presented and discussed followed by a discussion on testing. This thesis demonstrates the successful implementation of a fully functional reprogrammable logic device using RSFQ circuitry.

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Books on the topic "Field programmable gate arrays Automatic testing"

1

Daziron, Jean-Marie. Automatic synthesis of a LF-radio data receiver interface using ASYL and ACTEL field programmable gate arrays. Manchester: UMIST, 1994.

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Thompson, Adrian. Hardware evolution: Automatic design of electronic circuits in reconfigurable hardware by Artificial Evolution. London: Springer, 1998.

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Thompson, Adrian. Hardware Evolution: Automatic Design of Electronic Circuits in Reconfigurable Hardware by Artificial Evolution (Distinguished Dissertations). Springer, 1999.

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Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing). Springer, 2006.

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Conference papers on the topic "Field programmable gate arrays Automatic testing"

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Srivani, L., B. Krishna Kumar, S. A. V. Satya Murty, and P. Swaminathan. "Accelerated life testing of Field Programmable Gate Arrays." In 2010 2nd International Conference on Reliability, Safety and Hazard - Risk-Based Technologies and Physics-of-Failure Methods (ICRESH). IEEE, 2010. http://dx.doi.org/10.1109/icresh.2010.5779570.

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Liu, Tong, Wei Kang Huang, and Fabrizio Lombardi. "Testing of uncustomized segmented channel field programmable gate arrays." In the 1995 ACM third international symposium. New York, New York, USA: ACM Press, 1995. http://dx.doi.org/10.1145/201310.201330.

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Tong Liu, Wei Kang Huang, and F. Lombardi. "Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242145.

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Liao, Yongbo, Ruan Aiwu, Wang Yu, Xiang Chuanyin, Wang Lin, Huang Haocheng, and Zhu Jianhua. "Interconnect resources testing and faults diagnosis in field programmable gate arrays." In Instruments (ICEMI). IEEE, 2011. http://dx.doi.org/10.1109/icemi.2011.6037975.

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Tseng, Mao-Sheng, Hui-Wen Huang, Ming-Huei Chen, Tsung-Chieh Cheng, Hsiang-Han Chung, Tzeng-Hsi Liu, Wen-Lung Yang, Ming-Chung Lee, and Mao-Yuan Chen. "The Application of FPGA for Anticipated Transients Without Scram Mitigation System." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29029.

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The digitalized Instrumentation and Control (I&C) system of nuclear power plants (NPP) could provide operator easily Human-Machine Interface (HMI) and more powerful overall operation capability. However, some software errors may cause a kind of Common Cause Failure (CCF). As a consequence, the event of Anticipated Transients Without Scram (ATWS) will occur. In order to assure that the plant can be shutdown safely and to follow the requirements of 10CFR50.62, the utility builds up various ATWS mitigation features in NPP. The features include Fine Motion Control Rod Drive Run In, Alternate Rod Insertion, Standby Liquid Control System, Reactor Internal Pump Trip or Runback, Feedwater Flow Runback and Inhibition of Automatic Depressurization System. This research developed an evaluation method of diverse back-up means for computerized I&C system. A diverse backup of digital I&C system is the most important means to defend against CCF and un-detectable software faults. Institute of Nuclear Energy Research (INER) is developing a computerized I&C test facility, which is incorporated a commercial grade I&C systems with Personal Computer Transient Analyzer (PCTran)/Advanced Boiling Water Reactor (ABWR), a NPP simulation computer code. By taking the technology of Field Programmable Gate Array (FPGA) to implement the methods of ATWS mitigation, the research built up a diverse back-up of digital I&C system to expect to defend against CCF and undetectable software faults. According to the testing and evaluation, the work can be achieved the analysis of Diversity and Defense-in-Depth (D3).

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Yasko, Alexander, Eugene Babeshko, and Vyacheslav Kharchenko. "Verification of FPGA Based NPP I&C Systems Considering Multiple Faults: Technique and Automation Tool." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-67065.

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Instrumentation and Control (I&C) systems for Nuclear Power Plants (NPP) are exceedingly complicated electronic solutions that include thousands of different components such as microcontrollers, Field-Programmable Gate Arrays (FPGAs), integrated circuits etc. Deployment of such safety-critical systems cannot be performed without complex safety and reliability assessment, verification and validation (V&V) activities that are addressed to exposing of overlooked faults. The examples of such activities are Fault Tree Analysis (FTA), Failure Modes and Effects Analysis (FMEA), Fault Injection Testing (FIT). Due to complexity of NPP I&C systems in most cases the process of assessment is very time consuming and the results mostly depend on experts’ qualification. Traditional safety and reliability assessment methods are being constantly modified and enhanced so as to comply with increasing demands of national and international standards and guidance, as well as to be applied for I&C systems that contain number of complex components like FPGA. Although much work related to analysis of FPGA-based systems has been performed, there is a lack of detailed technique for FPGA-based I&C systems failure identification that considers probability of several faults at the same time (multi-faults), development of preventive strategies for controlling or reducing of the risk related to such failures, as well as automation of this technique so as to make it utilizable for real NPP industry tasks. FIT as verification for Failure Modes, Effects and Diagnostics Analysis (FMEDA) was used during Safety Integrity Level 3 (SIL3) certification process of RadICS NPP I&C platform, while the parts of proposed technique were used as internal verification and validation activities applied on several modules of the platform.

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Yang, Hsin-Jung, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, and Joel Emer. "Automatic Construction of Program-Optimized FPGA Memory Networks." In FPGA '17: The 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3020078.3021748.

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Burlyaev, Dmitry, Pascal Fradet, and Alain Girault. "Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits." In FPGA '15: The 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2015. http://dx.doi.org/10.1145/2684746.2689058.

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Yu, Yunxuan, and Lei He. "FPGA Power Estimation Using Automatic Feature Selection (Abstract Only)." In FPGA'16: The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2847263.2847327.

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Zhao, Ruizhe, Xinyu Niu, and Wayne Luk. "Automatic Optimising CNN with Depthwise Separable Convolution on FPGA." In FPGA '18: The 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3174243.3174959.

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