Journal articles: 'Field programmable gate arrays Automatic testing'

1

Liu, Qian, and Dan Wu. "FPGA Auto Configuration Based on ATE." Applied Mechanics and Materials 121-126 (October 2011): 3310–14. http://dx.doi.org/10.4028/www.scientific.net/amm.121-126.3310.

Full text

Abstract:

FPGAs (Field Programmable Gate Arrays) are highly integrated devices which can be programmed as variable functions. The application-level testing of FPGAs usually include multiple reconfigurations and relevant functional tests respectively through ATEs (Automated Test Equipments). However, test engineers are facing a tough problem to reconfigure FPGAs automatically through an ATE instead of using specific tools and download cables provided by FPGAs manufacturers. This paper takes example for XILINX Virtex-E series, presents two different methods for FPGA auto configuration based on an ATE using JTAG configuration interface and boundary-scan protocol, and accomplishes the entire auto configuration-test procedure by a single ATE.

APA, Harvard, Vancouver, ISO, and other styles

2

Rivera-Acosta, Miguel, Susana Ortega-Cisneros, and Jorge Rivera. "Automatic Tool for Fast Generation of Custom Convolutional Neural Networks Accelerators for FPGA." Electronics 8, no. 6 (June 6, 2019): 641. http://dx.doi.org/10.3390/electronics8060641.

Full text

Abstract:

This paper presents a platform that automatically generates custom hardware accelerators for convolutional neural networks (CNNs) implemented in field-programmable gate array (FPGA) devices. It includes a user interface for configuring and managing these accelerators. The herein-presented platform can perform all the processes necessary to design and test CNN accelerators from the CNN architecture description at both layer and internal parameter levels, training the desired architecture with any dataset and generating the configuration files required by the platform. With these files, it can synthesize the register-transfer level (RTL) and program the customized CNN accelerator into the FPGA device for testing, making it possible to generate custom CNN accelerators quickly and easily. All processes save the CNN architecture description are fully automatized and carried out by the platform, which manages third-party software to train the CNN and synthesize and program the generated RTL. The platform has been tested with the implementation of some of the CNN architectures found in the state-of-the-art for freely available datasets such as MNIST, CIFAR-10, and STL-10.

APA, Harvard, Vancouver, ISO, and other styles

3

Mylonas, Eleftherios, Nikolaos Tzanis, Michael Birbas, and Alexios Birbas. "An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications." Electronics 9, no. 2 (February 9, 2020): 299. http://dx.doi.org/10.3390/electronics9020299.

Full text

Abstract:

Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.

APA, Harvard, Vancouver, ISO, and other styles

4

Liu, Xianping, Xiaodong Ju, Wenxiao Qiao, Junqiang Lu, Baiyong Men, Kai Zhang, and Yongchao Yao. "Research on Test-bench for Sonic Logging Tool." Earth Sciences Research Journal 20, no. 1 (April 30, 2016): 1–4. http://dx.doi.org/10.15446/esrj.v20n1.54141.

Full text

Abstract:

<p>In this paper, the test-bench for sonic logging tool is proposed and designed to realize automatic calibration and testing of the sonic logging tool. The test-bench System consists of Host Computer, Embedded Controlling Board, and functional boards. The Host Computer serves as the Human Machine Interface (HMI) and processes uploaded data. The software running on Host Computer is designed on VC++, which is developed based on multithreading, Dynamic Linkable Library (DLL) and Multiple Document Interface (MDI) techniques. The Embedded Controlling Board uses ARM7 as the microcontroller and communicates with Host Computer via Ethernet. The Embedded Controlling Board software is realized based on embedded uclinux operating system with a layered architecture. The functional boards are designed based on Field Programmable Gate Array (FPGA) and provide test interfaces for the logging tool. The functional board software is divided into independent sub-modules that can repeatedly be used by various functional boards and then integrated those sub-modules in the top layer. With the layered architecture and modularized design, the software system is highly reliable and extensible. With the help of designed system, a test has been conducted quickly and successfully on the electronic receiving cabin of the sonic logging tool. It demonstrated that the system could greatly improve the production efficiency of the sonic logging tool.</p>

APA, Harvard, Vancouver, ISO, and other styles

5

Mohanakrishnan, S., and J. B. Evans. "Automatic implementation of FIR filters on field programmable gate arrays." IEEE Signal Processing Letters 2, no. 3 (March 1995): 51–53. http://dx.doi.org/10.1109/97.372915.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Saleh, Shukur Bin, Sulaiman Bin Mazlan, Nik Iskandar Bin Hamzah, Ahmad Zahid Zakwan Bin Abdul Karim, Mohd Shamian Bin Zainal, Shipun Anuar Bin Hamzah, Danial Bin Md Nor, and Hazwaj Bin Mhd Poad. "Smart Home Security Access System Using Field Programmable Gate Arrays." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (July 1, 2018): 152. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp152-160.

Full text

Abstract:

Nowadays, the rapid growth of burglary and theft cases over the world has been threatening to the vulnerability of traditional home security systems. Therefore the development home security with intelligent control wherein focus to enhance conventional technique to theadvanced digital security systemand to be more interestinginhome or building owner for preventing intruders in smart home implementation. However, using avariety of type conventional lock doors for security purposes and analog intruder sensor with individual function system is not secure enoughin order to protect the person or company properties. That why the emergence of new technology such as integrated circuit network will apply in Smart Home system for abetter security solution to prevent the houses from theintruder and hazardous fire incident. Therefore, this project is done to design and build a smart system with consist of digital security entry for automatic lock doors and also for activating or deactivate all security sensor in houses which is function for detecting the irregular movement and hot temperature (fire incident) in-house for the domestic residential sector. This product includeswith doors automatic lock system using servo motor and detect irregular movement intruder using PIR motion sensor (HC-SR501) and also measure hot temperature using temperature sensor (LM35). The sensor will transmit theanalog signal to Field Programmable Gate Array (FPGA) the Altera DE2-115 board to be processed and which will then display the status entry after key-in password and activation security system on the LED seven segment displays. The entry login controller will use apush button or switchesavailable on FPGA board that are used to login password for automatic door accessand also able maintained for control home smart security system.

APA, Harvard, Vancouver, ISO, and other styles

7

Kalyan Kumar, L., Aditya S. Ramani, Amol J. Mupid, and V. Kamakoti. "Pseudo-online testing methodologies for various components of field programmable gate arrays." Microprocessors and Microsystems 29, no. 2-3 (April 2005): 99–119. http://dx.doi.org/10.1016/j.micpro.2004.06.006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Smith, J. R., and Tian Xia. "High-Resolution Delay Testing of Interconnect Paths in Field-Programmable Gate Arrays." IEEE Transactions on Instrumentation and Measurement 58, no. 1 (January 2009): 187–95. http://dx.doi.org/10.1109/tim.2008.927212.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Dixit, Arati M., and Harpreet Singh. "A Soft Computing Approach to Crack Detection and Impact Source Identification with Field-Programmable Gate Array Implementation." Advances in Fuzzy Systems 2013 (2013): 1–12. http://dx.doi.org/10.1155/2013/343174.

Full text

Abstract:

The real-time nondestructive testing (NDT) for crack detection and impact source identification (CDISI) has attracted the researchers from diverse areas. This is apparent from the current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposed method can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB’s fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL). The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA) implementation is done using Xilinx’s Spartan 3 FPGA. SynaptiCAD’s Verilog Simulators—VeriLogger PRO and ModelSim—are used as the software simulation and debug environment.

APA, Harvard, Vancouver, ISO, and other styles

10

Zhai, Xiaojun, Faycal Bensaali, and Reza Sotudeh. "Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems." Journal of Electronic Imaging 22, no. 1 (January 15, 2013): 013009. http://dx.doi.org/10.1117/1.jei.22.1.013009.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Lan Zhao, D. M. H. Walker, and F. Lombardi. "I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays." IEEE Transactions on Computers 47, no. 10 (1998): 1136–52. http://dx.doi.org/10.1109/12.729796.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Hasnat, Abul, Anindya Ghosh, Amina Khatun, and Santanu Halder. "Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System." Fibres and Textiles in Eastern Europe 25 (February 28, 2017): 42–48. http://dx.doi.org/10.5604/01.3001.0010.1709.

Full text

Abstract:

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

APA, Harvard, Vancouver, ISO, and other styles

13

Levin, I. I., V. A. Gudkov, G. A. Еvstafiev, A. I. Dordopulo, A. A. Gulenok, and A. V. Bovkun. "TECHNIQUE OF C PROGRAM TRANSLATION FOR RECONFIGURABLE AND HYBRID COMPUTER SYSTEMS BASED ON FIELD-PROGRAMMABLE GATE ARRAYS." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 186 (December 2019): 54–60. http://dx.doi.org/10.14489/vkit.2019.12.pp.054-060.

Full text

Abstract:

In this paper, we thoroughly consider the technique of conversion of procedural programs in C to configuration files for field-programmable gate arrays used in the toolkit for programming of reconfigurable and hybrid computer systems. The creation of parallel program in the COLAMO (Common Oriented Language for Architecture of Multi Objects) language using the analysis results of information dependences in the initial procedural program and its further conversion to a parallel and pipeline form are the distinctive characteristics of the technique. We addressed the methods of scalar splitting and array extension by iterations, which are applied for the fulfillment of the single assignment and unique substitution rules in parallel program and the saving of information communications of the initial procedural program. The technique of conversion of automatically created parallel program to the scalable parallel and pipeline form is presented. The “Procrustes” preprocessor adapts the form for different architectures and configurations of reconfigurable and hybrid computer systems. Owing to the described methodology, it is possible to synthesize a resource-independent scalable COLAMO-application, which can adapt to available computational resource by changing of several constants in automatic mode without any considerable modification of the program source code. Then, the scalable COLAMO-applicationis translated by the COLAMO-translator into field-programmable gate arrays configuration files for the specified reconfigurable computer resource.

APA, Harvard, Vancouver, ISO, and other styles

14

KOCZ, J., L. J. GREENHILL, B. R. BARSDELL, G. BERNARDI, A. JAMESON, M. A. CLARK, J. CRAIG, et al. "A SCALABLE HYBRID FPGA/GPU FX CORRELATOR." Journal of Astronomical Instrumentation 03, no. 01 (March 2014): 1450002. http://dx.doi.org/10.1142/s2251171714500020.

Full text

Abstract:

Radio astronomical imaging arrays comprising large numbers of antennas, O(102–103), have posed a signal processing challenge because of the required O (N2) cross correlation of signals from each antenna and requisite signal routing. This motivated the implementation of a Packetized Correlator architecture that applies Field Programmable Gate Arrays (FPGAs) to the O (N) "F-stage" transforming time domain to frequency domain data, and Graphics Processing Units (GPUs) to the O (N2) "X-stage" performing an outer product among spectra for each antenna. The design is readily scalable to at least O(103) antennas. Fringes, visibility amplitudes and sky image results obtained during field testing are presented.

APA, Harvard, Vancouver, ISO, and other styles

15

Li, Ying, and P. Barker. "Field Evaluation of a Portable Whispering Gallery Mode Accelerometer." Sensors 18, no. 12 (November 29, 2018): 4184. http://dx.doi.org/10.3390/s18124184.

Full text

Abstract:

An accelerometer utilising the optomechanical coupling between an optical whispering gallery mode (WGM) resonance and the motion of the WGM cavity itself was prototyped and field-tested on a vehicle. We describe the assembly of this portable, battery operated sensor and the field-programmable gate array automation. Pre-trial testing using an electrodynamic shaker demonstrated linear scale-factors with <0.3% standard deviation ( ± 6 g range where g = 9.81 ms − 2 ), and a strong normalised cross-correlation coefficient (NCCC) of r ICP / WGM = 0.997 when compared with an integrated circuit piezoelectric (ICP) accelerometer. A noise density of 40 μ g Hz − 1 / 2 was obtained for frequencies of 2–7 kHz, increasing to 130 μ g Hz − 1 / 2 at 200 Hz, and 250 μ g Hz − 1 / 2 at 100 Hz. A reduction in the cross-correlation was found during the trial, r ICP / WGM = 0.36, which we attribute to thermal fluctuations, mounting differences, and the noisy vehicle environment. The deployment of this hand-fabricated sensor, shown to operate and survive during ±60 g shocks, demonstrates important steps towards the development of a chip-scale device.

APA, Harvard, Vancouver, ISO, and other styles

16

Sadeghi, Ali, Mina Zolfy Lighvan, and Paolo Prinetto. "Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm." Canadian Journal of Electrical and Computer Engineering 43, no. 4 (2020): 224–34. http://dx.doi.org/10.1109/cjece.2019.2962147.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Reddy, Naresh Kumar, and N. Suresh. "An Efficient approach for Design and Testing of FPGA Programming using LabVIEW." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 192. http://dx.doi.org/10.11591/ijres.v4.i3.pp192-200.

Full text

Abstract:

Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.

APA, Harvard, Vancouver, ISO, and other styles

18

Yoshizawa, Shingo, Noboru Hayasaka, Naoya Wada, and Yoshikazu Miyanaga. "VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform." Journal of Robotics and Mechatronics 17, no. 4 (August 20, 2005): 447–55. http://dx.doi.org/10.20965/jrm.2005.p0447.

Full text

Abstract:

This paper presents a VLSI architecture for a robust speech recognition system that enables high-speed, low-power operation. The proposed architecture improves recognition accuracy in noisy environments and realizes short-time response by implementing parallel and pipeline processing. We demonstrate improved processing time and power consumption by evaluating circuit performance in 0.25-μm CMOS technology. We also detail a verification platform that helps users implement our hardware-based robust speech recognition system. The verification platform facilitates software conversion to hardware and promptly provides testing environments on field-programmable gate arrays.

APA, Harvard, Vancouver, ISO, and other styles

19

Srivani, L., N. H. V. Krishna Giri, Shankar Ganesh, and V. Kamakoti. "Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization." Applied Soft Computing 27 (February 2015): 179–90. http://dx.doi.org/10.1016/j.asoc.2014.11.002.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Parvathi, M., N. Vasantha, and K. Satya Prasad. "BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (March 1, 2018): 1. http://dx.doi.org/10.11591/ijres.v7.i1.pp1-11.

Full text

Abstract:

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

APA, Harvard, Vancouver, ISO, and other styles

21

Figueiredo, Marco A., Clay S. Gloster, Mark Stephens, Corey A. Graves, and Mouna Nakkar. "Implementation of Multispectral Image Classification on a Remote Adaptive Computer." VLSI Design 10, no. 3 (January 1, 2000): 307–19. http://dx.doi.org/10.1155/2000/31983.

Full text

Abstract:

As the demand for higher performance computers for the processing of remote sensing science algorithms increases, the need to investigate new computing paradigms is justified. Field Programmable Gate Arrays enable the implementation of algorithms at the hardware gate level, leading to orders of magnitude performance increase over microprocessor based systems. The automatic classification of spaceborne multispectral images is an example of a computation intensive application that can benefit from implementation on an FPGA-based custom computing machine (adaptive or reconfigurable computer). A probabilistic neural network is used here to classify pixels of a multispectral LANDSAT-2 image. The implementation described utilizes Java client/server application programs to access the adaptive computer from a remote site. Results verify that a remote hardware version of the algorithm (implemented on an adaptive computer) is significantly faster than a local software version of the same algorithm (implemented on a typical general-purpose computer).

APA, Harvard, Vancouver, ISO, and other styles

22

Tang, Zhi-Ling, Si-Min Li, and Li-Juan Yu. "Implementation of Deep Learning-based Automatic Modulation Classifier on FPGA SDR Platform." Electronics 7, no. 7 (July 19, 2018): 122. http://dx.doi.org/10.3390/electronics7070122.

Full text

Abstract:

Intelligent radios collect information by sensing signals within the radio spectrum, and the automatic modulation recognition (AMR) of signals is one of their most challenging tasks. Although the result of a modulation classification based on a deep neural network is better, the training of the neural network requires complicated calculations and expensive hardware. Therefore, in this paper, we propose a master–slave AMR architecture using the reconfigurability of field-programmable gate arrays (FPGAs). First, we discuss the method of building AMR, by using a stack convolution autoencoder (CAE), and analyze the principles of training and classification. Then, on the basis of the radiofrequency network-on-chip architecture, the constraint conditions of AMR in FPGA are proposed from the aspects of computing optimization and memory access optimization. The experimental results not only demonstrated that AMR-based CAEs worked correctly, but also showed that AMR based on neural networks could be implemented on FPGAs, with the potential for dynamic spectrum allocation and cognitive radio systems.

APA, Harvard, Vancouver, ISO, and other styles

23

Giordano, Raffaele, Dario Barbieri, Sabrina Perrella, and Roberto Catalano. "Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs." Instruments 3, no. 4 (October 14, 2019): 56. http://dx.doi.org/10.3390/instruments3040056.

Full text

Abstract:

The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration. These effects may alter the functionality until the next reconfiguration of the device. In this work, we present the radiation testing of a high-speed serial link hardened by a new, custom scrubber designed for Xilinx FPGAs. We compared the performance of our scrubber to the Xilinx Single Event Mitigation (SEM) controller and we measured the impact of the scrubbers on the reliability of the link. Our results show that our scrubber may improve reliability up to 23 times over the SEM.

APA, Harvard, Vancouver, ISO, and other styles

24

Tsoeunyane, Lekhobola, Simon Winberg, and Michael Inggs. "Automatic Configurable Hardware Code Generation for Software-Defined Radios." Computers 7, no. 4 (October 19, 2018): 53. http://dx.doi.org/10.3390/computers7040053.

Full text

Abstract:

The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used.

APA, Harvard, Vancouver, ISO, and other styles

25

Viejo, Julian, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostua, and German Cano. "High-Performance Time Server Core for FPGA System-on-Chip." Electronics 8, no. 5 (May 11, 2019): 528. http://dx.doi.org/10.3390/electronics8050528.

Full text

Abstract:

This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.

APA, Harvard, Vancouver, ISO, and other styles

26

Fernández, Carolina, Sergio Giménez, Eduard Grasa, and Steve Bunch. "A P4-Enabled RINA Interior Router for Software-Defined Data Centers." Computers 9, no. 3 (September 2, 2020): 70. http://dx.doi.org/10.3390/computers9030070.

Full text

Abstract:

The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.

APA, Harvard, Vancouver, ISO, and other styles

27

López-Valcárcel, Luis A., and Manuel García Sánchez. "A Wideband Radio Channel Sounder for Non-Stationary Channels: Design, Implementation and Testing." Electronics 10, no. 15 (July 30, 2021): 1838. http://dx.doi.org/10.3390/electronics10151838.

Full text

Abstract:

The increasing bandwidths and frequencies proposed for new mobile communications give rise to new challenges for system designers. Channel sounding and channel characterization are important tasks to provide useful information for the design of systems, protocols, and techniques to fight the propagation impairments. In this paper, we present a novel radio channel sounder capable of dealing with non-stationary channels. It can be operated in real-time and has a compact size to ease transport. For versatility and cost purposes, the core of the system is implemented in Field Programmable Gate Arrays (FPGAs). Three measurement campaigns have been conducted to illustrate the performance of the sounder in both static and non-static channels. In its current configuration, the sounder reaches an RF null-to-null bandwidth of 1 GHz, providing a delay resolution of 2 ns, a maximum measurable Doppler shift of 7.63 kHz, and 4.29 s of continuous acquisition time. A comparison with other channel sounders in the literature reveals that our proposal achieves a good combination of performance, cost, and size.

APA, Harvard, Vancouver, ISO, and other styles

28

Buch, Kaushal D., Yashwant Gupta, and B. Ajith Kumar. "Variable Correlation Digital Noise Source on FPGA — A Versatile Tool for Debugging Radio Telescope Backends." Journal of Astronomical Instrumentation 03, no. 03n04 (December 2014): 1450007. http://dx.doi.org/10.1142/s225117171450007x.

Full text

Abstract:

Contemporary wideband radio telescope backends are generally developed on Field Programmable Gate Arrays (FPGA) or hybrid (FPGA+GPU) platforms. One of the challenges faced while developing such instruments is the functional verification of the signal processing backend at various stages of development. In the case of an interferometer or pulsar backend, the typical requirement is for one independent noise source per input, with provision for a common, correlated signal component across all the inputs, with controllable level of correlation. This paper describes the design of a FPGA-based variable correlation Digital Noise Source (DNS), and its applications to built-in testing and debugging of correlators and beamformers. This DNS uses the Central Limit Theorem-based approach for generation of Gaussian noise, and the architecture is optimized for resource requirements and ease of integration with existing signal processing blocks on FPGA.

APA, Harvard, Vancouver, ISO, and other styles

29

Lu, Shyue-Kung, Fu-Min Yeh, and Jen-Sheng Shih. "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs." VLSI Design 15, no. 1 (January 1, 2002): 397–406. http://dx.doi.org/10.1080/1065514021000012011.

Full text

Abstract:

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

APA, Harvard, Vancouver, ISO, and other styles

30

Kumari, Cms Amrutha, and Syed Jahangir Badashah. "Image Edge Detection Using FPGA." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 1 (July 25, 2013): 1192–200. http://dx.doi.org/10.24297/ijct.v10i1.3323.

Full text

Abstract:

Medical imaging often involves the injection of contrast agents and subsequent analysis of tissue enhancement patterns. X-ray angiograms are projections of 3D reality into 2D representations, there is a fair amount of self occlusion among the vessels, hence one cannot extract the vessels directly using the image intensities or gradients (edge) alone. Vessels extraction from angiogram images is useful for blood vessels measurement and computer visualizations of the coronary artery. This project describes the algorithm for automatic segmentation of coronary arteries in digital X-ray projections here an improved k-means algorithm is proposed. The performance of the proposed algorithm is compared with other techniques.Â A methodology for implementing real-time DSP applications on a field programmable gate arrays (FPGA) using Xilinx System Generator (XSG) for Mat lab is presented in this paper. It presents the architecture for Edge Detection using Sobel Filter for image processing using Xilinx System Generator. The design was implemented targeting a Spartan3 a DSP 3400 device (XC3SD3400A-4FGG676C) then a vertex 5 (xc5vlx50-1ff676) .the edge detection methods has been verified successfully with no visually perceptual errors in the resulted images.

APA, Harvard, Vancouver, ISO, and other styles

31

Ziebinski, Adam, and Stanwlaw Swierc. "Soft Core Processor Generated Based on the Machine Code of the Application." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650029. http://dx.doi.org/10.1142/s0218126616500298.

Full text

Abstract:

Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4).

APA, Harvard, Vancouver, ISO, and other styles

32

Baklouti, Mouna, and Mohamed Abid. "Multi-Softcore Architecture on FPGA." International Journal of Reconfigurable Computing 2014 (2014): 1–13. http://dx.doi.org/10.1155/2014/979327.

Full text

Abstract:

To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs) are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication).

APA, Harvard, Vancouver, ISO, and other styles

33

Cauwe, Maarten, Bart Vandevelde, Chinmay Nawghane, Marnix Van De Slyeke, Erwin Bosman, Joachim Verhegge, Alexia Coulon, and Stan Heltzel. "High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications." Journal of Microelectronics and Electronic Packaging 17, no. 3 (July 1, 2020): 79–88. http://dx.doi.org/10.4071/imaps.1212898.

Full text

Abstract:

Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.

APA, Harvard, Vancouver, ISO, and other styles

34

Al-Hashimi, Ahmed, Anis Nurashikin Nordin, and Amelia Wong Azman. "Design of a Reconfigurable, Modular and Multi-Channel Bioimpedance Spectroscopy System." Indonesian Journal of Electrical Engineering and Computer Science 8, no. 2 (November 1, 2017): 428. http://dx.doi.org/10.11591/ijeecs.v8.i2.pp428-440.

Full text

Abstract:

This paper presents the design and implementation of a multichannel bio-impedance spectroscopy system on field programmable gate arrays (FPGA). The proposed system is capable of acquiring multiple signals from multiple bio-impedance sensors, process the data on the FPGA and store the final data in the on-board Memory. The system employs the Digital Automatic Balance Bridge (DABB) method to acquire data from biosensors. The DABB measures initial data of a known impedance to extrapolate the value of the impedance for the device under test. This method offers a simpler design because the balancing of the circuit is done digitally in the FPGA rather than using an external circuit. Calculations of the impedance values for the device under test were done in the processor. The final data is sent to an onboard Flash Memory to be stored for later access. The control unit handles the interfacing and the scheduling between these different modules (Processor, Flash Memory) as well as interfacing to multiple Balance Bridge and multiple biosensors. The system has been simulated successfully and has comparable performance to other FPGA based solutions. The system has a robust design that is capable of handling and interfacing input from multiple biosensors. Data processing and storage is also performed with minimal resources on the FPGA.

APA, Harvard, Vancouver, ISO, and other styles

35

Babeshko, Eugene, Vyacheslav Kharchenko, Kostiantyn Leontiiev, and Eugene Ruchkov. "PRACTICAL ASPECTS OF OPERATING AND ANALYTICAL RELIABILITY ASSESSMENT OF FPGA-BASED I&C SYSTEMS." RADIOELECTRONIC AND COMPUTER SYSTEMS, no. 3 (September 28, 2020): 75–83. http://dx.doi.org/10.32620/reks.2020.3.08.

Full text

Abstract:

Operating reliability assessment of instrumentation and control systems (I&Cs) is always one of the most important activities, especially for critical domains such as nuclear power plants (NPPs). It is an important source of I&C reliability information preferable to lab testing data because it provides information on I&C reliability under real use conditions. That is the reason that now it is a common practice for companies to have an established process of collecting operating reliability data on a large variety of used components on regular basis, maintaining a database with failure information, total operation time, typical failure modes, etc. The intensive use of complicated components like field-programmable gate arrays (FPGAs) in I&C which appear in upgrades and newly-built nuclear power plants makes the task to develop and validate advanced operating reliability assessment methods that consider specific technology features very topical. Increased integration densities make the reliability of integrated circuits the most crucial point in modern NPP I&Cs. Moreover, FPGAs differ in some significant ways from other integrated circuits: they are shipped as blanks and are very dependent on the design configured into them. Furthermore, FPGA design could be changed during planned NPP outage for different reasons. Considering all possible failure modes of FPGA-based NPP instrumentation and control systems at the design stage is a quite challenging task. Therefore, operating reliability assessment is one of the most preferable ways to perform a comprehensive analysis of FPGA-based NPP I&Cs. Based on information in the literature and own experience, operational vs analytical reliability could be pretty far apart. For that reason, analytical reliability assessment using reliability block diagrams (RBD), failure modes, effects and diagnostics analysis (FMEDA), fault tree analysis (FTA), fault insertion testing (FIT), and other techniques and their combinations are important to meet requirements for such systems. The paper summarizes our experience in operating and analytical reliability assessment of FPGA based NPP I&Cs.

APA, Harvard, Vancouver, ISO, and other styles

36

Dumez-Viou, Cédric, Rodolphe Weber, and Philippe Ravier. "Multi-Level Pre-Correlation RFI Flagging for Real-Time Implementation on UniBoard." Journal of Astronomical Instrumentation 05, no. 04 (December 2016): 1641019. http://dx.doi.org/10.1142/s2251171716410191.

Full text

Abstract:

Because of the denser active use of the spectrum, and because of radio telescopes higher sensitivity, radio frequency interference (RFI) mitigation has become a sensitive topic for current and future radio telescope designs. Even if quite sophisticated approaches have been proposed in the recent years, the majority of RFI mitigation operational procedures are based on post-correlation corrupted data flagging. Moreover, given the huge amount of data delivered by current and next generation radio telescopes, all these RFI detection procedures have to be at least automatic and, if possible, real-time. In this paper, the implementation of a real-time pre-correlation RFI detection and flagging procedure into generic high-performance computing platforms based on field programmable gate arrays (FPGA) is described, simulated and tested. One of these boards, UniBoard, developed under a Joint Research Activity in the RadioNet FP7 European programme is based on eight FPGAs interconnected by a high speed transceiver mesh. It provides up to 4 TMACs with ®Altera Stratix IV FPGA and 160 Gbps data rate for the input data stream. The proposed concept is to continuously monitor the data quality at different stages in the digital preprocessing pipeline between the antennas and the correlator, at the station level and the core level. In this way, the detectors are applied at stages where different time–frequency resolutions can be achieved and where the interference-to-noise ratio (INR) is maximum right before any dilution of RFI characteristics by subsequent channelizations or signal recombinations. The detection decisions could be linked to a RFI statistics database or could be attached to the data for later stage flagging. Considering the high in–out data rate in the pre-correlation stages, only real-time and go-through detectors (i.e. no iterative processing) can be implemented. In this paper, a real-time and adaptive detection scheme is described. An ongoing case study has been set up with the Electronic Multi-Beam Radio Astronomy Concept (EMBRACE) radio telescope facility at Nançay Observatory. The objective is to evaluate the performances of this concept in term of hardware complexity, detection efficiency and additional RFI metadata rate cost. The UniBoard implementation scheme is described.

APA, Harvard, Vancouver, ISO, and other styles

37

McNelles, Phillip, and Lixuan Lu. "Design of a Tritium-In-Air Monitor Using Field-Programmable Gate Arrays." Journal of Nuclear Engineering and Radiation Science 2, no. 4 (October 12, 2016). http://dx.doi.org/10.1115/1.4033088.

Full text

Abstract:

Field-programmable gate arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, particle detectors, and health physics. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to increased production of tritium, which poses a health risk and must be monitored by tritium-in-air monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of carbon-14 and the addition of noble-gas compensation, are incorporated into a new FPGA-based TAM along with the standard functions included in the original microprocessor-based TAM. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. Potential issues caused by radiation interactions with the FPGA are beyond the scope of this work.

APA, Harvard, Vancouver, ISO, and other styles

38

"Design and Implementation of Perceptron Neuron in Machine Learning for Handwritten Character Recognition." Regular 9, no. 10 (August 10, 2020): 357–63. http://dx.doi.org/10.35940/ijitee.h6680.0891020.

Full text

Abstract:

Due to the exponential increase of electronic devices that are connected to the Internet, the amount of data that they produce have grown to the same extent. In order to face the processing of these data, the use of some automatic learning algorithms, also known as Machine Learning, has become widespread. The most popular is the one known as neural networks. These algorithms need a great deal of resources to compute all their operations, and because of that, they have been traditionally implemented in application specific integrated circuits. However, recently there have been a boom in implementations in field programmable gate arrays, also known as FPGAs. These allow greater parallelism in the implementation of the algorithms. Field Programmable Gate Arrays (FPGA) implementation based feature extraction method is proposed in this paper. This particular application is handwritten offline digit recognition. The classification depends on simple 2 layer MultiLayer Perceptron (MLP). The particular feature extraction approach is suitable for execution of FPGA because it is utilized with subtraction and addition operations. From Standard database handwritten digit images of normalized 40×40 pixel the features are extracted by the proposed method. It has been discovered by experiential outcomes that 85% accuracy is achieved by proposed system. Overall, as compared to other systems, it is less complex, more accurate and simple. Further this project explains IEE-754 format single precision floating point MAC unit’s FPGA implementation which is utilized for feeding the neurons weighted inputs in artificial neural networks. Data representation range is improved by floating point numbers utilization to a higher number from smaller number that is highly suggested for Artificial Neuron Network. The code is developed in HDL, simulated and synthesis results are extracted using Xilinx synthesis tools .In order to validate its computational accuracy of the FFT, an MATLAB validation script is used to verify the output of HDL with standard reference model.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Field programmable gate arrays Automatic testing'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles