Relevant bibliographies by topics / Field programmable gate arrays – Design and construction

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Field programmable gate arrays – Design and construction'

Author: Grafiati
Published: 4 June 2021
Last updated: 29 January 2023

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Journal articles on the topic "Field programmable gate arrays – Design and construction"

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Le, Khoa N., Ivan W. H. Fung, Vivian W. Y. Tam, Leslie Yip, and Eric W. M. Lee. "Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays." International Journal of Information Technology Project Management 5, no. 4 (October 2014): 24–49. http://dx.doi.org/10.4018/ijitpm.2014100102.

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Genetic algorithms (GAs) have found many applications in various fields such as physics, signal processing, artificial intelligence and recently construction engineering management. For a long time, GAs are usually criticized to be time-consuming, making it unpractical for real-time applications. This paper presents a new technique which can be used: (1) to automate construction activities, and (2) to improve building information modeling which has become an attractive research topic around the world. Different from the generic GA techniques employed in the literature, this paper proposes a new GA using hardware with field-programmable gate arrays. The proposed technique is shown to improve speed and lessen computational power. Hardware implementation of GA using static random access memory-based field-programmable gate arrays with synthesizable very hardware description language coding is introduced. Detailed analyses on the field-programmable gate arrays are given which show that it is suitable for real-time applications. As a result, GA is modified so that it can be implemented in series and parallel which can greatly improve computational hardware performance. Configuration of parallelization is available with a peripheral component interconnect interface, which further helps to form a fast optimization tool for real-time applications. The ultimate goal of this paper is thus to design an effective GA technique which can be employed to support building information modeling and to effectively automate critical processes in construction projects.
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Berezin, N. M., I. E. Chernetskaya, V. S. Panishchev, and A. M. Shabarov. "Development of a device for multiplying numbers by means of FPGA." Journal of Physics: Conference Series 2142, no. 1 (December 1, 2021): 012001. http://dx.doi.org/10.1088/1742-6596/2142/1/012001.

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Abstract The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.
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Zhang, Chunyu, Shouxiang Wang, Ruxun He, Qianyu Zhao, and Kai Wang. "Design and Construction of a Low Cost All-Digital Phase Locked Loop Based on Field Programmable Gate Array." Journal of Physics: Conference Series 1972, no. 1 (July 1, 2021): 012054. http://dx.doi.org/10.1088/1742-6596/1972/1/012054.

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Domínguez Conde, Cristina, Jonas Philipp Lüke, and Fernando Rosa González. "Implementation of a Depth from Light Field Algorithm on FPGA." Sensors 19, no. 16 (August 15, 2019): 3562. http://dx.doi.org/10.3390/s19163562.

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A light field is a four-dimensional function that grabs the intensity of light rays traversing an empty space at each point. The light field can be captured using devices designed specifically for this purpose and it allows one to extract depth information about the scene. Most light-field algorithms require a huge amount of processing power. Fortunately, in recent years, parallel hardware has evolved and enables such volumes of data to be processed. Field programmable gate arrays are one such option. In this paper, we propose two hardware designs that share a common construction block to compute a disparity map from light-field data. The first design employs serial data input into the hardware, while the second employs view parallel input. These designs focus on performing calculations during data read-in and producing results only a few clock cycles after read-in. Several experiments were conducted. First, the influence of using fixed-point arithmetic on accuracy was tested using synthetic light-field data. Also tests on actual light field data were performed. The performance was compared to that of a CPU, as well as an embedded processor. Our designs showed similar performance to the former and outperformed the latter. For further comparison, we also discuss the performance difference between our designs and other designs described in the literature.
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Wiśniewski, Remigiusz, Marcin Wojnakowski, and Zhiwu Li. "Design and Verification of Petri-Net-Based Cyber-Physical Systems Oriented toward Implementation in Field-Programmable Gate Arrays—A Case Study Example." Energies 16, no. 1 (December 21, 2022): 67. http://dx.doi.org/10.3390/en16010067.

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This paper presents a novel design approach of a Petri-net-based cyber-physical system (CPS). The idea is oriented toward implementation in a field-programmable gate array (FPGA). The proposed technique permits error detection in the system at the early specification stage in order to reduce the time and prototyping cost of the CPS. Due to the state explosion problem, the traditional verification methods have exponential computational complexity. In contrast, we show that under certain assumptions, the proposed algorithm is able to detect possible errors in the system even in cubic O(|T|2|P|) time. Furthermore, all the required steps of the proposed design method are presented and discussed. The idea is illustrated by a real-life case study example of a traffic light crossroad. The system was modelled, analysed, implemented, and finally validated within the FPGA device (Virtex-5 family).
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Jessa, Mieczysław, and Łukasz Matuszewski. "Producing Random Bits with Delay-Line-Based Ring Oscillators." International Journal of Electronics and Telecommunications 59, no. 1 (March 1, 2013): 41–50. http://dx.doi.org/10.2478/eletel-2013-0005.

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Abstract One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element.
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Pfänder, O. A., H. J. Pfleiderer, and S. W. Lachowicz. "Configurable multiplier modules for an adaptive computing system." Advances in Radio Science 4 (September 6, 2006): 231–36. http://dx.doi.org/10.5194/ars-4-231-2006.

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Abstract. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However, optimized arithmetic blocks in course-grain reconfigurable arrays as well as field-programmable architectures still play an important role. In countless digital systems and signal processing applications, the multiplication is one of the critical challenges, where in many cases a trade-off between area usage and data throughput has to be made. But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation. In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated processing. The 3-D-SoftChip architecture uses a novel approach to 3-dimensional integration based on flip-chip bonding with indium bumps. The modular construction, the introduction of interfaces to realize the exchange of intermediate data, and the reconfigurable sign handling approach will be explained, as well as a beneficial way to handle and distribute the numerous required control signals.
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Fang, Qizhi, Yuxuan Liu, and Lili Zhang. "Design and Implementation of a Lossless Compression System for Hyperspectral Images." Traitement du Signal 37, no. 5 (November 25, 2020): 745–52. http://dx.doi.org/10.18280/ts.370506.

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Despite its popularity, the hyperspectral image compression algorithm recommended by the Consultative Committee for Space Data Systems (CCSDS) faces a long delay of the feedback loop and complex computations in the modes of band sequential (BSQ) and band interleaved by line (BIL). After analyzing the features of the CCSDS algorithm, this paper proposes a forward prediction method based on the xc7k325tffg9000 field programmable gate array (FPGA) chip (Xilinx Inc.), and adjusts the calculation flow of the CCSDS algorithm, aiming to shorten the time delay in the feedback loop. In addition, full-pipeline construction was implemented on FPGA board to realize real-time processing of data, and dynamic configuration of image parameters. Through functional simulation and off-board test, it is learned that, for the speed-insensitive path, the optimized algorithm can realize the complex operations of the original algorithm with less hardware resources; for hyperspectral image data with an effective input bit width of 12bit, the proposed method can reach a maximum operating frequency of 103MHz, and the data throughput of 103M samples per second (1.237Gbps).
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Mahmood, Zainab H., and Mahmood K. Ibrahem. "HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV." Iraqi Journal of Information & Communications Technology 2, no. 2 (November 1, 2019): 44–57. http://dx.doi.org/10.31987/ijict.2.2.69.

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In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.
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Song, Yuefeng, Yongxin Zhu, Tianhao Nan, Junjie Hou, Sen Du, and Shijin Song. "Accelerating Faceting Wide-Field Imaging Algorithm with FPGA for SKA Radio Telescope as a Vast Sensor Array." Sensors 20, no. 15 (July 22, 2020): 4070. http://dx.doi.org/10.3390/s20154070.

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The SKA (Square Kilometer Array) radio telescope will become the most sensitive telescope by correlating a huge number of antenna nodes to form a vast array of sensors in a region over one hundred kilometers. Faceting, the wide-field imaging algorithm, is a novel approach towards solving image construction from sensing data where earth surface curves cannot be ignored. However, the traditional processor of cloud computing, even if the most sophisticated supercomputer is used, cannot meet the extremely high computation performance requirement. In this paper, we propose the design and implementation of high-efficiency FPGA (Field Programmable Gate Array) -based hardware acceleration of the key algorithm, faceting in SKA by focusing on phase rotation and gridding, which are the most time-consuming phases in the faceting algorithm. Through the analysis of algorithm behavior and bottleneck, we design and optimize the memory architecture and computing logic of the FPGA-based accelerator. The simulation and tests on FPGA are done to confirm the acceleration result of our design and it is shown that the acceleration performance we achieved on phase rotation is 20× the result of the previous work. We then further designed and optimized an efficient microstructure of loop unrolling and pipeline for the gridding accelerator, and the designed system simulation was done to confirm the performance of our structure. The result shows that the acceleration ratio is 5.48 compared to the result tested on software in gridding parts. Hence, our approach enables efficient acceleration of the faceting algorithm on FPGAs with high performance to meet the computational constraints of SKA as a representative vast sensor array.
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Dissertations / Theses on the topic "Field programmable gate arrays – Design and construction"

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Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
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Baskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Ng, Chiu-wa, and 吳潮華. "Bit-stream signal processing on FPGA." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2009. http://hub.hku.hk/bib/B41633842.

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Nsumbu, Cassandra Daviane. "Development of a soft-core based power electronic conversion controller." Thesis, Cape Peninsula University of Technology, 2014. http://hdl.handle.net/20.500.11838/2379.

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Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2014.
The application of digital control techniques has become dominant in power electronics owing to several advantages they present, when compared to analogue solutions. Their development is based on the use of microprocessors and microcontrollers, such as Application Specific Integrated Circuit (ASIC), Digital signal processors (DSP), Field Programmable Gate Arrays (FPGA), or a combination of these devices. This thesis presents an investigation of a soft-core based FPGA control system as a solution for power electronic applications. The aim was the development and implementation of a conversion controller, which purpose is to supply control inputs in the form of digital Pulse Width Modulation (PWM) signals, to a number of power electronic applications, such as single half and full bridge DC-DC converters, three phase and multicell inverters. The PWM control technique is achieved via their power semiconductor switching devices. These PWM control signals are necessary for the high frequency conversion of an analog input voltage (AC, DC or unregulated) to an analog output voltage of another level (AC or DC). This was intended to be achieved by exploiting and combining the advantages that FPGA and embedded processors provide such as high reconfigurability and multipurpose ability. This controller’s digital outputs, namely PWM switching signals, can be directly delivered to an analog signal amplification circuit to create an adequate voltage level before being processed by the converters’ switches.
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Messa, Norman C. "Design implementation into field programmable gate arrays." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.

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Mutigwe, Charles. "Automatic synthesis of application-specific processors." Thesis, Bloemfontein : Central University of Technology, Free State, 2012. http://hdl.handle.net/11462/163.

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Thesis (D. Tech. (Engineering: Electrical)) -- Central University of technology, Free State, 2012
This thesis describes a method for the automatic generation of appli- cation speci_c processors. The thesis was organized into three sepa- rate but interrelated studies, which together provide: a justi_cation for the method used, a theory that supports the method, and a soft- ware application that realizes the method. The _rst study looked at how modern day microprocessors utilize their hardware resources and it proposed a metric, called core density, for measuring the utilization rate. The core density is a function of the microprocessor's instruction set and the application scheduled to run on that microprocessor. This study concluded that modern day microprocessors use their resources very ine_ciently and proposed the use of subset processors to exe- cute the same applications more e_ciently. The second study sought to provide a theoretical framework for the use of subset processors by developing a generic formal model of computer architecture. To demonstrate the model's versatility, it was used to describe a number of computer architecture components and entire computing systems. The third study describes the development of a set of software tools that enable the automatic generation of application speci_c proces- sors. The FiT toolkit automatically generates a unique Hardware Description Language (HDL) description of a processor based on an application binary _le and a parameterizable template of a generic mi- croprocessor. Area-optimized and performance-optimized custom soft processors were generated using the FiT toolkit and the utilization of the hardware resources by the custom soft processors was character- ized. The FiT toolkit was combined with an ANSI C compiler and a third-party tool for programming _eld-programmable gate arrays (FPGAs) to create an unconstrained C-to-silicon compiler.
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Self, R. P. "Software-orientated system design for field programmable gate arrays." Thesis, University of Essex, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.397736.

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Sareen, Aman. "Reconfigurable design for pattern recognition using field programmable gate arrays." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175625525.

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Ebert, Dean A. "Design and development of a configurable fault-tolerant processor (CFTP) for space applications." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Jun%5FEbert.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003.
Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 219-224). Also available online.
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Langlois, Joseph Mathieu Pierre. "Design and implementation of wide band quadrature demodulators on field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/Mq44914.pdf.

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Books on the topic "Field programmable gate arrays – Design and construction"

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Design recipes for FPGAs. Oxford: Newnes, 2007.

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Battezzati, Niccolò. Reconfigurable field programmable gate arrays for mission-critical applications. New York: Springer, 2011.

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1950-, Smailagic Asim, ed. Digital systems design and prototyping using field programmable logic. Boston, Mass: Kluwer Academic Publishers, 1997.

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Advanced FPGA design: Architecture, implementation, and optimization. Hoboken, NJ: Wiley-Interscience, 2007.

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Dian lu she ji shi xi: FPGA she ji pian. Taibei Xian Zhonghe Shi: Xin wen jing kai fa chu ban gu fen you xian gong si, 2010.

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David E. Van den Bout. FPGA workout: Beginning exercises with the Intel FLEXlogic FPGA. Apex, N.C: X Engineering Software Systems Corp., 1994.

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Huffmire, Ted. Handbook of FPGA design security. Dordrecht: Springer, 2010.

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Beckert, René. Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration. Dresden: TUDpress, 2008.

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Beckert, René. Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration. Dresden: TUDpress, 2008.

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Kuo pin tong xin xi tong de FPGA she ji. Beijing Shi: Guo fang gong ye chu ban she, 2013.

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Book chapters on the topic "Field programmable gate arrays – Design and construction"

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Barkalov, Alexander, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, and Grzegorz Bazydlo. "Field Programmable Gate Arrays in FSM Design." In Logic Synthesis for FPGA-Based Finite State Machines, 33–64. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-24202-6_2.

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Hajji, Bekkay, Adel Mellit, and Loubna Bouselham. "Introduction to Field Programmable Gate Arrays (FPGA)." In A Practical Guide for Simulation and FPGA Implementation of Digital Design, 3–18. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0615-2_1.

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Meyer-Baese, Uwe. "Microprocessor Design." In Digital Signal Processing with Field Programmable Gate Arrays, 631–738. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-642-45309-0_9.

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Rodríguez-Andina, Juan J., J. Alvarez, and E. Mandado. "Design of safety systems using Field Programmable Gate Arrays." In Field-Programmable Logic Architectures, Synthesis and Applications, 341–43. Berlin, Heidelberg: Springer Berlin Heidelberg, 1994. http://dx.doi.org/10.1007/3-540-58419-6_118.

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Snider, Ross. "Chapter 2: Introduction to System-on-Chip Field Programmable Gate Arrays." In Advanced Digital System Design using SoC FPGAs, 17–24. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-15416-4_2.

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Sangiovanni-Vincentelli, Alberto. "Some considerations on Field Programmable Gate Arrays and their impact on system design." In Lecture Notes in Computer Science, 26–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/3-540-57091-8_26.

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Valdés, M. D., M. J. Moure, L. Rodríguez, and A. del Río. "Interactive practical teaching of digital circuits design by means of Field Programmable Gate Arrays." In Computer Aided Learning and Instruction in Science and Engineering, 408–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/bfb0022632.

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Bauer, Lars, Hongyan Zhang, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, and Jörg Henkel. "Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures." In Dependable Embedded Systems, 277–302. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_12.

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AbstractRuntime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable parts are typically manufactured in the latest technology, they may suffer from aging and environmentally induced dependability threats. In this chapter, strategic online test methods for dependable runtime-reconfigurable architectures as well as cross-layer optimizations for high reliability and lifetime are developed. Firstly, two orthogonal online tests are proposed that ensure reliable configuration of the reconfigurable fabric and aid fault detection. Secondly, a novel design method called module diversification is presented that enables self-repair of the system in case of faults caused by degradation effects as well as single-event upsets in the configuration. Thirdly, a novel stress-aware placement method is proposed that aims for slowing down system degradation by aging effects. The combined methods ensure reliable operation across architectural and gate level and allow to prolong the lifetime of dependable runtime-reconfigurable architectures.
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"Field-Programmable Gate Arrays." In Logic Design, 243–52. CRC Press, 2003. http://dx.doi.org/10.1201/9780203010150-26.

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Muroga, Saburo. "Field-Programmable Gate Arrays." In Logic Design, 22–1. CRC Press, 2003. http://dx.doi.org/10.1201/9780203010150.ch22.

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Conference papers on the topic "Field programmable gate arrays – Design and construction"

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Chen, Shili, Guangde Song, Shijiu Jin, and Xianglin Zhan. "The Design of an Ultrasonic Phased Array System on Pipelines’ Weld Inspection." In 2004 International Pipeline Conference. ASMEDC, 2004. http://dx.doi.org/10.1115/ipc2004-0719.

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Phased arrays generate ultrasonic waves by using recisely-defined time delays for each element in an ultrasonic array group, this permits constructive and destructive interference of the wavefronts to form the pre-defined beam. So, ultrasonic phased arrays are well suited to weld inspections. First, beams can be multiplexed across the array, in what is called “electronic scanning”. This permits very rapid inspections of components, typically an order of magnitude faster than a single transducer raster scan. Second, the beam can be swept through a range of angles without moving the array; this is called “beam steering”, and the inspections are typically called “azimuthal” scans or “sectorial” scans. Before weld inspecting, the time delays between elements were computed using a specific model and compared to experimental delays obtained using through transmission tests. This paper describes the application of phased array on pipelines’ weld inspection. The detail hardware designs of linear phased arrays system and the summary of system performance are presented. This inspection system includes eight ultrasonic signal transmitting and receiving circuit units, which are used to control time sequence of ultrasonic beam and select channel used for waves construction, and amplify the received ultrasonic signal. Each unit is connected with 16 probe elements (total 128 elements in this system), and can receive 4-way ultrasonic signals (channel selection is done by RF switching). Additional performance is gained by intensively using FPGA (Field Programmable Gate Arrays) technology for memory and delay counters. Since the working frequency or FPGA is 100MHz, the delay time less than 10 ns is realized by analogue delay line. This system not only has the functions of conventional ultrasonic inspector, but also can display the defect shape and its size on the screen.
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Jyothi, Vinayaka, Ashik Poojari, Richard Stern, and Ramesh Karri. "Fingerprinting Field Programmable Gate Arrays." In 2017 IEEE 35th International Conference on Computer Design (ICCD). IEEE, 2017. http://dx.doi.org/10.1109/iccd.2017.58.

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Abd-El-Barr, M., and Z. Vranesic. "Design issues in field programmable gate arrays (FPGAs)." In Proceedings of International Conference on Microelectronics (ICM'99). IEEE, 2000. http://dx.doi.org/10.1109/icm.2000.884832.

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Donzellini, Giuliano, and Domenico Ponta. "Introducing Field Programmable Gate Arrays with deeds projects." In 2014 4th Interdisciplinary Engineering Design Education Conference (IEDEC). IEEE, 2014. http://dx.doi.org/10.1109/iedec.2014.6784681.

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Alghurair, Dina, and Sefwan S. Al-Rawi. "Design of Sobel operator using Field Programmable Gate Arrays." In 2013 International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE). IEEE, 2013. http://dx.doi.org/10.1109/taeece.2013.6557341.

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Bratt, A., and I. Macbeth. "Design and Implementation of a Field Programmable Analogue Array." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242434.

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Lee, Edmund, Guy Lemieux, and Shahriar Mirabbasi. "Interconnect driver design for long wires in field-programmable gate arrays." In 2006 IEEE International Conference on Field Programmable Technology. IEEE, 2006. http://dx.doi.org/10.1109/fpt.2006.270299.

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Zilic, Z., and Z. G. Vranesic. "Using BDDs to Design ULMs for FPGAs." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242252.

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Oner, K., L. A. Barroso, S. Iman, Jaeheon Jeong, K. Ramamurthy, and M. Dubois. "The Design of RPM: An FPGA-based Multiprocessor Emulator." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.241946.

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Yao-Wen Chang, D. F. Wong, and C. K. Wong. "Universal Switch-Module Design for Symmetric-Array-Based FPGAs." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242433.

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Reports on the topic "Field programmable gate arrays – Design and construction"

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Tyler, Stephen C. The Design of a Frequency Domain Interference Excision Processor Using Field Programmable Gate Arrays. Fort Belvoir, VA: Defense Technical Information Center, January 2005. http://dx.doi.org/10.21236/ada432369.

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