Journal articles: 'Field programmable gate arrays – Design and construction'

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Le, Khoa N., Ivan W. H. Fung, Vivian W. Y. Tam, Leslie Yip, and Eric W. M. Lee. "Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays." International Journal of Information Technology Project Management 5, no. 4 (October 2014): 24–49. http://dx.doi.org/10.4018/ijitpm.2014100102.

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Genetic algorithms (GAs) have found many applications in various fields such as physics, signal processing, artificial intelligence and recently construction engineering management. For a long time, GAs are usually criticized to be time-consuming, making it unpractical for real-time applications. This paper presents a new technique which can be used: (1) to automate construction activities, and (2) to improve building information modeling which has become an attractive research topic around the world. Different from the generic GA techniques employed in the literature, this paper proposes a new GA using hardware with field-programmable gate arrays. The proposed technique is shown to improve speed and lessen computational power. Hardware implementation of GA using static random access memory-based field-programmable gate arrays with synthesizable very hardware description language coding is introduced. Detailed analyses on the field-programmable gate arrays are given which show that it is suitable for real-time applications. As a result, GA is modified so that it can be implemented in series and parallel which can greatly improve computational hardware performance. Configuration of parallelization is available with a peripheral component interconnect interface, which further helps to form a fast optimization tool for real-time applications. The ultimate goal of this paper is thus to design an effective GA technique which can be employed to support building information modeling and to effectively automate critical processes in construction projects.

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Berezin, N. M., I. E. Chernetskaya, V. S. Panishchev, and A. M. Shabarov. "Development of a device for multiplying numbers by means of FPGA." Journal of Physics: Conference Series 2142, no. 1 (December 1, 2021): 012001. http://dx.doi.org/10.1088/1742-6596/2142/1/012001.

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Abstract The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.

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Zhang, Chunyu, Shouxiang Wang, Ruxun He, Qianyu Zhao, and Kai Wang. "Design and Construction of a Low Cost All-Digital Phase Locked Loop Based on Field Programmable Gate Array." Journal of Physics: Conference Series 1972, no. 1 (July 1, 2021): 012054. http://dx.doi.org/10.1088/1742-6596/1972/1/012054.

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Domínguez Conde, Cristina, Jonas Philipp Lüke, and Fernando Rosa González. "Implementation of a Depth from Light Field Algorithm on FPGA." Sensors 19, no. 16 (August 15, 2019): 3562. http://dx.doi.org/10.3390/s19163562.

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A light field is a four-dimensional function that grabs the intensity of light rays traversing an empty space at each point. The light field can be captured using devices designed specifically for this purpose and it allows one to extract depth information about the scene. Most light-field algorithms require a huge amount of processing power. Fortunately, in recent years, parallel hardware has evolved and enables such volumes of data to be processed. Field programmable gate arrays are one such option. In this paper, we propose two hardware designs that share a common construction block to compute a disparity map from light-field data. The first design employs serial data input into the hardware, while the second employs view parallel input. These designs focus on performing calculations during data read-in and producing results only a few clock cycles after read-in. Several experiments were conducted. First, the influence of using fixed-point arithmetic on accuracy was tested using synthetic light-field data. Also tests on actual light field data were performed. The performance was compared to that of a CPU, as well as an embedded processor. Our designs showed similar performance to the former and outperformed the latter. For further comparison, we also discuss the performance difference between our designs and other designs described in the literature.

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Wiśniewski, Remigiusz, Marcin Wojnakowski, and Zhiwu Li. "Design and Verification of Petri-Net-Based Cyber-Physical Systems Oriented toward Implementation in Field-Programmable Gate Arrays—A Case Study Example." Energies 16, no. 1 (December 21, 2022): 67. http://dx.doi.org/10.3390/en16010067.

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This paper presents a novel design approach of a Petri-net-based cyber-physical system (CPS). The idea is oriented toward implementation in a field-programmable gate array (FPGA). The proposed technique permits error detection in the system at the early specification stage in order to reduce the time and prototyping cost of the CPS. Due to the state explosion problem, the traditional verification methods have exponential computational complexity. In contrast, we show that under certain assumptions, the proposed algorithm is able to detect possible errors in the system even in cubic O(|T|2|P|) time. Furthermore, all the required steps of the proposed design method are presented and discussed. The idea is illustrated by a real-life case study example of a traffic light crossroad. The system was modelled, analysed, implemented, and finally validated within the FPGA device (Virtex-5 family).

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Jessa, Mieczysław, and Łukasz Matuszewski. "Producing Random Bits with Delay-Line-Based Ring Oscillators." International Journal of Electronics and Telecommunications 59, no. 1 (March 1, 2013): 41–50. http://dx.doi.org/10.2478/eletel-2013-0005.

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Abstract One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element.

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Pfänder, O. A., H. J. Pfleiderer, and S. W. Lachowicz. "Configurable multiplier modules for an adaptive computing system." Advances in Radio Science 4 (September 6, 2006): 231–36. http://dx.doi.org/10.5194/ars-4-231-2006.

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Abstract. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However, optimized arithmetic blocks in course-grain reconfigurable arrays as well as field-programmable architectures still play an important role. In countless digital systems and signal processing applications, the multiplication is one of the critical challenges, where in many cases a trade-off between area usage and data throughput has to be made. But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation. In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated processing. The 3-D-SoftChip architecture uses a novel approach to 3-dimensional integration based on flip-chip bonding with indium bumps. The modular construction, the introduction of interfaces to realize the exchange of intermediate data, and the reconfigurable sign handling approach will be explained, as well as a beneficial way to handle and distribute the numerous required control signals.

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Fang, Qizhi, Yuxuan Liu, and Lili Zhang. "Design and Implementation of a Lossless Compression System for Hyperspectral Images." Traitement du Signal 37, no. 5 (November 25, 2020): 745–52. http://dx.doi.org/10.18280/ts.370506.

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Despite its popularity, the hyperspectral image compression algorithm recommended by the Consultative Committee for Space Data Systems (CCSDS) faces a long delay of the feedback loop and complex computations in the modes of band sequential (BSQ) and band interleaved by line (BIL). After analyzing the features of the CCSDS algorithm, this paper proposes a forward prediction method based on the xc7k325tffg9000 field programmable gate array (FPGA) chip (Xilinx Inc.), and adjusts the calculation flow of the CCSDS algorithm, aiming to shorten the time delay in the feedback loop. In addition, full-pipeline construction was implemented on FPGA board to realize real-time processing of data, and dynamic configuration of image parameters. Through functional simulation and off-board test, it is learned that, for the speed-insensitive path, the optimized algorithm can realize the complex operations of the original algorithm with less hardware resources; for hyperspectral image data with an effective input bit width of 12bit, the proposed method can reach a maximum operating frequency of 103MHz, and the data throughput of 103M samples per second (1.237Gbps).

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Mahmood, Zainab H., and Mahmood K. Ibrahem. "HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV." Iraqi Journal of Information & Communications Technology 2, no. 2 (November 1, 2019): 44–57. http://dx.doi.org/10.31987/ijict.2.2.69.

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In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

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Song, Yuefeng, Yongxin Zhu, Tianhao Nan, Junjie Hou, Sen Du, and Shijin Song. "Accelerating Faceting Wide-Field Imaging Algorithm with FPGA for SKA Radio Telescope as a Vast Sensor Array." Sensors 20, no. 15 (July 22, 2020): 4070. http://dx.doi.org/10.3390/s20154070.

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The SKA (Square Kilometer Array) radio telescope will become the most sensitive telescope by correlating a huge number of antenna nodes to form a vast array of sensors in a region over one hundred kilometers. Faceting, the wide-field imaging algorithm, is a novel approach towards solving image construction from sensing data where earth surface curves cannot be ignored. However, the traditional processor of cloud computing, even if the most sophisticated supercomputer is used, cannot meet the extremely high computation performance requirement. In this paper, we propose the design and implementation of high-efficiency FPGA (Field Programmable Gate Array) -based hardware acceleration of the key algorithm, faceting in SKA by focusing on phase rotation and gridding, which are the most time-consuming phases in the faceting algorithm. Through the analysis of algorithm behavior and bottleneck, we design and optimize the memory architecture and computing logic of the FPGA-based accelerator. The simulation and tests on FPGA are done to confirm the acceleration result of our design and it is shown that the acceleration performance we achieved on phase rotation is 20× the result of the previous work. We then further designed and optimized an efficient microstructure of loop unrolling and pipeline for the gridding accelerator, and the designed system simulation was done to confirm the performance of our structure. The result shows that the acceleration ratio is 5.48 compared to the result tested on software in gridding parts. Hence, our approach enables efficient acceleration of the faceting algorithm on FPGAs with high performance to meet the computational constraints of SKA as a representative vast sensor array.

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Dimopoulos, Alexandros C., Christos Pavlatos, and George Papakonstantinou. "Hardware Inexact Grammar Parser." International Journal of Pattern Recognition and Artificial Intelligence 31, no. 11 (April 11, 2017): 1759025. http://dx.doi.org/10.1142/s021800141759025x.

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In this paper, a platform is presented, that given a Stochastic Context-Free Grammar (SCFG), automatically outputs the description of a parser in synthesizable Hardware Description Language (HDL) which can be downloaded in an FPGA (Field Programmable Gate Arrays) board. Although the proposed methodology can be used for various inexact models, the probabilistic model is analyzed in detail and the extension to other inexact schemes is described. Context-Free Grammars (CFG) are augmented with attributes which represent the probability values. Initially, a methodology is proposed based on the fact that the probabilities can be evaluated concurrently with the parsing during the parse table construction by extending the fundamental parsing operation proposed by Chiang & Fu. Using this extended operation, an efficient architecture is presented based on Earley’s parallel algorithm, which given an input string, generates the parse table while evaluating concurrently the probabilities of the generated dotted grammar rules in the table. Based on this architecture, a platform has been implemented that automatically generates the hardware design of the parser given a SCFG. The platform is suitable for embedded systems applications where a natural language interface is required or in pattern recognition tasks. The proposed hardware platform has been tested for various SCFGs and was compared with previously presented hardware parser for SCFGs based on Earley’s parallel algorithm. The hardware generated by the proposed platform is much less complicated than the one of comparison and succeeds a speed-up of one order of magnitude.

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Zhang, Zhun, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu, and Jinhui Ma. "High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems." Micromachines 12, no. 5 (May 15, 2021): 560. http://dx.doi.org/10.3390/mi12050560.

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Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

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Bhatia, Dinesh. "Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (January 1, 1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

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Bazydło, Grzegorz. "Designing Reconfigurable Cyber-Physical Systems Using Unified Modeling Language." Energies 16, no. 3 (January 25, 2023): 1273. http://dx.doi.org/10.3390/en16031273.

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Technological progress in recent years in the Cyber-Physical Systems (CPSs) area has given designers unprecedented possibilities and computational power, but as a consequence, the modeled CPSs are becoming increasingly complex, hierarchical, and concurrent. Therefore, new methods of CPSs design (especially using abstract modeling) are needed. The paper presents an approach to the CPS control part modeling using state machine diagrams from Unified Modelling Language (UML). The proposed design method attempts to combine the advantages of graphical notation (intuitiveness, convenience, readability) with the benefits of text specification languages (unambiguity, precision, versatility). The UML specification is transformed using Model-Driven Development (MDD) techniques into an effective program in Hardware Description Language (HDL), using Concurrent Finite State Machine (CFSM) as a temporary model. The obtained HDL specification can be analyzed, validated, synthesized, and finally implemented in Field Programmable Gate Array (FPGA) devices. The dynamic, partial reconfiguration (a feature of modern FPGAs) allows for the exchange of a part of the implemented CPS algorithm without stopping the device. But to use this feature, the model must be safe, which in the proposed approach means, that it should possess special idle states, where the control is transferred during the reconfiguration process. Applying the CFSM model greatly facilitates this task. The proposed design method offers efficient graphical modeling of a control part of CPS, and automatic translation of the behavior model into a synthesizable Verilog description, which can be directly implemented in FPGA devices, and dynamically reconfigured as needed. A practical example illustrating the successive stages of the proposed method is also presented.

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Jung, Peter, and Josef Blanz. "Design of a viterbi equalizer with field programmable gate arrays." Microelectronics Journal 24, no. 7 (November 1993): 787–800. http://dx.doi.org/10.1016/0026-2692(93)90023-8.

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Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam, and Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays." International Journal of Handheld Computing Research 7, no. 4 (October 2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation. While the proposed camera is far from being able to compete with commercial offerings, it can serve as a framework to test new research ideas related to digital camera systems, image processing, computer vision, etc., as well as an educational platform for advanced digital design with VHDL and FPGAs. As examples of that, we report two spin-off projects developed on top of or starting from the presented digital camera system.

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Conti, Vincenzo, Carmelo Militello, Filippo Sorbello, and Salvatore Vitabile. "Biometric sensors rapid prototyping on field-programmable gate arrays." Knowledge Engineering Review 30, no. 2 (March 2015): 201–19. http://dx.doi.org/10.1017/s0269888914000307.

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AbstractBiometric user authentication in large-scale distributed systems involves passive scanners and networked workstations and databases for user data acquisition, processing, and encryption. Unfortunately, traditional biometric authentication systems are prone to several attacks, such as Replay Attacks, Communication Attacks, and Database Attacks. Embedded biometric sensors overcome security limits of conventional software recognition systems, hiding its common attack points. The availability of mature reconfigurable hardware technology, such as field-programmable gate arrays, allows the developers to design and prototype the whole embedded biometric sensors. In this work, two strong and invasive biometric traits, such as fingerprint and iris, have been considered, analyzed, and combined in unimodal and multimodal biometric sensors. Biometric sensor performance has been evaluated using the well-known FVC2002, CASIA, and BATH databases.

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Lee, Edmund, Guy Lemieux, and Shahriar Mirabbasi. "Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays." Journal of Signal Processing Systems 51, no. 1 (October 4, 2007): 57–76. http://dx.doi.org/10.1007/s11265-007-0141-y.

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Mirchandani, Chandru. "4.1.3 Selection Process for System Design Using Field Programmable Gate Arrays." INCOSE International Symposium 12, no. 1 (August 2002): 129–36. http://dx.doi.org/10.1002/j.2334-5837.2002.tb02451.x.

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Fei Li, Y. Lin, Lei He, Deming Chen, and J. Cong. "Power modeling and characteristics of field programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 11 (November 2005): 1712–24. http://dx.doi.org/10.1109/tcad.2005.852293.

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Teng, Bill, and J. H. Anderson. "Latch-Based Performance Optimization for Field-Programmable Gate Arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 5 (May 2013): 667–80. http://dx.doi.org/10.1109/tcad.2012.2235913.

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Guillemenet, Y., L. Torres, G. Sassatelli, and N. Bruchon. "On the Use of Magnetic RAMs in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–9. http://dx.doi.org/10.1155/2008/723950.

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This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

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Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

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A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acquisition system has characteristics of stable performance, flexible expansion, high real-timeness and integration

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Guerrero-Rivera, Ruben, Abigail Morrison, Markus Diesmann, and Tim C. Pearce. "Programmable Logic Construction Kits for Hyper-Real-Time Neuronal Modeling." Neural Computation 18, no. 11 (November 2006): 2651–79. http://dx.doi.org/10.1162/neco.2006.18.11.2651.

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Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

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Majumdar, Jharna, Darshan K M, and Abhijith Vijayendra. "Design and Implementation of Video Shot Detection on Field Programmable Gate Arrays." IAES International Journal of Robotics and Automation (IJRA) 2, no. 1 (March 1, 2013): 17. http://dx.doi.org/10.11591/ijra.v2i1.pp17-25.

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Video has become an interactive medium of communication in everyday life. The sheer volume of video makes it extremely difficult to browse through and find the required data. Hence extraction of key frames from the video which represents the abstract of the entire video becomes necessary. The aim of the video shot detection is to find the position of the shot boundaries, so that key frames can be selected from each shot for subsequent processing such as video summarization, indexing etc. For most of the surveillance applications like video summery, face recognition etc., the hardware (real time) implementation of these algorithms becomes necessary. Here in this paper we present the architecture for simultaneous accessing of consecutive frames, which are then used for the implementation of various Video Shot Detection algorithms. We also present the real time implementation of three video shot detection algorithms using the above mentioned architecture on FPGA (Field Programmable Gate Arrays).

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Taha, T. B., R. Ngadiran, and P. L. Ehkan. "Design and Implementation of Lifting Wavelet Transform Using Field Programmable Gate Arrays." IOP Conference Series: Materials Science and Engineering 767 (March 21, 2020): 012041. http://dx.doi.org/10.1088/1757-899x/767/1/012041.

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Homulle, Harald, Stefan Visser, Bishnu Patra, and Edoardo Charbon. "Design techniques for a stable operation of cryogenic field-programmable gate arrays." Review of Scientific Instruments 89, no. 1 (January 2018): 014703. http://dx.doi.org/10.1063/1.5004484.

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Neelima, S., and R. Brindha. "512 bit-SHA3 design approach and implementation on field programmable gate arrays." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (November 1, 2019): 169. http://dx.doi.org/10.11591/ijres.v8.i3.pp169-174.

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<p>In this work, the authors consider the newly selected Hash Secure (SHA-3) algorithm on FPGA Gateway. The design is logically optimized for zone efficiency by combining the Rho steps and the one-pass algorithm. Logically recording these three steps registers leads to usage 16% of the logical resources for all implementations. This in turn reduces the latency and increases the maximum operating frequency of the project. It uses only 240 sections and has a frequency of 301.02 MHz compared to the design results with the previous FPGA implementation described in SHA3-512, the design shows the Throughput-Per-Slice (TPS) ratio of 30, 1.</p>

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Bhatia, Dinesh, and Amit Chowdhary. "A Multi-Terminal Net Router for Field-Programmable Gate Arrays." VLSI Design 4, no. 1 (January 1, 1996): 1–10. http://dx.doi.org/10.1155/1996/79127.

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This paper presents a router for routing multi-terminal nets in field-programmable gate arrays (FPGAs). The router does not require pre-assignment of routing channels, a phase that is normally accomplished during global routing. This direct routing approach greatly enhances the probability of routing (routability). The multi-terminal routing greatly reduces the total wire length as it approximates a Steiner tree. The total number of segments required to route the circuits is usually less as compared to other routing approaches. The router has generated excellent routing results for some industrial circuits. The memory requirements for this router are very low. The time needed for the routing is linear with respect to the size of the circuit.

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Saleh, Shukur Bin, Sulaiman Bin Mazlan, Nik Iskandar Bin Hamzah, Ahmad Zahid Zakwan Bin Abdul Karim, Mohd Shamian Bin Zainal, Shipun Anuar Bin Hamzah, Danial Bin Md Nor, and Hazwaj Bin Mhd Poad. "Smart Home Security Access System Using Field Programmable Gate Arrays." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (July 1, 2018): 152. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp152-160.

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Nowadays, the rapid growth of burglary and theft cases over the world has been threatening to the vulnerability of traditional home security systems. Therefore the development home security with intelligent control wherein focus to enhance conventional technique to theadvanced digital security systemand to be more interestinginhome or building owner for preventing intruders in smart home implementation. However, using avariety of type conventional lock doors for security purposes and analog intruder sensor with individual function system is not secure enoughin order to protect the person or company properties. That why the emergence of new technology such as integrated circuit network will apply in Smart Home system for abetter security solution to prevent the houses from theintruder and hazardous fire incident. Therefore, this project is done to design and build a smart system with consist of digital security entry for automatic lock doors and also for activating or deactivate all security sensor in houses which is function for detecting the irregular movement and hot temperature (fire incident) in-house for the domestic residential sector. This product includeswith doors automatic lock system using servo motor and detect irregular movement intruder using PIR motion sensor (HC-SR501) and also measure hot temperature using temperature sensor (LM35). The sensor will transmit theanalog signal to Field Programmable Gate Array (FPGA) the Altera DE2-115 board to be processed and which will then display the status entry after key-in password and activation security system on the LED seven segment displays. The entry login controller will use apush button or switchesavailable on FPGA board that are used to login password for automatic door accessand also able maintained for control home smart security system.

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VENKATESWARAN, N., S. PATTABIRAMAN, J. DESOUZA, G. SRIRAM, R. SRINIVASAN, R. SANKAR, and G. SURESH. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (April 1995): 263–301. http://dx.doi.org/10.1142/s0218001495000134.

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The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable Pacube (PA3—Programmable Array of Array Adders) VLSI array is proposed in this paper. These arrays can be mask programmed for building cost-effective super computing VLSI functional units. Another important feature is the architecture of the macro-cell, which is designed in such a way that the functional units corresponding to the G-set equations when mapped on the macro-cell arrays possess identical data flow control. This leads to a highly simplified control design for executing complex computations.

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Ditmar, Johan, Steve McKeever, and Alex Wilson. "Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation." International Journal of Reconfigurable Computing 2008 (2008): 1–14. http://dx.doi.org/10.1155/2008/674340.

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This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.

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Rais. "Field Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's Multipliers." Journal of Computer Science 7, no. 12 (December 1, 2011): 1894–99. http://dx.doi.org/10.3844/jcssp.2011.1894.1899.

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Simpkins, Alex. "Introduction to Embedded System Design Using Field Programmable Gate Arrays [On the Shelf]." IEEE Robotics & Automation Magazine 20, no. 4 (December 2013): 163–64. http://dx.doi.org/10.1109/mra.2013.2283188.

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Tufa, Guta Tesema, Fitsum Assamnew Andargie, and Anchit Bijalwan. "Acceleration of Deep Neural Network Training Using Field Programmable Gate Arrays." Computational Intelligence and Neuroscience 2022 (October 17, 2022): 1–11. http://dx.doi.org/10.1155/2022/8387364.

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Convolutional neural network (CNN) training often necessitates a considerable amount of computational resources. In recent years, several studies have proposed for CNN inference and training accelerators in which the FPGAs have previously demonstrated good performance and energy efficiency. To speed up the processing, CNN requires additional computational resources such as memory bandwidth, a FPGA platform resource usage, time, power consumption, and large datasets for training. They are constrained by the requirement for improved hardware acceleration to support scalability beyond existing data and model sizes. This paper proposes a procedure for energy efficient CNN training in collaboration with an FPGA-based accelerator. We employed optimizations such as quantization, which is a common model compression technique, to speed up the CNN training process. Additionally, a gradient accumulation buffer is used to ensure maximum operating efficiency while maintaining gradient descent of the learning algorithm. To validate the design, we implemented the AlexNet and VGG-16 models on an FPGA board and laptop CPU along side GPU. It achieves 203.75 GOPS on Terasic DE1 SoC with the AlexNet model and 196.50 GOPS with the VGG-16 model on Terasic DE-SoC. Our result also exhibits that the FPGA accelerators are more energy efficient than other platforms.

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Wiśniewski, Remigiusz, Alexander Barkalov, Larisa Titarenko, and Wolfgang Halang. "Design of microprogrammed controllers to be implemented in FPGAs." International Journal of Applied Mathematics and Computer Science 21, no. 2 (June 1, 2011): 401–12. http://dx.doi.org/10.2478/v10006-011-0030-1.

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Design of microprogrammed controllers to be implemented in FPGAs In the article we propose a new design method for microprogrammed controllers. The traditional structure is improved by modifying internal modules and connections. Such a solution allows reducing the total number of logic elements needed for implementation in programmable structures, especially Field Programmable Gate Arrays (FPGAs). Detailed results of experiments show that on the average the application of the proposed methods yields up to 30% savings as far as the destination device is considered.

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John, Lizy Kurian. "Memory Chips with Adjustable Configurations." VLSI Design 10, no. 2 (January 1, 1999): 203–15. http://dx.doi.org/10.1155/1999/62801.

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In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax⁡ can be constructed with the extra cost of Wmax⁡ – 1 pass gates, (Wmax⁡/2) 2-to-1 multiplexers, and ⌈log⁡2[log⁡2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.

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Bartnykas, Kęstutis. "PROJECT DESIGN FOR COMPUTER ARCHITECTURE PRACTICAL SESSIONS BASED ON FIELD-PROGRAMMABLE GATE ARRAY." Mokslas - Lietuvos ateitis 13 (September 2, 2021): 1–5. http://dx.doi.org/10.3846/mla.2021.15184.

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Field-programmable logic arrays are often used in courses on computer architecture. The student must describe the processor with the external components necessary for its operation in the specified HDL (hardware description language) language according to the provided specification during a certain number of projects. The weakness of this approach is that the basis of such projects is a processor of one specific architecture, so the lecturer faces the issue of individualization of projects. This article proposes a solution based on dedicated processors instead of one programmable processor of a specific architecture. It’s shown here that the issue of project individualization is easier solvable in the proposed way, and it does not deviate from the theory of computer architecture, because the programmable processor is a generalization of a dedicated processor. The article describes project design ideas based on dedicated processors and gives some examples. Represented different instance than was applied during practical sessions of Computer Architecture that are held at the Department of Electronic Systems within VILNIUS TECH, i.e. certain modifications, and additions were applied.

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Zhang, Yunxiang, Xiaokun Yang, Lei Wu, Archit Gajjar, and Han He. "Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System." International Journal of Computer Applications 180, no. 17 (February 15, 2018): 1–7. http://dx.doi.org/10.5120/ijca2018916380.

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McNelles, Phillip, and Lixuan Lu. "ICONE23-1171 DESIGN OF A TRITIUM-IN-AIR-MONITOR USING FIELD PROGRAMMABLE GATE ARRAYS." Proceedings of the International Conference on Nuclear Engineering (ICONE) 2015.23 (2015): _ICONE23–1—_ICONE23–1. http://dx.doi.org/10.1299/jsmeicone.2015.23._icone23-1_93.

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Kelly, Jamie S., Vittal S. Rao, Hardy J. Pottinger, and H. Clifford Bowman. "Design and implementation of digital controllers for smart structures using field programmable gate arrays." Smart Materials and Structures 6, no. 5 (October 1, 1997): 559–72. http://dx.doi.org/10.1088/0964-1726/6/5/007.

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Tajary, Alireza, and Behnam Ghavami. "A Metallic CNT Tolerant Design Methodology for Carbon Nanotube-Based Programmable Gate Arrays." Journal of Circuits, Systems and Computers 25, no. 02 (December 23, 2015): 1650016. http://dx.doi.org/10.1142/s021812661650016x.

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Carbon nanotube field effect transistor (CNFET) is one of the promising technologies as a replacement for current CMOS technology due to its excellent electronic properties. CNFETs can be fabricated in regular structures, making them ideal for creating the repetitive architectures found in field programmable gate arrays (FPGAs). However, CNFETs face some fabrication challenges. The unwanted metallic carbon nanotubes (CNTs) are one of the major challenges in using CNFET technology for FPGAs. In this paper, we take the advantage of FPGAs programmability allowing reconfiguration around the metallic CNTs to tolerate this defect. We demonstrate a multi-stage solution to the metallic CNT problem in CNFET-based FPGAs that does not require any metallic nanotube removal of any kind. The proposed methodology consists of four consecutive stages in logic mapping process: (i) reordering of input variables, (ii) inputs complementing, (iii) adding inputs redundancy to basic logic element (BLE) and (iv) BLE lookup table (LUT) splitting. A fault simulation tool is designed to work closely with VPR, an academic FPGA CAD tool, to provide the investigation of metallic CNTs effects on CNFET-based FPGAs. Experimental results show that the proposed method can successfully map all logical nets at a cost of [Formula: see text] area overhead if the fraction of metallic CNTs is reduced to 30%.

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Brown, Stephen, Muhammad Khellah, and Guy Lemieux. "Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (January 1, 1996): 275–91. http://dx.doi.org/10.1155/1996/45983.

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This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the effective utilization of available interconnect resources in an FPGA, and the speed-performance of implemented circuits. The major contributions of this research include the following: 1) we illustrate the effect of a global router on both area-utilization and speed-performance of implemented circuits, 2) experiments quantify the impact of the detailed router cost functions on area-utilization and speed-performance, 3) we show the effect on circuit implementation of dividing multi-point nets in a circuit being routed into point-to-point connections, and 4) the paper illustrates that CAD routing tools should account for both routability and speed-performance at the same time, not just focus on one goal.

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Allani, Mohamed Yassine, Jamel Riahi, Silvano Vergura, and Abdelkader Mami. "FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load." Energies 14, no. 8 (April 9, 2021): 2108. http://dx.doi.org/10.3390/en14082108.

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The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the system performance. The inverter and the LCL filter allow for the integration of this hybrid system with AC loads and the grid. Moreover, a hardware solution for the field programmable gate arrays-based implementation of the controllers is proposed. The combination of these controllers was synthesized using the Integrated Synthesis Environment Design Suite software (Version: 14.7, City: Tunis, Country: Tunisia) and was successfully implemented on Field Programmable Gate Arrays Spartan 3E. The innovative design provides a suitable architecture based on power converters and control strategies that are dedicated to the proposed hybrid system to ensure system reliability. This implementation can provide a high level of flexibility that can facilitate the upgrade of a control system by simply updating or modifying the proposed algorithm running on the field programmable gate arrays board. The simulation results, using Matlab/Simulink (Version: 2016b, City: Tunis, Country: Tunisia, verify the efficiency of the proposed solution when the environmental conditions change. This study focused on the development and optimization of an electrical system control strategy to manage the produced energy and to coordinate the performance of the hybrid energy system. The paper proposes a combined photovoltaic and wind energy system, supported by a battery acting as an energy storage system. In addition, a bi-directional converter charges/discharges the battery, while a high-voltage gain converter connects them to the DC bus. The use of a battery is useful to compensate for the mismatch between the power demanded by the load and the power generated by the hybrid energy systems. The proposed field programmable gate arrays (FPGA)-based controllers ensure a fast time response by making control executable in real time.

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Howard, Neil J., Andrew M. Tyrrell, and Nigel M. Allinson. "The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks." VLSI Design 4, no. 2 (January 1, 1996): 135–39. http://dx.doi.org/10.1155/1996/17505.

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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.

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Liu, Xiang Wen, and Li Min Liu. "The IP Design for a Customized Mobile SoC." Advanced Materials Research 605-607 (December 2012): 2087–90. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.2087.

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IP, Intellectual Property, modules are essential and important for SoC applications. SoC, System on a Chip, is a system integrated on a single semiconductor chip. It is a research hot-point in embedded systems. In this paper, the IP design for a customized mobile SoC is discussed. The customized mobile SoC integrates a mobile computing control or monitor system into one chip FPGA, Field Programmable Gate Arrays. The SoC is required smaller in size and more efficient in operation.

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Wang, Jian, Houqin Wang, Yuemei Luo, Hongying Tang, Hongwei Mao, and Shubo Bi. "Psychological stress recognition from heart rate variability parameters based on field programmable gate arrays." Review of Scientific Instruments 93, no. 11 (November 1, 2022): 115107. http://dx.doi.org/10.1063/5.0118630.

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Psychological stress is a big threat to people’s health. Early detection of psychological stress is important. The design of a stress recognition device based on the ECG (electrocardiograph) signal is presented in this paper. The device features intelligence, precision, portability, fast response, and low power consumption. In the design, the ECG signals are acquired by the AD8232 ECG module and processed by a low power consumption FPGA (Field Programmable Gated Array) development board PYNQ-Z2. Meanwhile, a modified Deep Forest model named Aw-Deep Forest (Adaptive Weight Deep Forest) is proposed. The Aw-Deep Forest has better performance than the Deep Forest model because it improves the fitting quality of the forests. By implementing the Aw-Deep Forest model on the FPGA, the device can assess people’s state of psychological stress by analyzing the HRV (heart rate variability) parameters from ECG data. This paper mainly introduces the detailed process of ECG signal collecting, filtering, analog signal to digital signal conversion, HRV parameter analysis, and psychological stress recognition with Aw-Deep Forest. The final accuracy is 81.39%.

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Gaillardon, Pierre-Emmanuel, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, and Giovanni De Micheli. "Nanowire systems: technology and design." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130102. http://dx.doi.org/10.1098/rsta.2013.0102.

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Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology.

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Rassal Raj, Nisha Rexline, Ebenezer Priya, and George Fernandez Savari. "Design and implementation of portable electrocardiogram recorder with field programmable gate arrays and IoT interface." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (October 1, 2022): 5176. http://dx.doi.org/10.11591/ijece.v12i5.pp5176-5181.

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The electrical activities of the heart are used to monitor cardiovascular diseases. It can be measured using electrocardiogram (ECG), a simple, painless test that can be recorded graphically. The physician, to predict the patient’s heart conditions and recommend suitable treatments, uses electrodes placed on the patient’s skin surface, to record these signals. The P, Q, R, S, T waves in the ECG signal can be used to determine the normality and abnormality of the heart's condition. The time interval differs for each cardiovascular condition of the heart. In this work, the ECG signal is acquired real-time using an intelligent sensor module, and the recorded value is processed to find the peak values. The data is sent to the web serverusing internet of things technology at a minimal time, where the physician can view it and proper decision can be taken. The real-time ECG data acquisition is also made using the field programmable gate array kit as it is a low cost, high-speed device and the output is viewed in the computer. The developed model is validated through MATLAB software and implemented for real-time applications.

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Lamoureux, Julien, and Steven J. E. Wilton. "On the Interaction Between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays." Journal of Low Power Electronics 1, no. 2 (August 1, 2005): 119–32. http://dx.doi.org/10.1166/jolpe.2005.023.

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Journal articles on the topic 'Field programmable gate arrays – Design and construction'

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