Relevant bibliographies by topics / Field Programmable Gate Arrays (FPGA)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Field Programmable Gate Arrays (FPGA)'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Field Programmable Gate Arrays (FPGA)"

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Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam, and Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays." International Journal of Handheld Computing Research 7, no. 4 (October 2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation. While the proposed camera is far from being able to compete with commercial offerings, it can serve as a framework to test new research ideas related to digital camera systems, image processing, computer vision, etc., as well as an educational platform for advanced digital design with VHDL and FPGAs. As examples of that, we report two spin-off projects developed on top of or starting from the presented digital camera system.
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Tufa, Guta Tesema, Fitsum Assamnew Andargie, and Anchit Bijalwan. "Acceleration of Deep Neural Network Training Using Field Programmable Gate Arrays." Computational Intelligence and Neuroscience 2022 (October 17, 2022): 1–11. http://dx.doi.org/10.1155/2022/8387364.

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Convolutional neural network (CNN) training often necessitates a considerable amount of computational resources. In recent years, several studies have proposed for CNN inference and training accelerators in which the FPGAs have previously demonstrated good performance and energy efficiency. To speed up the processing, CNN requires additional computational resources such as memory bandwidth, a FPGA platform resource usage, time, power consumption, and large datasets for training. They are constrained by the requirement for improved hardware acceleration to support scalability beyond existing data and model sizes. This paper proposes a procedure for energy efficient CNN training in collaboration with an FPGA-based accelerator. We employed optimizations such as quantization, which is a common model compression technique, to speed up the CNN training process. Additionally, a gradient accumulation buffer is used to ensure maximum operating efficiency while maintaining gradient descent of the learning algorithm. To validate the design, we implemented the AlexNet and VGG-16 models on an FPGA board and laptop CPU along side GPU. It achieves 203.75 GOPS on Terasic DE1 SoC with the AlexNet model and 196.50 GOPS with the VGG-16 model on Terasic DE-SoC. Our result also exhibits that the FPGA accelerators are more energy efficient than other platforms.
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Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

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A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acquisition system has characteristics of stable performance, flexible expansion, high real-timeness and integration
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Chen, Yonghao, Tianrui Li, Xiaojie Chen, ZhiGang Cai, and Tao Su. "High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays." Electronics 12, no. 4 (February 6, 2023): 822. http://dx.doi.org/10.3390/electronics12040822.

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The systolic array is frequently used in accelerators for neural networks, including Transformer models that have recently achieved remarkable progress in natural language processing (NLP) and machine translation. Due to the constraints of FPGA EDA (Field Programmable Gate Array Electronic Design Automation) tools and the limitations of design methodology, existing systolic array accelerators for FPGA deployment often cannot achieve high frequency. In this work, we propose a well-designed high-frequency systolic array for an FPGA-based Transformer accelerator, which is capable of performing the Multi-Head Attention (MHA) block and the position-wise Feed-Forward Network (FFN) block, reaching 588 MHz and 474 MHz for different array size, achieving a frequency improvement of 1.8× and 1.5× on a Xilinx ZCU102 board, while drastically saving resources compared to similar recent works and pushing the utilization of each DSP slice to a higher level. We also propose a semi-automatic design flow with constraint-generating tools as a general solution for FPGA-based high-frequency systolic array deployment.
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Guillemenet, Y., L. Torres, G. Sassatelli, and N. Bruchon. "On the Use of Magnetic RAMs in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–9. http://dx.doi.org/10.1155/2008/723950.

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This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.
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Brown, Stephen, Muhammad Khellah, and Guy Lemieux. "Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (January 1, 1996): 275–91. http://dx.doi.org/10.1155/1996/45983.

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This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the effective utilization of available interconnect resources in an FPGA, and the speed-performance of implemented circuits. The major contributions of this research include the following: 1) we illustrate the effect of a global router on both area-utilization and speed-performance of implemented circuits, 2) experiments quantify the impact of the detailed router cost functions on area-utilization and speed-performance, 3) we show the effect on circuit implementation of dividing multi-point nets in a circuit being routed into point-to-point connections, and 4) the paper illustrates that CAD routing tools should account for both routability and speed-performance at the same time, not just focus on one goal.
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Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, and Rahul Khanna. "Field Programmable Gate Array Applications—A Scientometric Review." Computation 7, no. 4 (November 11, 2019): 63. http://dx.doi.org/10.3390/computation7040063.

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.
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Amer Abbas, Yasir, Razali Jidin, Norziana Jamil, Muhammad Reza Z\'aba, and Mohd Ezanee Rusli. "PRINCE IP-core on Field Programmable Gate Arrays (FPGA)." Research Journal of Applied Sciences, Engineering and Technology 10, no. 8 (July 20, 2015): 914–22. http://dx.doi.org/10.19026/rjaset.10.2447.

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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.
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Das, N., P. Roy, and H. Rahaman. "Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)." Journal of The Institution of Engineers (India): Series B 96, no. 3 (July 15, 2014): 227–36. http://dx.doi.org/10.1007/s40031-014-0141-9.

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Dissertations / Theses on the topic "Field Programmable Gate Arrays (FPGA)"

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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Hauck, Scott. "Multi-FPGA systems /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/7008.

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Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configuration data. For a wide set of benchmark circuits on various FPGAs, it is shown that the proposed methods outperform all previous configuration compression methods and, depending upon the relative size of the circuit to the device, compress within 5\% of the fundamental information theoretic limit. Moreover, it is shown that the corresponding decoders are simple to implement in hardware and scale well with device size and available configuration bandwidth. It is not unreasonable to expect that with little modification to existing FPGA configuration memory systems and acceptable increase in configuration power a 10-fold improvement in configuration delay could be achieved. The main contribution of this thesis is that it defines the limit of configuration compression for the FPGAs under consideration and develops practical methods of overcoming this reconfiguration bottleneck. The functional density of reconfigurable devices could thereby be enhanced and the range of potential applications reasonably expanded.
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Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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James, Calvin L. "COMPLEX WAVEFORM GENERATION UTILIZING FIELD PROGRAMMABLE GATE ARRAYS." International Foundation for Telemetering, 1997. http://hdl.handle.net/10150/609692.

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International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada
The basic building blocks for implementing complex waveform generators using a look-up table approach are random access memory (RAM) and read only memory (ROM) devices. Due to technological advancements in field programmable gate array (FPGA) development, these devices have the ability to allocate large amounts of memory elements within the same structure. The self containment property makes the FPGA a suitable topology for complex waveform generation applications. In addition, this self containment property significantly reduces implementation costs by reducing the number of external components required to support many applications. This paper examines the use of FPGA’s in various complex waveform generation applications. In particular, a discussion will ensue examining possible mappings of the time domain response of the complex waveform into memory elements of the FPGA. The analyses and examples contained in the sequel are from existing waveform generation applications, developed for Gauissian Minimum Shift Keying (GMSK) and Unbalanced Quadriphase Shift Keying (UQPSK) modulation formats.
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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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Lin, Yu Colin, and 林郁. "ArchSyn: an energy-efficient FPGA high-level synthesizer." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49799599.

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Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops a highly energy-efficient FPGA high-level synthesis tool, ArchSyn, using an application-specific coarse-grain architecture as an intermediate synthesis step. ArchSyn provides rapid and energy-efficient compilation of dataflow graphs (DFGs) on FPGAs by scheduling the dataflow operations on an array of directly connected simple configurable processing elements (CPEs). Each CPE in the array performs primitive compute operations according to a small local sequencer at each cycle. Data are communicated via multi-hop routing within the direct interconnect network. The scheduler schedules each compute operation of the DFG obtained from the high-level design to execute on a particular hardware CPE at a particular cycle. It also determines the communication schedule of the intermediate data among the producing and consuming CPEs, optionally buffering them with distributed memory along the path. As such, the lengthy process of synthesizing a full custom hardware design on FPGA is reduced to a scheduling and mapping process. By restricting the fine-grain programmability into a coarse grain processor network scheduling problem, the compilation time can be improved substantially, thereby improving the overall productivity of the designer. Furthermore, taking advantage of the programmability of FPGAs, the effect of the array interconnect architecture on the energy-efficiency of the resulting system is studied. By altering the array configuration, the data communication scheme among the CPEs must also be changed. This has a net effect on both the energy consumption spent on data movement as well as on the overall compute performance. It is shown that by using array topology that is customized to the input DFG, up to 28% improvement in energy-efficiency could be achieved. An exploratory framework based on a genetic algorithm was developed that allows us to obtain such application-specific connection network. Such degree of customization is possible only with the programmability of FPGAs. Moreover, such topology adaptation can be achieved rapidly as only routings between a fixed set of pre-placed CPEs are required. Implementations using ArchSyn and an existing FPGA compilation tool xPilot were compared. ArchSyn gave a 2X better energy consumption and a 11X better energy-delay product for computation with very regular and simple data dependency. For computation with irregular data dependency, the energy consumption and energy-delay product improvement was 9.6X and 199X.
published_or_final_version
Electrical and Electronic Engineering
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Doctor of Philosophy
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Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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Källström, Petter. "Direct Digital Frequency Synthesis in Field-Programmable Gate Arrays." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56550.

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This thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs).

Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use.


Detta exjobb handlar om att skapa ett Matlab-program som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digital frekvenssyntes (DDFS). Ämnad hårdvara för implementeringen är en fältprogrammerbar grindmatris (FPGA).

Fokus i denna rapport ligger på hur en FPGA är uppbyggd, olika metoder för sinusgenerering och vilka kvaliteter på sinusvågen de ger och vilka resurser i hårdvaran de använder.

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Books on the topic "Field Programmable Gate Arrays (FPGA)"

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ACM, International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey Calif ). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, NY: ACM Press, 1999.

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ACM Special Interest Group on Design Automation., ed. FPGA '00: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, N.Y: Association for Computing Machinery, 2000.

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ACM International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey, Calif.). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, NY: Association for Computing Machinery, 1999.

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David E. Van den Bout. FPGA workout: Beginning exercises with the Intel FLEXlogic FPGA. Apex, N.C: X Engineering Software Systems Corp., 1994.

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ACM International Symposium on Field-Programmable Gate Arrays (6th 1998 Monterey, Calif.). FPGA '98: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, NY: Association for Computing Machinery, 1998.

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ACM International Symposium on Field-Programmable Gate Arrays (9th 2001 Monterey, Calif.). FPGA '01: ACM/SIGDA International Symposium on Field Programmable Gate Arrays : Monterey, California, USA. New York, N.Y: Association for Computing Machinery, 2001.

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ACM International Symposium on Field-Programmable Gate Arrays (10th 2002 Monterey, Calif.). FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA : February 24-26, 2002. New York, N.Y: ACM Press, 2002.

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Ukeiley, Richard Larry. Field programmable gate arrays (FPGAs): The 3000 series. Englewood Cliffs, N.J: PTR Prentice Hall, 1993.

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Advanced FPGA design: Architecture, implementation, and optimization. Hoboken, NJ: Wiley-Interscience, 2007.

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ACM Special Interest Group on Design Automation, ed. FPGA '13: Proceedings of the 2013 ACM SIGDA International Symposium on Field Programmable Gate Arrays : February 11-13, 2013, Monterey, California, USA. New York, N.Y: Association for Computing Machinery, 2013.

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Book chapters on the topic "Field Programmable Gate Arrays (FPGA)"

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Flexibility of FPGA Routing Architectures." In Field-Programmable Gate Arrays, 147–67. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_6.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "A Theoretical Model for FPGA Routing." In Field-Programmable Gate Arrays, 169–90. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_7.

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Pandey, Bishwajeet, and Keshav Kumar. "Field programmable gate arrays (FPGA)." In Green Communication with Field-programmable Gate Array for Sustainable Development, 13–32. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003302872-2.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Introduction to FPGAs." In Field-Programmable Gate Arrays, 1–11. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_1.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Commercially Available FPGAs." In Field-Programmable Gate Arrays, 13–43. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_2.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Routing for FPGAs." In Field-Programmable Gate Arrays, 117–45. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_5.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Technology Mapping for FPGAs." In Field-Programmable Gate Arrays, 45–86. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_3.

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Bindal, Ahmet, and Sotoudeh Hamedi-Hagh. "Field-Programmable-Gate-Array (FPGA)." In Silicon Nanowire Transistors, 121–33. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-27177-4_7.

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Hajji, Bekkay, Adel Mellit, and Loubna Bouselham. "Introduction to Field Programmable Gate Arrays (FPGA)." In A Practical Guide for Simulation and FPGA Implementation of Digital Design, 3–18. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0615-2_1.

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Garcia, Andrés, Wayne Burleson, and Jean-Luc Danger. "Power Modelling in Field Programmable Gate Arrays (FPGA)." In Field Programmable Logic and Applications, 396–404. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-540-48302-1_44.

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Conference papers on the topic "Field Programmable Gate Arrays (FPGA)"

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DeHon, A. "Entropy, Counting, and Programmable Interconnect." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242346.

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Chow, P., P. G. Gulak, and P. Chow. "A Field-Programmable Mixed-Analog-Digital Array." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242048.

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Lombardi, F., D. Ashen, Xiaotao Chen, and Wei Kang Huang. "Diagnosing Programmable Interconnect Systems for FPGAs." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242436.

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Kaviani, A., and S. Brown. "Hybrid FPGA Architecture." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242249.

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Tong Liu, Wei Kang Huang, and F. Lombardi. "Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242145.

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Vi Cuong Chan and D. M. Lewis. "Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242343.

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Amerson, R., R. Carter, W. Culbertson, P. Kuekes, G. Snider, and L. Albertson. "Plasma: An FPGA for Million Gate Systems." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242250.

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Bratt, A., and I. Macbeth. "Design and Implementation of a Field Programmable Analogue Array." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242434.

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Roy-Neogi, K., and C. Sechen. "Multiple FPGA Partitioning with Performance Optimization." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242148.

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Pak K. Chan, M. D. F. Schlag, and J. Y. Zien. "Spectral-Based Multi-Way FPGA Partitioning." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242146.

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Reports on the topic "Field Programmable Gate Arrays (FPGA)"

1

Mumbru, Jose, George Panotopoulos, and Demetri Psaltis. Optically Programmable Field Programmable Gate Arrays (FPGA) Systems. Fort Belvoir, VA: Defense Technical Information Center, January 2004. http://dx.doi.org/10.21236/ada421336.

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Manohar, Rajit. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA). Fort Belvoir, VA: Defense Technical Information Center, March 2015. http://dx.doi.org/10.21236/ada614130.

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Wawrzynek, J., and K. Asanovic. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture. Fort Belvoir, VA: Defense Technical Information Center, August 2009. http://dx.doi.org/10.21236/ada519578.

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Wirthlin, Michael, Brent Nelson, Brad Hutchings, Peter Athanas, and Shawn Bohner. Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows. Fort Belvoir, VA: Defense Technical Information Center, July 2008. http://dx.doi.org/10.21236/ada492273.

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Lin, Chun-Shin. High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA). Fort Belvoir, VA: Defense Technical Information Center, January 2010. http://dx.doi.org/10.21236/ada514601.

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Chang, Chen, and Kevin Camera. Exploring Field-Programmable Gate Array (FPGA)-Based Emulation Technologies for Accelerating Computer Architecture Development and Evaluation. Fort Belvoir, VA: Defense Technical Information Center, April 2009. http://dx.doi.org/10.21236/ada511786.

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El-Ghazawi, Tarek, Alan D. George, Ivan Gonzalez, Herman Lam, Saumil Merchant, Proshanta Saha, Melissa Smith, Greg Stitt, Nahid Alam, and Esam El-Araby. Exploration of a Research Roadmap for Application Development and Execution on Field-Programmable Gate Array (FPGA)-Based Systems. Fort Belvoir, VA: Defense Technical Information Center, October 2008. http://dx.doi.org/10.21236/ada494473.

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Tyler, Stephen C. The Design of a Frequency Domain Interference Excision Processor Using Field Programmable Gate Arrays. Fort Belvoir, VA: Defense Technical Information Center, January 2005. http://dx.doi.org/10.21236/ada432369.

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