Dissertations / Theses: 'Field Programmable Gate Arrays (FPGA)'

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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Hauck, Scott. "Multi-FPGA systems /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/7008.

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Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configuration data. For a wide set of benchmark circuits on various FPGAs, it is shown that the proposed methods outperform all previous configuration compression methods and, depending upon the relative size of the circuit to the device, compress within 5\% of the fundamental information theoretic limit. Moreover, it is shown that the corresponding decoders are simple to implement in hardware and scale well with device size and available configuration bandwidth. It is not unreasonable to expect that with little modification to existing FPGA configuration memory systems and acceptable increase in configuration power a 10-fold improvement in configuration delay could be achieved. The main contribution of this thesis is that it defines the limit of configuration compression for the FPGAs under consideration and develops practical methods of overcoming this reconfiguration bottleneck. The functional density of reconfigurable devices could thereby be enhanced and the range of potential applications reasonably expanded.

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Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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5

James, Calvin L. "COMPLEX WAVEFORM GENERATION UTILIZING FIELD PROGRAMMABLE GATE ARRAYS." International Foundation for Telemetering, 1997. http://hdl.handle.net/10150/609692.

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International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada
The basic building blocks for implementing complex waveform generators using a look-up table approach are random access memory (RAM) and read only memory (ROM) devices. Due to technological advancements in field programmable gate array (FPGA) development, these devices have the ability to allocate large amounts of memory elements within the same structure. The self containment property makes the FPGA a suitable topology for complex waveform generation applications. In addition, this self containment property significantly reduces implementation costs by reducing the number of external components required to support many applications. This paper examines the use of FPGA’s in various complex waveform generation applications. In particular, a discussion will ensue examining possible mappings of the time domain response of the complex waveform into memory elements of the FPGA. The analyses and examples contained in the sequel are from existing waveform generation applications, developed for Gauissian Minimum Shift Keying (GMSK) and Unbalanced Quadriphase Shift Keying (UQPSK) modulation formats.

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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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8

Lin, Yu Colin, and 林郁. "ArchSyn: an energy-efficient FPGA high-level synthesizer." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49799599.

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Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops a highly energy-efficient FPGA high-level synthesis tool, ArchSyn, using an application-specific coarse-grain architecture as an intermediate synthesis step. ArchSyn provides rapid and energy-efficient compilation of dataflow graphs (DFGs) on FPGAs by scheduling the dataflow operations on an array of directly connected simple configurable processing elements (CPEs). Each CPE in the array performs primitive compute operations according to a small local sequencer at each cycle. Data are communicated via multi-hop routing within the direct interconnect network. The scheduler schedules each compute operation of the DFG obtained from the high-level design to execute on a particular hardware CPE at a particular cycle. It also determines the communication schedule of the intermediate data among the producing and consuming CPEs, optionally buffering them with distributed memory along the path. As such, the lengthy process of synthesizing a full custom hardware design on FPGA is reduced to a scheduling and mapping process. By restricting the fine-grain programmability into a coarse grain processor network scheduling problem, the compilation time can be improved substantially, thereby improving the overall productivity of the designer. Furthermore, taking advantage of the programmability of FPGAs, the effect of the array interconnect architecture on the energy-efficiency of the resulting system is studied. By altering the array configuration, the data communication scheme among the CPEs must also be changed. This has a net effect on both the energy consumption spent on data movement as well as on the overall compute performance. It is shown that by using array topology that is customized to the input DFG, up to 28% improvement in energy-efficiency could be achieved. An exploratory framework based on a genetic algorithm was developed that allows us to obtain such application-specific connection network. Such degree of customization is possible only with the programmability of FPGAs. Moreover, such topology adaptation can be achieved rapidly as only routings between a fixed set of pre-placed CPEs are required. Implementations using ArchSyn and an existing FPGA compilation tool xPilot were compared. ArchSyn gave a 2X better energy consumption and a 11X better energy-delay product for computation with very regular and simple data dependency. For computation with irregular data dependency, the energy consumption and energy-delay product improvement was 9.6X and 199X.
published_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy

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Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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Källström, Petter. "Direct Digital Frequency Synthesis in Field-Programmable Gate Arrays." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56550.

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This thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs).

Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use.

Detta exjobb handlar om att skapa ett Matlab-program som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digital frekvenssyntes (DDFS). Ämnad hårdvara för implementeringen är en fältprogrammerbar grindmatris (FPGA).

Fokus i denna rapport ligger på hur en FPGA är uppbyggd, olika metoder för sinusgenerering och vilka kvaliteter på sinusvågen de ger och vilka resurser i hårdvaran de använder.

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11

Lamoureux, Julien. "Modeling and reduction of dynamic power in field-programmable gate arrays." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/414.

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Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs.

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Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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Mutlu, Baris Ragip. "Real-time Motion Control Using Field Programmable Gate Arrays." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612049/index.pdf.

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In this thesis, novel implementation methods for FPGA based real-time motion control systems are investigated. These methods are examined for conventional and modern controller topologies as well as peripheral device interfaces which are mutually essential pieces of a motion controller. The developed methods are initially tested one by one to assess the performance of the individual design
and finally an assembled solution is developed to test the overall design. Tests of the overall design are realized via hardware-in-the-loop simulation of a real-world control problem, selected as a CNC machining center. The developed methods are discussed in terms of their success, resource consumptions and attainable sampling rates.

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Ambat, Shadab Gopinath. "SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS." UKnowledge, 2008. http://uknowledge.uky.edu/gradschool_theses/511.

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The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

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15

Lu, Qi Charles. "Active tamper-detector hardware mechanism and FPGA implementation /." Diss., Online access via UMI:, 2006.

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16

Simmler, Harald C. "Preemptive multitasking auf FPGA-Prozessoren : ein Betriebssystem für FPGA-Prozessoren /." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9460961.

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17

Gundam, Madhuri. "Implementation of Directional Median Filtering using Field Programmable Gate Arrays." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/111.

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Median filtering is a non-linear filtering technique which is effective in removing impulsive noise from data. In this thesis, directional median filtering has been implemented using cumulative histogram of samples in several directions. Different methods to implement directional median filtering have been proposed. The filtered images are smoothed along the direction of the filtering window. All implementations aimed to generate outputs in the least amount of time, while reducing the resource utilization on hardware. The implementation methods were designed for Xilinx Virtex 5 FPGA devices but were also attempted on Spartan 3E. The proposed methods used less than 30% of the resources on Virtex 5 FPGA but the resource utilization on Spartan 3E exceeded the number of available resources. After an initial delay, methods 1 and 2 generate a new output for every 5 clock cycles while method 3 generates an output for every 1.5 clock cycles.

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Kornmesser, Klaus. "Das FPGA-Entwicklungssystem CHDL eine vollständige, C++-basierte Entwicklungsumgebung für FPGA-Koprozessoren /." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11612006.

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Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

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Balog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.

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Alotaibi, Khalid F. D. "A high level hardware description environment for FPGA-based image processing applications." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.287288.

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Catanzaro, Bryan C. "Higher radix floating-point representations for FPGA-based arithmetic /." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd808.pdf.

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Clark, Christopher R. "A Unified Model of Pattern-Matching Circuits for Field-Programmable Gate Arrays." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14138.

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The objective of this dissertation is to develop a methodology for describing the functionality, analyzing the complexity, and evaluating the performance of a large class of pattern-matching circuit design approaches for field-programmable gate arrays (FPGAs). The developed methodology consists of three elements. The first is a functional model and associated nomenclature that unifies a significant portion of published circuit design approaches while also illuminating many novel approaches. The second is a set of analytical expressions that model the area and time complexity of each circuit design approach based on attributes of a given pattern set. Third, software tools are developed that facilitate architectural design space exploration and circuit implementation. This methodology is used to conduct an extensive evaluation and comparison of design approaches under a wide range of conditions using pattern sets from multiple application domains as well as synthetic pattern sets. The results indicate strong dependences between pattern set properties and circuit performance and provide new insights on the fundamental nature of various design approaches. A number of techniques have been proposed for designing pattern-matching hardware circuits with reconfigurable FPGA chips. The use of FPGAs enables high performance because the circuits can be customized for a particular application and pattern set. A relatively unstudied consequence of tailoring circuits for specific patterns is that circuit area and performance are affected by various properties of the patterns used. Most previous work in this field only considers a single design approach and a small number of pattern sets. Therefore, it is not clear how each design is affected by pattern set properties. For a given set of patterns, it is difficult to determine which approach would be the most efficient or provide the highest performance. Previous attempts to compare approaches using results from different publications are conflicting and inconclusive due to variations in the FPGA devices, patterns, and circuit optimizations used. There has been no attempt to evaluate a wide range of designs under a common set of conditions. The methodology presented in this dissertation provides a framework for studying multiple aspects of FPGA pattern-matching circuits in a controlled and consistent manner.

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Chong, Michael Yee Jern Computer Science &amp Engineering Faculty of Engineering UNSW. "Customization of floating-point units for embedded systems and field programmable gate arrays." Publisher:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44399.

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While Application Specific Instruction Set Processors (ASIPs) have allowed designers to create processors with custom instructions to target specific applications, floating-point units (FPUs) are still instantiated as non-customizable general-purpose units, which if under utilized, wastes area and performance. However, customizing FPUs manually is a complex and time-consuming process. Therefore, there is a need for an automated custom FPU generation scheme. This thesis presents a methodology for generating application-specific FPUs customized at the instruction level, with integrated datapath merging to minimize area. The methodology reduces the subset of floating-point instructions implemented to the minimum required for the application. Datapath merging is then performed on the required datapaths to minimize area. Previous datapath merging techniques failed to consider merging components of different bit-widths and thus ignore the bit-alignment problem in datapath merging. This thesis presents a novel bit-alignment solution during datapath merging. In creating the custom FPU, the subset of floating-point instructions that should be implemented in hardware has to be determined. Implementing more instructions in hardware reduces the cycle count of the application, but may lead to increased delay due to multiplexers inserted on the critical path during datapath merging. A rapid design space exploration was performed to explore the trade-offs. By performing this exploration, a designer could determine the number of instructions that should be implemented as a custom FPU and the number that should be left for software emulation, such that performance and area meets the designer's requirements. Customized FPUs were generated for different Mediabench applications and compared to a fully-featured reference FPU that implemented all floating-point operations. Reducing the floating-point instruction set reduced the FPU area by an average of 55%. Performing instruction reduction and then datapath merging reduced the FPU area by an average of 68%. Experiments showed that datapath merging without bit-alignment achieved an average area reduction of 10.1%. With bit-alignment, an average of 16.5% was achieved. Bit-alignment proved most beneficial when there was a diverse mix of different bit-widths in the datapaths. Performance of Field-Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. Therefore, there is a need for embedded FPUs in FPGAs. However, if unutilized, they waste area on the FPGA die. To overcome this issue, a novel flexible multi-mode embedded FPU for FPGAs is presented in this thesis that can be configured to perform a wide range of operations. The floating-point adder and multiplier in the embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. It is also capable of floating-point and integer multiply-add operations. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on the FPGA with embedded FPU blocks. The implementations on the FPGA with embedded FPUs showed mean area and delay improvements of 5.2x and 5.8x respectively for the double-precision benchmarks, and 4.4x and 4.2x for the single-precision benchmarks.

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De, la Cruz Juan Alberto. "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays." DigitalCommons@USU, 2011. https://digitalcommons.usu.edu/etd/854.

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The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, with some additional resources used in the Field Programmable Gate Array (FPGA), a speed increase is obtained by using a one-dimensional Systolic Array (SA) approach. Additionally, extra guidelines are given for further research in this area.

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26

Galindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.

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27

Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.

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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.

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Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to ensure that area, timing and budget constraints of the application are met. The approach advocates the regular layout of modules surrounded by a wiring harness supporting the communications for those modules, and thus provides an advanced understanding of how to implement the "fixed wiring harness" model of reconfigurable computing proposed by Brebner. Results have shown that compared to flattened net lists the regularity of the layout does not impose significant overheads on critical path delays. At high communication densities it can even result in lower delays. The core of the methodology is an infrastructure generation process that allocates modules to slots and merges configuration graphs to form wiring harnesses that support the communications for these merged configurations. This thesis suggests methods and evaluates algorithms for configuration graph merging so as to reduce run-time reconfiguration overheads. Initial experiments with a greedy merging algorithm performed on an optical flow application resulted in a substantial reduction of 64% in reconfiguration time. The effects of graph merging with the initial greedy algorithm and an improved dynamic programming algorithm were explored for a range of device sizes and architectural parameters. Results show that configuration merging using the greedy method results in significant reductions to the reconfiguration delay. The dynamic programming algorithm provides consistent improvements above and beyond the savings provided by the greedy method. In addition, a strong correlation was identified between the quality of front-end design activities such as partitioning and the effectiveness of back-end implementations. The methodology is integrated into the Xilinx commercial tool flow for partial reconfiguration, and is effective for implementing applications for module-based FPGA reconfiguration where the modules and their communications requirements are known at design time. It also allows a system designer to consider alternate device sizes and parameters until a set is found that satisfies the application constraints.

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Parris, Matthew. "OPTIMIZING DYNAMIC LOGIC REALIZATIONS FOR PARTIAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS." Master's thesis, University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4128.

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Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.
M.S.Cp.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Engineering MSCpE

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30

Möhrke, Ulrich, Paul Herrmann, M. Steffen, and Wilhelm G. Spruth. "Ein Branch&Bound-Ansatz zur Verdrahtung von Field Programmable Gate-Arrays." Universität Leipzig, 1998. https://ul.qucosa.de/id/qucosa%3A34536.

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Zur Verdrahtung der meisten FPGA-Architekturen können die aus dem ASIC-Entwurf stammenden Werkzeuge wie z.B. Kanalverdrahter nicht eingesetzt werden. Eine vollautomatische Verdrahtung mit optimalen Signallaufzeiten kann nur dann erreicht werden, wenn bei gegebener Plazierung die Leitungführung den technologischen Gegebenheiten angepaßt wird. Diese unterscheiden sich deutlich von denen in ASICs. Im Rahmen des von der Deutschen Forschungsgemeinschaft (DFG) geförderten Gemeinschafts-Projekts „FPGA Entwurfssystem“, an dem die Universität Leipzig, die Universität Tübingen und die Technischen Universität München beteiligt sind, wurden am Lehrstuhl für Computersysteme (Prof. W.G. Spruth) des Instituts für Informatik der Universität Leipzig Verfahren zur effizienten und qualitativ hochwertigen Verdrahtung von FPGA-Bausteinen entwickelt. Es wird eine Beschreibung des Verdrahtungsproblems für FPGAs gegeben und ein Lösungsansatz mit Hilfe des Branch&Bound – Verfahrens vorgestellt. Die Ergebnisse in Form von Programmlaufzeiten, Länge des kritischen Pfades und Anzahl der betrachteten Suchknoten in Abhängigkeit von einer Vielzahl von Schaltungsvarianten sind tabellarisch dargestellt und dokumentieren eine deutliche Verkürzung der längsten Pfade gegenüber dem Plazier- und Verdrahtungswerkzeug von Xilinx. Abschließend werden Probleme und weiterführende Arbeiten diskutiert.

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31

Rangoonwala, Sakina Kougianos Elias. "A Verilog 8051 soft core for FPGA applications." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11013.

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32

Choi, Yuk-ming, and 蔡育明. "A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/206679.

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The era of big data has led to problems of unprecedented scale and complexity that are challenging the computing capability of conventional computer systems. One way to address the computational and communication challenges of such demanding applications is to incorporate the use of non-conventional hardware accelerators such as FPGAs into existing systems. By providing a mix of FPGAs and conventional CPUs as computing resources in a heterogeneous cluster, a distributed computing environment can be achieved to address the need of both compute-intensive and data-intensive applications. However, utilizing heterogeneous clusters requires application developers’ comprehensive knowledge on both hardware and software. In order to assist programmers to take advantage of the synergy between hardware and software easily, an easy-to-use framework for virtualizing the underlying FPGA computing resources of the heterogeneous cluster is motivated. In this work, a heterogeneous cluster consisting of both FPGAs and CPUs was built and a framework for managing multiple FPGAs across the cluster was designed. The major contribution of the framework is to provide an abstraction layer between the application developer and the underlying FPGA computing resources, so as to improve the overall design productivity. An inter-FPGA communication system was implemented such that gateware executing on FPGAs can communicate with each other autonomously to the CPU. Furthermore, to demonstrate a real-life application on the heterogeneous cluster, a generic k-means clustering application was implemented, using the MapReduce programming model. The implementation of the k-means application on multiple FPGAs was compared with a software-only version that was run on a Hadoop multi-core computer cluster. The performance results show that the FPGA version outperforms the Hadoop version across various parameters. An in-depth study on the communication bottleneck presented in the system was also carried out. A number of experiments were specifically designed to benchmark the performance of each I/O channel. The study shows that the major source of I/O bottleneck lies at the communication between the host system and the FPGA. This gives insight into programming considerations of potential applications on the cluster as well as improvement to the framework. Moreover, the benefit of multiple FPGAs was investigated through a series of experiments. Compared with putting all mappers on a single FPGA, it was found that distributing the same amount of mappers across more FPGAs can provide a tradeoff between FPGA resources and I/O performance.
published_or_final_version
Electrical and Electronic Engineering
Master
Master of Philosophy

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33

Weinstein, Randall Kenneth. "Techniques for FPGA neural modeling." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/26685.

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Thesis (Ph.D)--Bioengineering, Georgia Institute of Technology, 2007.
Committee Chair: Lee, Robert; Committee Member: Butera, Robert; Committee Member: DeWeerth, Steve; Committee Member: Madisetti, Vijay; Committee Member: Voit, Eberhard. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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Ng, Chiu-wa. "Bit-stream signal processing on FPGA." Click to view the E-thesis via HKUTO, 2009. http://sunzi.lib.hku.hk/hkuto/record/B41633842.

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Elsehely, Ehab Abou Bakr. "Radar target identification in jamming environments using multiscale wavelet transform on FPGA chip." Thesis, University of Kent, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.324709.

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McMurtrey, Daniel Lee. "Using duplication with compare for on-line error detection in FPGA-based designs /." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1642.pdf.

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HAWK, CHRISTOPHER J. "DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.

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38

Marolia, Pratik M. "Watermarking FPGA bitstream for IP protection." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24804.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Dr. Lee, Hsien-Hsin S.; Committee Member: Dr. Lim, Sung-Kyu; Committee Member: Dr. Yalamanchili, Sudhakar.

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Nigania, Nimit. "FPGA prototyping of custom GPGPUs." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51966.

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Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping of general-purpose graphics processing units (GPGPUs) on field programmable gate arrays (FPGAs) using a novel tool chain. This hardware flow combined with the higher level simulation flow using the same source code allowed us to create a whole tool chain to study and build future architectures using new technologies. It also gave us enough flexibility at different granularities to make architectural decisions. We will also discuss some example systems that were built using this tool chain along with some results.

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Sudarsanam, Arvind. "Analysis of Field Programmable Gate Array-Based Kalman Filter Architectures." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/788.

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A Field Programmable Gate Array (FPGA)-based Polymorphic Faddeev Systolic Array (PolyFSA) architecture is proposed to accelerate an Extended Kalman Filter (EKF) algorithm. A system architecture comprising a software processor as the host processor, a hardware controller, a cache-based memory sub-system, and the proposed PolyFSA as co-processor, is presented. PolyFSA-based system architecture is implemented on a Xilinx Virtex 4 family of FPGAs. Results indicate significant speed-ups for the proposed architecture when compared against a space-based software processor. This dissertation proposes a comprehensive architecture analysis that is comprised of (i) error analysis, (ii) performance analysis, and (iii) area analysis. Results are presented in the form of 2-D pareto plots (area versus error, area versus time) and a 3-D plot (area versus time versus error). These plots indicate area savings obtained by varying any design constraints for the PolyFSA architecture. The proposed performance model can be reused to estimate the execution time of EKF on other conventional hardware architectures. In this dissertation, the performance of the proposed PolyFSA is compared against the performance of two conventional hardware architectures. The proposed architecture outperforms the other two in most test cases.

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Chandrakar, Shant. "Memory Architecture Template for Fast Block Matching Algorithms on Field Programmable Gate Arrays." DigitalCommons@USU, 2009. https://digitalcommons.usu.edu/etd/495.

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Fast Block Matching (FBM) algorithms for video compression are well suited for acceleration using parallel data-path architectures on Field Programmable Gate Arrays (FPGAs). However, designing an efficient on-chip memory subsystem to provide the required throughput to this parallel data-path architecture is a complex problem. This thesis presents a memory architecture template that can be parameterized for a given FBM algorithm, number of parallel Processing Elements (PEs), and block size. The template can be parameterized with well known exploration techniques to design efficient on-chip memory subsystems. The memory subsystems are derived for two existing FBM algorithms and are implemented on a Xilinx Virtex 4 family of FPGAs. Results show that the derived memory subsystem in the best case supports up to 27 more parallel PEs than the three existing subsystems and processes integer pixels in a 1080p video sequence up to a rate of 73 frames per second. The speculative execution of an FBM algorithm for the same number of PEs increases the number of frames processed per second by 49%.

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Lillrose, Micah A. "High-speed data acquisition and FPGA detected pulse blanking system for interference mitigation in radio astronomy /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2076.pdf.

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Fong, Ryan Joseph Lim. "Improving Field-Programmable Gate Array Scaling Through Wire Emulation." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/35086.

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Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag behind ASICs due to interconnection scalability issues. To improve FPGA scalability, this thesis proposes an architectural enhancement to improve global communications in large FPGAs, where chip-length programmable interconnects are slow. It is expected that this architectural enhancement, based on wire emulation techniques, can reduce chip-length communication latency and routing congestion. A prototype wire emulation system that uses FPGA self-reconfiguration as a non-traditional means of intra-FPGA communication is implemented and verified on a Xilinx Virtex-II XC2V1000 FPGA. Wire emulation benefits and impact to FPGA architecture are examined with quantitative and qualitative analysis.
Master of Science

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44

Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.

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45

Krantz, Emil. "Utvärdering av Field-Programmable Gate Array (FPGA) som hjälpprocessor för prestandaökning." Thesis, University of Gävle, Department of Mathematics, Natural and Computer Sciences, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-586.

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Det här arbetet är en utvärdering om huruvida det finns problem som kan få en prestandavinst då man använder en Field-Programmable Gate Array (FPGA) som hjälpprocessor till en mikroprocessor i jämförelse men att enbart använda en mikro-processor. För att avgöra detta implementerades algoritmen gaussfiltrering dels på en mikroprocessor med språket C och dels för en FPGA med hårdvarubeskrivningsspråket Very-High-Speed Integrated Circuits Hardware Description Language (VHDL). Simuleringar gjordes för dessa två implementationer och resultatet visade att det var möjligt att få en prestandaökning på 25 gånger för denna speciella algoritm.

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46

Wright, Durke A. "Field programmable gate array (FPGA) based software defined radio (SDR) design." Thesis, Monterey, Calif. : Naval Postgraduate School, 2009. http://edocs.nps.edu/npspubs/scholarly/theses/2009/March/09Mar%5FWright.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2009.
Thesis Advisor(s): Kragh, Frank ; Loomis, Herschel. "March 2009." Description based on title screen as viewed on April 24, 2009. Author(s) subject terms: Software Defined Radio, SDR, Field Programmable Gate Array, FPGA, Signal Compression. Includes bibliographical references (p. 105-106). Also available in print.

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47

Billian, Bruce. "Next Generation Design of a Frequency Data Recorder Using Field Programmable Gate Arrays." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/34560.

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The Frequency Disturbance Recorder (FDR) is a specialized data acquisition device designed to monitor fluctuations in the overall power system. The device is designed such that it can be attached by way of a standard wall power outlet to the power system. These devices then transmit their calculated frequency data through the public internet to a centralized data management and storage server.

By distributing a number of these identical systems throughout the three major North American power systems, Virginia Tech has created a Frequency Monitoring Network (FNET). The FNET is composed of these distributed FDRs as well as an Information Management Server (IMS). Since frequency information can be used in many areas of power system analysis, operation and control, there are a great number of end uses for the information provided by the FNET system. The data provides researchers and other users with the information to make frequency analyses and comparisons for the overall power system. Prior to the end of 2004, the FNET system was made a reality, and a number of FDRs were placed strategically throughout the United States.

The purpose of this thesis is to present the elements of a new generation of FDR hardware design. These elements will enable the design to be more flexible and to lower reliance on some vendor specific components. Additionally, these enhancements will offload most of the computational processing required of the system to a commodity PC rather than an embedded system solution that is costly in both development time and financial cost. These goals will be accomplished by using a Field Programmable Gate Array (FPGA), a commodity off-the-shelf personal computer, and a new overall system design.

Master of Science

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48

Li, Hao. "Low power technology mapping and performance driven placement for field programmable gate arrays." [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000523.

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49

Thakkar, Anuja. "PIPELINING OF DOUBLE PRECISION FLOATING POINT DIVISION AND SQUARE ROOT OPERATIONS ON FIELD-PROGRAMMABLE GATE ARRAYS." Master's thesis, University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4194.

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Many space applications, such as vision-based systems, synthetic aperture radar, and radar altimetry rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be executed on DSP processors, the DSP numerical requirements of these new space applications surpass by far the numerical capabilities of many current DSP processors. Since the tradition in DSP processing has been to use fixed point number representation, only recently have DSP processors begun to incorporate floating point arithmetic units, even though most of these units handle only single precision floating point addition/subtraction, multiplication, and occasionally division. While DSP processors are slowly evolving to meet the numerical requirements of newer space applications, FPGA densities have rapidly increased to parallel and surpass even the gate densities of many DSP processors and commodity CPUs. This makes them attractive platforms to implement compute-intensive DSP computations. Even in the presence of this clear advantage on the side of FPGAs, few attempts have been made to examine how wide precision floating point arithmetic, particularly division and square root operations, can perform on FPGAs to support these compute-intensive DSP applications. In this context, this thesis presents the sequential and pipelined designs of IEEE-754 compliant double floating point division and square root operations based on low radix digit recurrence algorithms. FPGA implementations of these algorithms have the advantage of being easily testable. In particular, the pipelined designs are synthesized based on careful partial and full unrolling of the iterations in the digit recurrence algorithms. In the overall, the implementations of the sequential and pipelined designs are common-denominator implementations which do not use any performance-enhancing embedded components such as multipliers and block memory. As these implementations exploit exclusively the fine-grain reconfigurable resources of Virtex FPGAs, they are easily portable to other FPGAs with similar reconfigurable fabrics without any major modifications. The pipelined designs of these two operations are evaluated in terms of area, throughput, and dynamic power consumption as a function of pipeline depth. Pipelining experiments reveal that the area overhead tends to remain constant regardless of the degree of pipelining to which the design is submitted, while the throughput increases with pipeline depth. In addition, these experiments reveal that pipelining reduces power considerably in shallow pipelines. Pipelining further these designs does not necessarily lead to significant power reduction. By partitioning these designs into deeper pipelines, these designs can reach throughputs close to the 100 MFLOPS mark by consuming a modest 1% to 8% of the reconfigurable fabric within a Virtex-II XC2VX000 (e.g., XC2V1000 or XC2V6000) FPGA.
M.S.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering

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50

Teehan, Paul Leonard. "Reliable high-throughput FPGA interconnect using source-synchronous surfing and wave pipelining." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2767.

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FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.

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Dissertations / Theses on the topic 'Field Programmable Gate Arrays (FPGA)'

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