Journal articles: 'Field Programmable Gate Arrays (FPGA)'

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Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam, and Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays." International Journal of Handheld Computing Research 7, no. 4 (October 2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation. While the proposed camera is far from being able to compete with commercial offerings, it can serve as a framework to test new research ideas related to digital camera systems, image processing, computer vision, etc., as well as an educational platform for advanced digital design with VHDL and FPGAs. As examples of that, we report two spin-off projects developed on top of or starting from the presented digital camera system.

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Tufa, Guta Tesema, Fitsum Assamnew Andargie, and Anchit Bijalwan. "Acceleration of Deep Neural Network Training Using Field Programmable Gate Arrays." Computational Intelligence and Neuroscience 2022 (October 17, 2022): 1–11. http://dx.doi.org/10.1155/2022/8387364.

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Convolutional neural network (CNN) training often necessitates a considerable amount of computational resources. In recent years, several studies have proposed for CNN inference and training accelerators in which the FPGAs have previously demonstrated good performance and energy efficiency. To speed up the processing, CNN requires additional computational resources such as memory bandwidth, a FPGA platform resource usage, time, power consumption, and large datasets for training. They are constrained by the requirement for improved hardware acceleration to support scalability beyond existing data and model sizes. This paper proposes a procedure for energy efficient CNN training in collaboration with an FPGA-based accelerator. We employed optimizations such as quantization, which is a common model compression technique, to speed up the CNN training process. Additionally, a gradient accumulation buffer is used to ensure maximum operating efficiency while maintaining gradient descent of the learning algorithm. To validate the design, we implemented the AlexNet and VGG-16 models on an FPGA board and laptop CPU along side GPU. It achieves 203.75 GOPS on Terasic DE1 SoC with the AlexNet model and 196.50 GOPS with the VGG-16 model on Terasic DE-SoC. Our result also exhibits that the FPGA accelerators are more energy efficient than other platforms.

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Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

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A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acquisition system has characteristics of stable performance, flexible expansion, high real-timeness and integration

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Chen, Yonghao, Tianrui Li, Xiaojie Chen, ZhiGang Cai, and Tao Su. "High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays." Electronics 12, no. 4 (February 6, 2023): 822. http://dx.doi.org/10.3390/electronics12040822.

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The systolic array is frequently used in accelerators for neural networks, including Transformer models that have recently achieved remarkable progress in natural language processing (NLP) and machine translation. Due to the constraints of FPGA EDA (Field Programmable Gate Array Electronic Design Automation) tools and the limitations of design methodology, existing systolic array accelerators for FPGA deployment often cannot achieve high frequency. In this work, we propose a well-designed high-frequency systolic array for an FPGA-based Transformer accelerator, which is capable of performing the Multi-Head Attention (MHA) block and the position-wise Feed-Forward Network (FFN) block, reaching 588 MHz and 474 MHz for different array size, achieving a frequency improvement of 1.8× and 1.5× on a Xilinx ZCU102 board, while drastically saving resources compared to similar recent works and pushing the utilization of each DSP slice to a higher level. We also propose a semi-automatic design flow with constraint-generating tools as a general solution for FPGA-based high-frequency systolic array deployment.

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Guillemenet, Y., L. Torres, G. Sassatelli, and N. Bruchon. "On the Use of Magnetic RAMs in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–9. http://dx.doi.org/10.1155/2008/723950.

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This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

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Brown, Stephen, Muhammad Khellah, and Guy Lemieux. "Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (January 1, 1996): 275–91. http://dx.doi.org/10.1155/1996/45983.

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This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the effective utilization of available interconnect resources in an FPGA, and the speed-performance of implemented circuits. The major contributions of this research include the following: 1) we illustrate the effect of a global router on both area-utilization and speed-performance of implemented circuits, 2) experiments quantify the impact of the detailed router cost functions on area-utilization and speed-performance, 3) we show the effect on circuit implementation of dividing multi-point nets in a circuit being routed into point-to-point connections, and 4) the paper illustrates that CAD routing tools should account for both routability and speed-performance at the same time, not just focus on one goal.

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Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, and Rahul Khanna. "Field Programmable Gate Array Applications—A Scientometric Review." Computation 7, no. 4 (November 11, 2019): 63. http://dx.doi.org/10.3390/computation7040063.

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Amer Abbas, Yasir, Razali Jidin, Norziana Jamil, Muhammad Reza Z\'aba, and Mohd Ezanee Rusli. "PRINCE IP-core on Field Programmable Gate Arrays (FPGA)." Research Journal of Applied Sciences, Engineering and Technology 10, no. 8 (July 20, 2015): 914–22. http://dx.doi.org/10.19026/rjaset.10.2447.

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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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Das, N., P. Roy, and H. Rahaman. "Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)." Journal of The Institution of Engineers (India): Series B 96, no. 3 (July 15, 2014): 227–36. http://dx.doi.org/10.1007/s40031-014-0141-9.

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., Karthik S. "REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB." International Journal of Research in Engineering and Technology 03, no. 04 (April 25, 2014): 842–45. http://dx.doi.org/10.15623/ijret.2014.0304149.

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Ramezani, Hadise, Majid Mohammadi, and Amir Sabbagh Molahosseini. "An efficient look up table based approximate adder for field programmable gate array." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (January 1, 2022): 144. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp144-151.

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The approximate computing is an alternative computing approach which can lead to high-performance implementation of audio and image processing as well as deep learning applications. However, most of the available approximate adders have been designed using application specific integrated circuits (ASICs), and they would not result in an efficient implementation on field programmable gate arrays (FPGAs). In this paper, we have designed a new approximate adder customized for efficient implementation on FPGAs, and then it has been used to build the Gaussian filter. The experimental results of the implementation of Gaussian filter based on the proposed approximate adder on a Virtex-7 FPGA, indicated that the resource utilization has decreased by 20-51%, and the designed filter delay based on the modified design methodology for building approximate adders for FPGA-based systems (MDeMAS) adder has improved 10-35%, due to the obtained output quality.

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Howard, Neil J., Andrew M. Tyrrell, and Nigel M. Allinson. "The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks." VLSI Design 4, no. 2 (January 1, 1996): 135–39. http://dx.doi.org/10.1155/1996/17505.

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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.

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Tran, Hoang T., Dong LT Tran, Quang N. Pham, Thanh C. Vo, Quan NA Nguyen, Thang K. Nguyen, Duyen M. Ha, and Minh T. Nguyen. "Field programmable gate array based moving object tracking system for robot navigation." Bulletin of Electrical Engineering and Informatics 12, no. 2 (April 1, 2023): 771–81. http://dx.doi.org/10.11591/eei.v12i2.4538.

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This paper proposes a method in which an object tracking robot system is implemented on field programmable gate arrays (FPGAs). The OV7670 camera provides real-time object pictures to the system. To improve picture quality, images are put via the median filter phase. The item is distinguished from the backdrop based on color (red), after which it is subjected to a mathematical morphological approach of filtering to eliminate noise. To send the robot control signals, the object's (new) coordinates are found. In this method, the median filter, color separation, hardware IP cores, and morphological filter are all part of the embedded system on FPGA. Through the direct memory access (DMA) controller, these cores may communicate and perform high-speed pipeline computing at higher data rates. The entire system is executed in real-time on Xilinx's spartan-6 FPGA KIT. The results show practical and promise.

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Lai, Chiu-Keng, Yaw-Ting Tsao, Shou-Liang Tsai, and Wei-Nan Chien. "Development of an FPGA-Based Motion Control IC for Caving Machine." Advances in Mechanical Engineering 6 (January 1, 2014): 813204. http://dx.doi.org/10.1155/2014/813204.

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Since the Field Programmable Gate Arrays (FPGAs) with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

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Bhuvaneswari, Thangavel, Nor Hidayati Abdul Aziz, Jakir Hossen, and Chinthakunta Venkataseshaiah. "Field Programmable Gate Array (FPGA) Based Microwave Oven." Applied Mechanics and Materials 892 (June 2019): 120–26. http://dx.doi.org/10.4028/www.scientific.net/amm.892.120.

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In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms are generated using Modelsim 10.1d software. The simulation results for various cases have been presented and the results confirmed that all the basic functionalities of a practical microwave oven can be realized. The proposed FPGA based controller has a high potential for incorporation in microwave ovens.

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ROSENDAHL, G. K., R. D. MCLEOD, and H. C. CARD. "A DSP–FPGA-BASED RECONFIGURABLE COMPUTER." Journal of Circuits, Systems and Computers 08, no. 04 (August 1998): 453–59. http://dx.doi.org/10.1142/s0218126698000250.

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In order to exploit architectural advantages associated with specific computations while at the same time having flexibility in those computations, we have designed a reconfigurable parallel machine architecture. A prototype reconfigurable computer has been constructed based on digital signal processing (DSP) chips and field-programmable gate arrays (FPGAs). Communications are based upon a broadcast network that employs FPGA-based message pre-processing and post-processing. Tradeoffs between computational and communication performance are made possible by software reconfiguration of the FPGAs. The system has been successfully tested on several applications in signal processing.

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Neelima, S., and R. Brindha. "512 bit-SHA3 design approach and implementation on field programmable gate arrays." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (November 1, 2019): 169. http://dx.doi.org/10.11591/ijres.v8.i3.pp169-174.

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In this work, the authors consider the newly selected Hash Secure (SHA-3) algorithm on FPGA Gateway. The design is logically optimized for zone efficiency by combining the Rho steps and the one-pass algorithm. Logically recording these three steps registers leads to usage 16% of the logical resources for all implementations. This in turn reduces the latency and increases the maximum operating frequency of the project. It uses only 240 sections and has a frequency of 301.02 MHz compared to the design results with the previous FPGA implementation described in SHA3-512, the design shows the Throughput-Per-Slice (TPS) ratio of 30, 1.

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Bojja Venkatakrishnan, Satheesh, Elias A. Alwan, and John L. Volakis. "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer." International Journal of Reconfigurable Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/7802735.

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

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Keller, Andrew M., and Michael J. Wirthlin. "The Impact of Terrestrial Radiation on FPGAs in Data Centers." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (June 30, 2022): 1–21. http://dx.doi.org/10.1145/3457198.

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Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.

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Pradeep, Sunkari, Yogesh Kumar Sharma, Chaman Verma, Gutha Sreeram, and Panugati Hanumantha Rao. "Express Data Processing on FPGA: Network Interface Cards for Streamlined Software Inspection for Packet Processing." Applied System Innovation 6, no. 1 (January 9, 2023): 9. http://dx.doi.org/10.3390/asi6010009.

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Modern computers’ network interface cards (NICs) are undergoing changes in order to handle greater data rates and assist with scaling problems caused by general-purpose CPU technology. The inclusion of programmable accelerators to the NIC’s data channel is one of the ongoing improvements that is particularly intriguing since it gives the accelerator the chance to take on a portion of the CPU’s network packet processing duties. Accelerators are frequently developed using platforms like field-programmable gate arrays because packet processing operations have severe latency requirements (FPGAs). When implementing packet processing activities, FPGAs’ gain for through put is the number of data packets being successfully sent per second and latency is the actual time those packets take. However, due to their restricted resources, programming may need to be shared throughout a variety of applications. We provide hXDP, a software solution for FPGAs that targets the Linux eXpress Data Path and performs packet processing functions outlined with the eBPF technology. While maintaining performance on par with top-tier CPUs, hXDP only uses a tiny portion from the field programmable gate arrays, which are semiconductor devices that are based around a matrix of configuration logic blocks (CLB) connected over programmable interconnects. However, we demonstrate that when aiming towards a purpose-built FPGA architecture, many extended Berkeley packet filters (eBPF) allow programmers to use Berkeley packet filter byte code that makes use of certain kernel resources and instruction set architecture, to collocate and even eliminate, with considerably productivity and effectiveness. On an FPGA NIC, we implement hXDP and test its effectiveness using authentic eBPF programmes from the real world. Our version consumes 15% of the FPGA resources and operates at 156.25 MHz. This can constantly change and lead to the act of identification, inspection, extraction, and manipulation so that a network may make more intelligent management decisions.

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Lai, Chiu Keng, Yaw Ting Tsao, Shou Liang Tsai, and Wei Nan Chen. "An Integrated Realization of Motion Control and Motor Drives with FPGA." Applied Mechanics and Materials 479-480 (December 2013): 607–11. http://dx.doi.org/10.4028/www.scientific.net/amm.479-480.607.

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Since the Field Programmable Gate Arrays (FPGAs) with high density are available nowadays, systems with complex functions can be realized by FPGA in a single chip while they are usually traditionally implemented by several individual chips. In this research, the drives as well as motion controller are integrated and implemented on Altera Cyclone III FPGA. The system is also evaluated by applying it to a 3-axis motion platform driven by stepping motors. Finally, experimental results of current regulator and motion controller are shown to prove the validness.

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Baans, Omar Salem, and Asral Bahari Jambek. "Implementation of an ARM-based system using a Xilinx ZYNQ SoC." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 485. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp485-491.

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ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.

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Saleh, Shukur Bin, Sulaiman Bin Mazlan, Nik Iskandar Bin Hamzah, Ahmad Zahid Zakwan Bin Abdul Karim, Mohd Shamian Bin Zainal, Shipun Anuar Bin Hamzah, Danial Bin Md Nor, and Hazwaj Bin Mhd Poad. "Smart Home Security Access System Using Field Programmable Gate Arrays." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (July 1, 2018): 152. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp152-160.

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Nowadays, the rapid growth of burglary and theft cases over the world has been threatening to the vulnerability of traditional home security systems. Therefore the development home security with intelligent control wherein focus to enhance conventional technique to theadvanced digital security systemand to be more interestinginhome or building owner for preventing intruders in smart home implementation. However, using avariety of type conventional lock doors for security purposes and analog intruder sensor with individual function system is not secure enoughin order to protect the person or company properties. That why the emergence of new technology such as integrated circuit network will apply in Smart Home system for abetter security solution to prevent the houses from theintruder and hazardous fire incident. Therefore, this project is done to design and build a smart system with consist of digital security entry for automatic lock doors and also for activating or deactivate all security sensor in houses which is function for detecting the irregular movement and hot temperature (fire incident) in-house for the domestic residential sector. This product includeswith doors automatic lock system using servo motor and detect irregular movement intruder using PIR motion sensor (HC-SR501) and also measure hot temperature using temperature sensor (LM35). The sensor will transmit theanalog signal to Field Programmable Gate Array (FPGA) the Altera DE2-115 board to be processed and which will then display the status entry after key-in password and activation security system on the LED seven segment displays. The entry login controller will use apush button or switchesavailable on FPGA board that are used to login password for automatic door accessand also able maintained for control home smart security system.

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Reddy, Naresh Kumar, and N. Suresh. "An Efficient approach for Design and Testing of FPGA Programming using LabVIEW." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 192. http://dx.doi.org/10.11591/ijres.v4.i3.pp192-200.

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Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.

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Kou, Zhengchang, and Michael L. Oelze. "Ultrafast ultrasound beamformer for plane wave imaging with field programmable gate array." Journal of the Acoustical Society of America 153, no. 3_supplement (March 1, 2023): A353. http://dx.doi.org/10.1121/10.0019131.

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In this work, we propose a novel method of implementing an ultrafast ultrasound beamformer for plane wave imaging (PWI) on a field programmable gate array (FPGA). First, a modified delay calculation method was proposed to (1) separate the transmit and receive delay, (2) reduce the size of delay profile, and (3) enable parallel beamforming by delay reuse and data vectorization. Second, a parallelized implementation of beamformer on single FPGA was proposed by (1) loading pre-calculated delay profile from external memory instead of calculating delay on run-time, (2) vectorizing channel data fetching, (3) compensating transmit and receive delays separately, and (4) using fixed summing networks to reduce consumption of logic resources. The proposed method was also highly scalable, which was demonstrated by implementing the beamformer with different beamforming rates ranging from 2.4 G to 9.6 G samples per second to three different sizes of FPGAs ranging from entry-level FPGA to high-end FPGA. The power consumption was less than 3 watts for 2.4 G samples per second beamforming rate, which demonstrates the possibility of implementing ultrafast ultrasound imaging on handheld probe. The FPGA beamformer’s results were compared with Verasonics CPU beamformer’s result to verify that the image quality was not compromised for speed.

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da Silva, Bruno, An Braeken, and Abdellah Touhafi. "FPGA-Based Architectures for Acoustic Beamforming with Microphone Arrays: Trends, Challenges and Research Opportunities." Computers 7, no. 3 (August 3, 2018): 41. http://dx.doi.org/10.3390/computers7030041.

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Over the past decades, many systems composed of arrays of microphones have been developed to satisfy the quality demanded by acoustic applications. Such microphone arrays are sound acquisition systems composed of multiple microphones used to sample the sound field with spatial diversity. The relatively recent adoption of Field-Programmable Gate Arrays (FPGAs) to manage the audio data samples and to perform the signal processing operations such as filtering or beamforming has lead to customizable architectures able to satisfy the most demanding computational, power or performance acoustic applications. The presented work provides an overview of the current FPGA-based architectures and how FPGAs are exploited for different acoustic applications. Current trends on the use of this technology, pending challenges and open research opportunities on the use of FPGAs for acoustic applications using microphone arrays are presented and discussed.

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Liu, Qian, and Dan Wu. "FPGA Auto Configuration Based on ATE." Applied Mechanics and Materials 121-126 (October 2011): 3310–14. http://dx.doi.org/10.4028/www.scientific.net/amm.121-126.3310.

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FPGAs (Field Programmable Gate Arrays) are highly integrated devices which can be programmed as variable functions. The application-level testing of FPGAs usually include multiple reconfigurations and relevant functional tests respectively through ATEs (Automated Test Equipments). However, test engineers are facing a tough problem to reconfigure FPGAs automatically through an ATE instead of using specific tools and download cables provided by FPGAs manufacturers. This paper takes example for XILINX Virtex-E series, presents two different methods for FPGA auto configuration based on an ATE using JTAG configuration interface and boundary-scan protocol, and accomplishes the entire auto configuration-test procedure by a single ATE.

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Joler, Miroslav. "How FPGAs Can Help Create Self-Recoverable Antenna Arrays." International Journal of Antennas and Propagation 2012 (2012): 1–10. http://dx.doi.org/10.1155/2012/196925.

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An approach to utilize Field Programmable Gate Array (FPGA) technology to control antenna arrays is presented based on the scenario of sensing a failure of any array element, analyzing degradation of the radiation pattern due to that failure, and finding a new set of excitations to the array elements in order to recover the radiation pattern as close to the original state as possible, thus creating aself-recoverable antenna array(SRA). The challenges of the SRA concept and embodiment of the recovery algorithm(s) are discussed. The results of the radiation recovery are presented on a few array cases, followed by a discussion on the advantages and possible limitations of the FPGA-based array control.

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Quang, Nguyen Khanh, and Nguyen Ho Quang. "FPGA Technology and Sequential Finite State Machine Method." Hue University Journal of Science: Natural Science 127, no. 1D (December 10, 2018): 55. http://dx.doi.org/10.26459/hueuni-jns.v127i1d.5073.

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The implementation of complex control algorithms on an FPGA (Field programmable gate arrays) is still at a basic level. There is no fixed method to develop algorithms on these devices because of their general characteristics. Therefore, the design engineers are still on the way to find the good approaches to optimize the implementation of algorithms on FPGAs [1-7]. This paper presents and demonstrates a sequential finite state machine design method that can solve the issue of optimal usage of the limited resources on an FPGA.

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Hasnat, Abul, Anindya Ghosh, Amina Khatun, and Santanu Halder. "Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System." Fibres and Textiles in Eastern Europe 25 (February 28, 2017): 42–48. http://dx.doi.org/10.5604/01.3001.0010.1709.

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This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

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LI, XIAOYING, and ENHUA WU. "RELIEF TEXTURE MAPPING ON FIELD PROGRAMMABLE GATE ARRAY." International Journal of Image and Graphics 06, no. 04 (October 2006): 641–55. http://dx.doi.org/10.1142/s021946780600246x.

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Relief texture mapping is an image-based rendering technique which can successfully support the representation of 3D surface details and view motion parallax. It has the potential to significantly increase visual realism of rendered geometry while keeping system load constant. In this paper, FPGA (Field Programmable Gate Array) chip technology is applied to this three-dimensional image warping method. A relief texture mapping system has been implemented on a reprogrammable and reconfigurable FPGA board. The algorithm is optimized for the specific architecture and the framework is customized for circuit resources, which can be flexibly changed for other structures. In our design, we take advantage of inherent parallelism of the algorithm by concatenating multiple warping engines and well organizing data in memory space. Experimental results show high image quality with improved rendering speed.

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JOHNSTON, S. P., G. PRASAD, L. MAGUIRE, and T. M. MCGINNITY. "AN FPGA HARDWARE/SOFTWARE CO-DESIGN TOWARDS EVOLVABLE SPIKING NEURAL NETWORKS FOR ROBOTICS APPLICATION." International Journal of Neural Systems 20, no. 06 (December 2010): 447–61. http://dx.doi.org/10.1142/s0129065710002541.

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This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem.

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Kumar Reddy, B. Naresh, N. Suresh, and J. V. N. Ramesh. "A Gracefully Degrading and Energy-Efﬁcient FPGA Programming using LabVIEW." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (November 1, 2016): 165. http://dx.doi.org/10.11591/ijres.v5.i3.pp165-175.

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Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.

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Hyodo, Kazuhito, Hirokazu Noborisaka, Keijiro Yamamoto, and Takashi Yada. "Development of a Portable Multipurpose Controller for Mechatronics Education." Journal of Robotics and Mechatronics 19, no. 2 (April 20, 2007): 223–31. http://dx.doi.org/10.20965/jrm.2007.p0223.

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The control module we developed for mechatronics education, consists of a Field-programmable gate array (FPGA), a Programmable System-On-Chip (PSoC) and Game Boy Advance (GBA). The FPGA and PSoC provide a reconfigurable peripheral module and the GBA provides computational power and an interactive user interface. The interactive user interface is very useful for developing educational materials, and the control module enables educators to develop a variety of educational materials.

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Kurniawan, Yusuf, and Muhammad Adli Rizqulloh. "Block cipher four implementation on field programmable gate array." Communications in Science and Technology 5, no. 2 (December 26, 2020): 53–64. http://dx.doi.org/10.21924/cst.5.2.2020.184.

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Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.

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Govil, Anchal, Anmol Karnwal, Govinda Sindhu, Ayush Singh, and Dr Shubham Shukla. "Design and Implementation of UART Using FPGA Board." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (April 30, 2022): 1187–90. http://dx.doi.org/10.22214/ijraset.2022.41478.

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Abstract: This paper introduces the implementation of the Universal Asynchronous Receiver- Transmitter Controller (UART) based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our UART design is fully functional and built-in. Coded using the Verilog design from top to bottom and visible in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. Use results show that the design can work Spartan-3E FPGA maximum clock frequency of 218.248 MHz. The maximum frequent use of the UART controller is 192.773 MHz. of bits and hence this is why with a small amount of storage. Keywords: Receiver, Transmitter, Microprogrammed Controller and Field Programmable Gate Array (FPGA).

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Xiong, Xu, Xuecheng Du, Bo Zheng, Zhi Chen, Wei Jiang, Sanjun He, and Yixin Zhu. "Soft Error Sensitivity Analysis Based on 40 nm SRAM-Based FPGA." Electronics 11, no. 23 (November 22, 2022): 3844. http://dx.doi.org/10.3390/electronics11233844.

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Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the failure mechanisms of the FPGA. The SEEs test results for the FPGA device based on the 40 nm CMOS process are significant.

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Zgheib, Grace, and Iyad Ouaiss. "Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550039. http://dx.doi.org/10.1142/s0218126615500395.

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In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.

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Semka, E. V., A. B. Buslaev, V. V. Ovcharov, A. A. Pirogov, and S. A. Gvozdenko. "Software driver for working with different types of SPI interfaces." Issues of radio electronics 49, no. 9 (October 28, 2020): 38–45. http://dx.doi.org/10.21778/2218-5453-2020-9-38-45.

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Field-Programmable Gate Arrays (FPGAs) are configurable integrated circuits whose logic is defined through programming. The use of FPGAs makes it possible to obtain devices capable of changing the configuration, adapting to a specific task due to their flexibly changeable, programmable structure. When developing complex devices, ready-made IP-cores can be used as components for design. The use of software IP-cores allows them to be used most effectively in the final structure, to a significant extent to reduce design costs. A software driver has been developed for working with different types of SPI interfaces (Serial Peripheral Interface), which implements switching the input-output line when transmitting data through a FPGA.

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41

Sorokoumov, Georgy. "Single event transients monitoring and diagnostic in FPGA." Facta universitatis - series: Electronics and Energetics 31, no. 3 (2018): 401–10. http://dx.doi.org/10.2298/fuee1803401s.

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Analysis of single event transients (SETs) generated in field programmable gate arrays (FPGA) under heavy charged particles (HCP) irradiation and SET suppression methods is performed. The circuit for FPGA SET detection is designed for transients generated both inside FPGA and outside at package pin level. SET registration inside FPGA is carried out as an event when logical cell is switched. The SET control schematic circuit efficiency has been comparatively verified using heavy ion accelerator and picosecond focused laser source. SET in FPGA experimental results are presented and discussed.

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42

Tajary, Alireza, and Behnam Ghavami. "A Metallic CNT Tolerant Design Methodology for Carbon Nanotube-Based Programmable Gate Arrays." Journal of Circuits, Systems and Computers 25, no. 02 (December 23, 2015): 1650016. http://dx.doi.org/10.1142/s021812661650016x.

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Carbon nanotube field effect transistor (CNFET) is one of the promising technologies as a replacement for current CMOS technology due to its excellent electronic properties. CNFETs can be fabricated in regular structures, making them ideal for creating the repetitive architectures found in field programmable gate arrays (FPGAs). However, CNFETs face some fabrication challenges. The unwanted metallic carbon nanotubes (CNTs) are one of the major challenges in using CNFET technology for FPGAs. In this paper, we take the advantage of FPGAs programmability allowing reconfiguration around the metallic CNTs to tolerate this defect. We demonstrate a multi-stage solution to the metallic CNT problem in CNFET-based FPGAs that does not require any metallic nanotube removal of any kind. The proposed methodology consists of four consecutive stages in logic mapping process: (i) reordering of input variables, (ii) inputs complementing, (iii) adding inputs redundancy to basic logic element (BLE) and (iv) BLE lookup table (LUT) splitting. A fault simulation tool is designed to work closely with VPR, an academic FPGA CAD tool, to provide the investigation of metallic CNTs effects on CNFET-based FPGAs. Experimental results show that the proposed method can successfully map all logical nets at a cost of [Formula: see text] area overhead if the fraction of metallic CNTs is reduced to 30%.

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43

Bailey, Donald G. "Image Processing Using FPGAs." Journal of Imaging 5, no. 5 (May 10, 2019): 53. http://dx.doi.org/10.3390/jimaging5050053.

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Nine articles have been published in this Special Issue on image processing using field programmable gate arrays (FPGAs). The papers address a diverse range of topics relating to the application of FPGA technology to accelerate image processing tasks. The range includes: Custom processor design to reduce the programming burden; memory management for full frames, line buffers, and image border management; image segmentation through background modelling, online K-means clustering, and generalised Laplacian of Gaussian filtering; connected components analysis; and visually lossless image compression.

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44

Ajitha, C., and T. Jaya. "Field Programmable Gate Arrays (FPGA) Based Computational Complexity Analysis of Multicarrier Waveforms." Intelligent Automation & Soft Computing 34, no. 2 (2022): 1033–48. http://dx.doi.org/10.32604/iasc.2022.021984.

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45

Bamerni, Serwan Ali, and Ahmed Kh Al-Sulaifanie. "Field programmable gate arrays implementation of different standard deviation estimation techniques." Indonesian Journal of Electrical Engineering and Computer Science 27, no. 1 (July 1, 2022): 118. http://dx.doi.org/10.11591/ijeecs.v27.i1.pp118-130.

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Additive white Gaussian noise level estimation has found its application in many fields such as biomedical signal processing, communication system, and image processing. Many methods have been proposed with different output accuracy, system complexity, power consumption, and speed. In this paper, three of the most well-known and largely used algorithms (median based, root mean square (RMS) based, and P84 based methods) have been implemented and investigated in a full comparison between them to find their advantage and disadvantage, and the suitability of each method for a specific application. The three designs are created using Xilinx system generator (XSG) and implemented on Xilinx field programmable gate arrays (FPGA) development board with Zynq series "XC7Z020-1CLG484", to evaluate the design's performance and the results are discussed in the paper.

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46

C. P., Mallikarjuna Gowda, and Raju Hajare. "Space-time trellis codes: Field programmable gate array approach." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 3 (November 1, 2020): 213. http://dx.doi.org/10.11591/ijres.v9.i3.pp213-223.

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This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

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Zhao, Tianrun. "FPGA-Based Machine Learning: Platforms, Applications, Design Considerations, Challenges, and Future Directions." Highlights in Science, Engineering and Technology 62 (July 27, 2023): 96–101. http://dx.doi.org/10.54097/hset.v62i.10430.

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Field-Programmable Gate Arrays (FPGAs) have emerged as a promising platform for accelerating machine learning tasks due to their high parallelism, low latency, and hardware customization ability. In this paper, the authors provide an overview of popular FPGA platforms for machine learning and compare the tradeoffs among FPGAs, GPUs, and CPUs for machine learning. The authors also present specific applications of machine learning based on FPGAs, including those in autonomous driving and healthcare. Additionally, the paper explores FPGA design considerations, such as architecture, resource utilization, and power consumption. Nonetheless, obstacles persist in the realm of FPGA-based machine learning that require attention. Identifying the ideal balance between adaptability and performance, considering factors such as space, energy usage, and latency, is still challenging. As the capabilities of FPGAs expand, there is a significant need for devices that have a smaller footprint, reduced power consumption, and minimized delays. The paper emphasizes the necessity of ongoing research in the field of FPGA-based machine learning to address these issues and continue enhancing the performance and effectiveness of machine learning systems.

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Chin, Scott Y. L., Clarence S. P. Lee, and Steven J. E. Wilton. "On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–13. http://dx.doi.org/10.1155/2008/751863.

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We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

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Xie, Weikun, Wenjing Qi, Xiaohui Lin, and Houjun Wang. "Research on an Intelligent Test Method for Interconnect Resources in an FPGA." Applied Sciences 13, no. 13 (July 7, 2023): 7951. http://dx.doi.org/10.3390/app13137951.

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With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs.

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Zhang, Jun Bin, Jin Yan Cai, and Dan Yang Li. "A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register." Applied Mechanics and Materials 347-350 (August 2013): 1602–6. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1602.

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With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of FPGA Configurable Logic Blocks was advanced. The paper analyses the design theory about core circuit configure, and has important significance impact on Fault Orientation of FPGA Configurable Logic Blocks.

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Journal articles on the topic 'Field Programmable Gate Arrays (FPGA)'

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