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Dissertations / Theses on the topic 'Field programmable gate arrays. Image processing'

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Published: 4 June 2021

Last updated: 16 February 2022

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1

De, la Cruz Juan Alberto. "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays." DigitalCommons@USU, 2011. https://digitalcommons.usu.edu/etd/854.

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The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, wit

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2

Alotaibi, Khalid F. D. "A high level hardware description environment for FPGA-based image processing applications." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.287288.

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3

Chen, Luna. "Fast generation of Gaussian and Laplacian image pyramids using an FPGA-based custom computing platform." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020239/.

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4

Donachy, Paul. "Design and implementation of a high level image processing machine using reconfigurable hardware." Thesis, Queen's University Belfast, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337688.

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5

Isaacson, Spencer William. "Hardware support for a configurable architecture for real-time embedded systems on a programmable chip /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1966.pdf.

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6

Cappabianco, Fabio Augusto Menocci. "Uma plataforma de hardware para processamento de imagem baseada na transformada imagem-floresta." [s.n.], 2006. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275908.

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Orientadores: Guido Costa Souza de Araujo, Alexandre Xavier Falcão<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação<br>Made available in DSpace on 2018-08-07T09:45:52Z (GMT). No. of bitstreams: 1 Cappabianco_FabioAugustoMenocci_M.pdf: 2472578 bytes, checksum: 8df546b29eccff4337413df4b5d9a7c3 (MD5) Previous issue date: 2006<br>Resumo: Implementações de operadores de processamento de imagens em plataformas de hardware têm obtido ótimos resultados devido a sua atuação paralela em diversas regiões da imagem. Ao mesmo tempo, a IFT (Image Foresting Transform)

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Patil, Sreenivas. "Reconfigurable hardware for color space conversion /." Online version of thesis, 2008. http://hdl.handle.net/1850/7756.

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8

Souare, Moussa. "Sar Image Analysis In Wavelets Domain." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1405014006.

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9

Xu, Haifeng. "Digital Image Processing Algorithms Research Based on FPGA." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-91039.

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As we can find through the development of TV systems in America, the digital TV related digital broadcasting is just the road we would walk into. Nowadays digital television is prevailing in China, and the government is promoting the popularity of digital television. However, because of the economic development, analog television will still take its place in the TV market during a long period. But the broadcasting system has not been reformed, as a result, we should not only take use of the traditional analog system we already have, but also improve the quality of the pictures of analog system

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10

Heithecker, Sven. "Communication and memory scheduling in reconfigurable image processing systems." Berlin Dissertation.de, 2008. http://d-nb.info/994809271/04.

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11

Joginipelly, Arjun. "Implementation of Separable & Steerable Gaussian Smoothers on an FPGA." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/98.

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Smoothing filters have been extensively used for noise removal and image restoration. Directional filters are widely used in computer vision and image processing tasks such as motion analysis, edge detection, line parameter estimation and texture analysis. It is practically impossible to tune the filters to all possible positions and orientations in real time due to huge computation requirement. The efficient way is to design a few basis filters, and express the output of a directional filter as a weighted sum of the basis filter outputs. Directional filters having these properties are called

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12

Klingler, Randall S. "Compilation and Generation of Multi-Processor on a Chip Real-Time Embedded Systems." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1941.pdf.

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13

Morgan, Keith S. "SEU-Induced Persistent Error Propagation in FPGAs." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1377.pdf.

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14

Johnston, Christopher Troy. "VERTIPH : a visual environment for real-time image processing on hardware : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Computer Systems Engineering at Massey University, Palmerston North, New Zealand." Massey University, 2009. http://hdl.handle.net/10179/1219.

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This thesis presents VERTIPH, a visual programming language for the development of image processing algorithms on FPGA hardware. The research began with an examination of the whole design cycle, with a view to identifying requirements for implementing image processing on FPGAs. Based on this analysis, a design process was developed where a selected software algorithm is matched to a hardware architecture tailor made for its implementation. The algorithm and architecture are then transformed into an FPGA suitable design. It was found that in most cases the most efficient mapping for image proce

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15

Almeida, Carlos Caetano de 1976. "Arquitetura do módulo de convolução para visão computacional baseada em FPGA." [s.n.], 2015. http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

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Orientador: Eurípedes Guilherme de Oliveira Nóbrega<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica<br>Made available in DSpace on 2018-08-27T23:49:29Z (GMT). No. of bitstreams: 1 Almeida_CarlosCaetanode_M.pdf: 5316196 bytes, checksum: 8c3ec7a0c5709f2507df4dbc54c137b0 (MD5) Previous issue date: 2015<br>Resumo: Esta dissertação apresenta o estudo de uma arquitetura para o processamento digital de imagens, desenvolvido através de dispositivos de hardware programável, no caso FPGA, para a implementação eficiente no domínio do tempo do algoritmo da

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Tallawi, Reham. "FPGA-based Speed Limit Sign Detection." Master's thesis, Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-229018.

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This thesis presents a new hardware accelerated approach using image processing and detection algorithms for implementing fast and robust traffic sign detection system with focus on speed limit sign detection. The proposed system targets reconfigurable integrated circuits particularly Field Programmable Gate Array (FPGA) devices. This work propose a fully parallelized and pipelined parallel system architecture to exploit the high performance and flexibility capabilities of FPGA devices. This thesis is divided into two phases, the first phase, is a software prototype implementation of the propo

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17

Moeller, Tyler J. (Tyler John) 1975. "Field programmable gate arrays for radar front-end digital signal processing." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80555.

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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (p. 113-116).<br>by Tyler J. Moeller.<br>S.B.and M.Eng.

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18

Bäck, Carl. "Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments." Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-78738.

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FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histog

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19

Ortiz, Gual Fernando Enrique. "Novel reconfigurable computing architectures for embedded high performance signal processing and numerical applications." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 1.73 Mb., 102 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3221141.

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20

Johnson, Steven A. "Implementation of a configurable fault tolerant processor (CFTP)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Mar%5FJohnson.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2003.<br>Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 117). Also available online.

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21

Milojevic, Dragomir. "Implémentation des filtres non-linéaires de rang sur des architectures universelles et reconfigurables." Doctoral thesis, Universite Libre de Bruxelles, 2004. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/211147.

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Les filtres non-linéaires de rang sont souvent utilisés dans le but de rehausser la qualité d'une image numérique. Leur application permet de faciliter l'interprétation visuelle et la compréhension du contenu des images que ce soit pour un opérateur humain ou pour un traitement automatique ultérieur. Dans le pipeline d'une chaîne habituelle de traitement des images, ces filtres sont appliqués généralement dans la phase de pré-traitement, juste après l'acquisition et avant le traitement et l'analyse d'image proprement dit.<p>Les filtres de rang sont considérés comme un important goulot d'étrang

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22

Twigg, Christopher M. "Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11601.

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Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three gen

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23

Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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24

Ebert, Dean A. "Design and development of a configurable fault-tolerant processor (CFTP) for space applications." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Jun%5FEbert.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003.<br>Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 219-224). Also available online.

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Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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Chandrakar, Shant. "Memory Architecture Template for Fast Block Matching Algorithms on Field Programmable Gate Arrays." DigitalCommons@USU, 2009. https://digitalcommons.usu.edu/etd/495.

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Fast Block Matching (FBM) algorithms for video compression are well suited for acceleration using parallel data-path architectures on Field Programmable Gate Arrays (FPGAs). However, designing an efficient on-chip memory subsystem to provide the required throughput to this parallel data-path architecture is a complex problem. This thesis presents a memory architecture template that can be parameterized for a given FBM algorithm, number of parallel Processing Elements (PEs), and block size. The template can be parameterized with well known exploration techniques to design efficient on-chip memo

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27

Leonov, Maxim. "Method and implementation of multi-channel correlation in the hybrid CPU+FPGA system a thesis submitted to Auckland University of Technology in partial fulfilment of the requirements for the degree of Master of Engineering, 2009 /." Click here to access this resource online, 2008. http://hdl.handle.net/10292/678.

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28

Wunderlich, Richard Bryan. "Floating-gate-programmable and reconfigurable, digital and mixed-signal systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51815.

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This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, digital, and neuromorphic techniques to solving general problems. Typically, this is a very difficult task, and one that few attempt to undertake. However, when done right, solutions can be found with orders-of-magn

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29

Stevenson, Jeremy C. Duren Russell Walker Thompson Michael Wayne. "A comparison of field programmable gate arrays and digital signal processors in acoustic array processing." Waco, Tex. : Baylor University, 2006. http://hdl.handle.net/2104/4186.

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30

Bonamy, Robin. "Modélisation, exploration et estimation de la consommation pour les architectures hétérogènes reconfigurables dynamiquement." Phd thesis, Université Rennes 1, 2013. http://tel.archives-ouvertes.fr/tel-00931849.

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L'utilisation des accélérateurs reconfigurables, pour la conception de system-on-chip hétérogènes, offre des possibilités intéressantes d'augmentation des performances et de réduction de la consommation d'énergie. En effet, ces accélérateurs sont couramment utilisés en complément d'un (ou de plusieurs) processeur(s) pour permettre de décharger celui-ci (ceux-ci) des calculs intensifs et des traitements de flots de données. Le concept de reconfiguration dynamique, supporté par certains constructeurs de FPGA, permet d'envisager des systèmes beaucoup plus flexibles en offrant notamment la possibi

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31

Ng, Chiu-wa. "Bit-stream signal processing on FPGA." Click to view the E-thesis via HKUTO, 2009. http://sunzi.lib.hku.hk/hkuto/record/B41633842.

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32

Garcia, Lorca Federico. "Filtres récursifs temps réel pour la détection de contours : optimisations algorithmiques et architecturales." Paris 11, 1996. http://www.theses.fr/1996PA112439.

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Dans cette thèse on s'intéresse à deux aspects différents : conceptuel et réalisationel, sur lesquels portent les quatre innovations présentées. Si celles-ci sont illustrées par une application au détecteur de contours de Deriche, elles sont facilement généralisables à d'autres détecteurs qu'ils soient basés sur le calcul de maxima locaux de la dérivée première, ou le calcul des passages par zéro du laplacien. Les filtres à réponse impulsionnelle infinie symétriques ou anti-symétriques peuvent être réalisés sous forme cascade. Le filtre de lissage peut être défini par intégration numérique du

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33

Cholewa, Fabian [Verfasser]. "Time domain based image generation for synthetic aperture radar on field programmable gate arrays / Fabian Cholewa." Hannover : Gottfried Wilhelm Leibniz Universität Hannover, 2019. http://d-nb.info/1194158412/34.

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34

Catanzaro, Bryan C. "Higher radix floating-point representations for FPGA-based arithmetic /." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd808.pdf.

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Lillrose, Micah A. "High-speed data acquisition and FPGA detected pulse blanking system for interference mitigation in radio astronomy /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2076.pdf.

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36

McMurtrey, Daniel Lee. "Using duplication with compare for on-line error detection in FPGA-based designs /." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1642.pdf.

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Almeida, Manoel Aranda de. "Sistema embarcado reconfigurável de forma estática por programação genética utilizando hardware evolucionário híbrido." Universidade Federal de São Carlos, 2016. https://repositorio.ufscar.br/handle/ufscar/8000.

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Submitted by Izabel Franco (izabel-franco@ufscar.br) on 2016-10-03T18:47:50Z No. of bitstreams: 1 DissMAA.pdf: 3325891 bytes, checksum: 1b4744d48d74943990bed42753cc4b4c (MD5)<br>Approved for entry into archive by Marina Freitas (marinapf@ufscar.br) on 2016-10-20T18:27:58Z (GMT) No. of bitstreams: 1 DissMAA.pdf: 3325891 bytes, checksum: 1b4744d48d74943990bed42753cc4b4c (MD5)<br>Approved for entry into archive by Marina Freitas (marinapf@ufscar.br) on 2016-10-20T18:28:04Z (GMT) No. of bitstreams: 1 DissMAA.pdf: 3325891 bytes, checksum: 1b4744d48d74943990bed42753cc4b4c (MD5)<br>Made available

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Gunawardena, Sanjeev. "Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays." Ohio University / OhioLINK, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779.

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39

Raghavan, Anup Kumar. "JPG : a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe17691.pdf.

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Johannes, Michael T. "A fixed-point phase lock loop in a software defined radio." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2002. http://library.nps.navy.mil/uhtbin/hyperion-image/02sep%5FJohannes.pdf.

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41

Petre, Csaba. "Sim2spice a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits /." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31820.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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42

Simon, Wesley A. "Optimization of a cyclostationary signal processing algorithm using multiple field programmable gate arrays on the SRC-6 reconfigurable computer." Thesis, Monterey, California : Naval Postgraduate School, 2009. http://edocs.nps.edu/npspubs/scholarly/theses/2009/Sep/09Sep%5FSimon.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 2009.<br>Thesis Advisor(s): Fouts, Douglas J. ; Pace, Phillip E. "September 2009." Description based on title screen as viewed on November 6, 2009. Author(s) subject terms: SRC-6, reconfigurable computers, FPGA, cyclostationary processing, Time- Smoothing FFT Accumulation Method. Includes bibliographical references (p. 101-102). Also available in print.

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Alexander, Steven Wilson. "Efficient arithmetic for high speed DSP implementation on FPGAs." Thesis, Connect to e-thesis, 2007. http://theses.gla.ac.uk/856/.

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Thesis (Eng.D.) - University of Glasgow, 2007.<br>Eng.D. thesis submitted to the Faculty of Engineering, Department of Civil Engineering, University of Glasgow, 2007. Includes bibliographical references. Print version also available.

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Hulme, Charles A. "Testing and evaluation of the configurable fault tolerant processor (CFTP) for space-based application." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Dec%5FHulme.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003.<br>Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.

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Meyers, Tom. "UTILIZATION OF FIELD PROGRAMMABLE GATE ARRAYS AND DIGITAL SIGNAL PROCESSING MICROPROCESSORS IN AN ADVANCED PC TT&C SATCOM SYSTEM." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/606819.

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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>L-3 Communications Telemetry & Instrumentation (L-3 T&I) has developed an advanced IBM PC-AT Telemetry, Tracking, and Commanding (TT&C) SATCOM system based on the utilization of Field Programmable Gate Array / Digital Signal Processing (FPGA/DSP) microprocessors. This system includes up-link, down-link, and range processing sections. Physically, the system consists of one IF Transceiver and two or more FPGA/DSP microprocessor boards called Advanced Processing

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46

Nigania, Nimit. "FPGA prototyping of custom GPGPUs." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51966.

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Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping of general-purpose graphics processing units (GPGPUs) on field programmable gate arrays (FPGAs) using a novel tool chain. This hardware flow combined with the higher level simulation flow using the same source code allowed us to create a whole tool chain to study and build future architectures using new technologies. It also gave us enough flexibility at different granularities to make architectural decisions. We will also discuss

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Abramson, David. "A mite based translinear fpaa and its practical implementation." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26494.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam; Committee Member: Hamblen, James; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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48

Espenshade, Jeremy K. "Scalable framework for heterogeneous clustering of commodity FPGAs /." Online version of thesis, 2009. http://hdl.handle.net/1850/10765.

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Ng, Chiu-wa, and 吳潮華. "Bit-stream signal processing on FPGA." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2009. http://hub.hku.hk/bib/B41633842.

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50

Parthasarathy, Anand Kumar. "Feasibility analysis of FPGA based spindle motor controller." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2009.<br>Includes bibliographical references.

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