Relevant bibliographies by topics / Field programmable gate arrays. Programmable array logic. Computer engineering

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  2. Dissertations / Theses
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Academic literature on the topic 'Field programmable gate arrays. Programmable array logic. Computer engineering'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Field programmable gate arrays. Programmable array logic. Computer engineering"

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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.
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John, Lizy Kurian. "Memory Chips with Adjustable Configurations." VLSI Design 10, no. 2 (January 1, 1999): 203–15. http://dx.doi.org/10.1155/1999/62801.

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In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax⁡ can be constructed with the extra cost of Wmax⁡ – 1 pass gates, (Wmax⁡/2) 2-to-1 multiplexers, and ⌈log⁡2[log⁡2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.
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Wiśniewski, Remigiusz, Alexander Barkalov, Larisa Titarenko, and Wolfgang Halang. "Design of microprogrammed controllers to be implemented in FPGAs." International Journal of Applied Mathematics and Computer Science 21, no. 2 (June 1, 2011): 401–12. http://dx.doi.org/10.2478/v10006-011-0030-1.

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Design of microprogrammed controllers to be implemented in FPGAs In the article we propose a new design method for microprogrammed controllers. The traditional structure is improved by modifying internal modules and connections. Such a solution allows reducing the total number of logic elements needed for implementation in programmable structures, especially Field Programmable Gate Arrays (FPGAs). Detailed results of experiments show that on the average the application of the proposed methods yields up to 30% savings as far as the destination device is considered.
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Howard, Neil J., Andrew M. Tyrrell, and Nigel M. Allinson. "The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks." VLSI Design 4, no. 2 (January 1, 1996): 135–39. http://dx.doi.org/10.1155/1996/17505.

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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.
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Lu, Shyue-Kung, Fu-Min Yeh, and Jen-Sheng Shih. "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs." VLSI Design 15, no. 1 (January 1, 2002): 397–406. http://dx.doi.org/10.1080/1065514021000012011.

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In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.
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Wiedemann, Thomas, and Julian Spengler. "Gaussian Belief Propagation on a Field-Programmable Gate Array for Solving Linear Equation Systems." Electronics 10, no. 14 (July 15, 2021): 1695. http://dx.doi.org/10.3390/electronics10141695.

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Solving Linear Equation System (LESs) is a common problem in numerous fields of science. Even though the problem is well studied and powerful solvers are available nowadays, solving LES is still a bottleneck in many numerical applications concerning computation time. This issue especially pertains to applications in mobile robotics constrained by real-time requirements, where on-top power consumption and weight play an important role. This paper provides a general framework to approximately solve large LESs by Gaussian Belief Propagation (GaBP), which is extremely suitable for parallelization and implementation in hardware on a Field-Programmable Gate Array (FPGA). We derive the simple update rules of the Message Passing Algorithm for GaBP and show how to implement the approach efficiently on a System on a Programmable Chip (SoPC). In particular, multiple dedicated co-processors take care of recurring computations in GaBP. Exploiting multiple Direct Memory Access (DMA) controllers in scatter-gather mode and available arithmetic logic slices for numerical calculations accelerate the algorithm. Presented evaluations demonstrate that the approach does not only provide an accurate approximative solution of the LES. It also outperforms traditional solvers with respect to computation time for certain LESs.
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Cherepacha, Don, and David Lewis. "DP-FPGA: An FPGA Architecture Optimized for Datapaths." VLSI Design 4, no. 4 (January 1, 1996): 329–43. http://dx.doi.org/10.1155/1996/95942.

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This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.This paper discusses the requirements of logic blocks and routing structures that can be used to implement typical circuits containing a number of regularly structured datapaths of various sizes, as well as a small number of irregularities. It proposes a specific set of logic block architectures and analyzes it empirically. Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry skip circuit, a four-bit register with enable and direct input capabilities, and four three-state buffers. Further estimates of implementation area predict that the area of a design's datapath can be reduced by a factor of approximately two compared to a conventional FPGA through the use of programming bit sharing.
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Barkalov, Alexander, Larysa Titarenko, and Jacek Bieganowski. "Reduction in the number of LUT elements for control units with code sharing." International Journal of Applied Mathematics and Computer Science 20, no. 4 (December 1, 2010): 751–61. http://dx.doi.org/10.2478/v10006-010-0057-8.

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Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.
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Abdelazim, Sameh, David Santoro, Mark Arend, Fred Moshary, and Sam Ahmed. "A Hardware Implemented Autocorrelation Technique for Estimating Power Spectral Density for Processing Signals from a Doppler Wind Lidar System." Sensors 18, no. 12 (November 28, 2018): 4170. http://dx.doi.org/10.3390/s18124170.

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A signal processing technique utilizing autocorrelation of backscattered signals was designed and implemented in a 1.5 µm all-fiber wind sensing Coherent Doppler Lidar (CDL) system to preprocess atmospheric signals. The signal processing algorithm’s design and implementation are presented. The system employs a 20 kHz pulse repetition frequency (PRF) transmitter and samples the return signals at 400 MHz. The logic design of the autocorrelation algorithm was developed and programmed into a field programmable gate array (FPGA) located on a data acquisition board. The design generates and accumulates real time correlograms representing average autocorrelations of the Doppler shifted echo from a series of adjustable range gates. Accumulated correlograms are streamed to a host computer for subsequent processing to yield a line of sight wind velocity. Wind velocity estimates can be obtained under nominal aerosol loading and nominal atmospheric turbulence conditions for ranges up to 3 km.
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Lee, JunKyu, Gregory D. Peterson, Robert J. Harrison, and Robert J. Hinde. "Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators." VLSI Design 2010 (March 1, 2010): 1–11. http://dx.doi.org/10.1155/2010/930821.

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The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo π-estimator for the Cray XD1. The RC Monte Carlo π-estimator shows a 19.1× speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1. In this paper we describe the FPGA implementation for HASPRNG and a π-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.
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Dissertations / Theses on the topic "Field programmable gate arrays. Programmable array logic. Computer engineering"

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Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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Shen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.

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Van, Heerden Hein. "The design and testing of a superconducting programmable gate array." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1644.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.
This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design was assembled incorporating a routing architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final chip is presented and discussed followed by a discussion on testing. This thesis demonstrates the successful implementation of a fully functional reprogrammable logic device using RSFQ circuitry.
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Sudarsanam, Arvind. "Analysis of Field Programmable Gate Array-Based Kalman Filter Architectures." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/788.

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A Field Programmable Gate Array (FPGA)-based Polymorphic Faddeev Systolic Array (PolyFSA) architecture is proposed to accelerate an Extended Kalman Filter (EKF) algorithm. A system architecture comprising a software processor as the host processor, a hardware controller, a cache-based memory sub-system, and the proposed PolyFSA as co-processor, is presented. PolyFSA-based system architecture is implemented on a Xilinx Virtex 4 family of FPGAs. Results indicate significant speed-ups for the proposed architecture when compared against a space-based software processor. This dissertation proposes a comprehensive architecture analysis that is comprised of (i) error analysis, (ii) performance analysis, and (iii) area analysis. Results are presented in the form of 2-D pareto plots (area versus error, area versus time) and a 3-D plot (area versus time versus error). These plots indicate area savings obtained by varying any design constraints for the PolyFSA architecture. The proposed performance model can be reused to estimate the execution time of EKF on other conventional hardware architectures. In this dissertation, the performance of the proposed PolyFSA is compared against the performance of two conventional hardware architectures. The proposed architecture outperforms the other two in most test cases.
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Stevenson, Jeremy C. Duren Russell Walker Thompson Michael Wayne. "A comparison of field programmable gate arrays and digital signal processors in acoustic array processing." Waco, Tex. : Baylor University, 2006. http://hdl.handle.net/2104/4186.

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De, la Cruz Juan Alberto. "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays." DigitalCommons@USU, 2011. https://digitalcommons.usu.edu/etd/854.

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The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, with some additional resources used in the Field Programmable Gate Array (FPGA), a speed increase is obtained by using a one-dimensional Systolic Array (SA) approach. Additionally, extra guidelines are given for further research in this area.
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Wu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.

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The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require regular connection patterns in the netlists resulting from logic synthesis. This thesis presents a synthesis tree searching program PROMPT, which generates AND/EXOR tree circuits from given Boolean functions. Such circuits have the property that the gate structures are AND/EXOR ( A *B EB C ), AND and EXOR which could be realized by the CLI6000 cells. Also, the connection. way in the circuit is that usually the output of one level gate is the input of the next level gate of the tree. This matches ideally to the architecture of the CLI6000 bussing network where the macrocells have only connections to their neighboring cells. PROMPT is based on the Davio expansions ( an equivalent of the Shannon expansions for the EXOR gates ) as its Boolean decomposition methods. The program includes three versions: exact version, heuristic version and fixed-variable version. The exact version of PROMPT generates the Permuted Reed-Muller Tree circuit which has the minimum number of gates. Such tree circuit is obtained by searching through all possible combinations of the expansion variable orders to get the one which needs the least number of gates. The heuristic version of PROMPT is designed to decrease the time complexity of the search algorithm when dealing with logic functions having many input variables. It generates a Permuted Reed-Muller Tree which may not have the minimum number of gates. However, the tree searching time in this version decreases tremendously compared to the time necessary in the exact version. The fix-variable version is developed to generate Reed-Muller Tree circuits. Such circuits will have the same expansion variables at the same tree level, so they can be easier routed after the placement to the CLI6000 chips. In short, the program PROMPT generates the PRM and RM tree circuits which are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. Thus, the PRM and RM circuits can be easily placed and routed on the CLI6000 FPGAs.
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Kakkeroda, Anupriya. "Hardware Design And Certification Aspects Of A Field Programmable Gate Array-Based Terrain Database Integrity Monitor For A Synthetic Vision System." Ohio University / OhioLINK, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1102708816.

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Johnson, Darrel E. "Estimating the Dynamic Sensitive Cross Section of an FPGA Design through Fault injection." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd803.pdf.

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Tsui, Willie. "Hardware Implementation of Soft Computing Approaches for an Intelligent Wall-following Vehicle." Thesis, 2007. http://hdl.handle.net/10012/3053.

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Soft computing techniques are generally well-suited for vehicular control systems that are usually modeled by highly nonlinear differential equations and working in unstructured environment. To demonstrate their applicability, two intelligent controllers based upon fuzzy logic theories and neural network paradigms are designed for performing a wall-following task and an autonomous parking task. Based on performance and flexibility considerations, the two controllers are implemented onto a reconfigurable hardware platform, namely a Field Programmable Gate Array (FPGA). As the number of comparative studies of these two embedded controllers designed for the same application is limited in the literature, one of the main goals of this research work has been to evaluate and compare the two controllers in terms of hardware resource requirements, operational speeds and trajectory tracking errors in following different pre-defined trajectories. The main advantages and disadvantages of each of the controllers are presented and discussed in details. Challenging issues for implementation of the controllers on the FPGA platform are also highlighted. As the two controllers exhibit benefits and drawbacks under different circumstances, this research suggests as well a hybrid controller scheme as an attempt to integrate the benefits of both control units. To evaluate its performance, the hybrid controller is tested on the same pre-defined trajectories and the corresponding results are compared to that of the fuzzy logic and the neural network based controllers. For further demonstration of the capabilities of the wall-following controllers in other applications, the fuzzy logic and the neural network controllers are used in a parallel parking system. We see this work to be a stepping stone for further research work aiming at real world implementation of the controllers on Application Specified Integrated Circuit (ASIC) type of environment.
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Books on the topic "Field programmable gate arrays. Programmable array logic. Computer engineering"

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Murgai, Rajeev. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995.

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Kuon, Ian. FPGA architecture: Survey and challenges. Boston: Now Publishers, 2008.

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Samiha, Mourad, ed. Digital design using field programmable gate arrays. Englewood Cliffs, N.J: PTR Prentice Hall, 1994.

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1958-, Rose Jonathan Scott, and Marquardt Alexander, eds. Architecture and CAD for deep-submicron FPGAs. Boston: Kluwer Academic, 1999.

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1950-, Smailagic Asim, ed. Digital systems design and prototyping: Using field programmable logic and hardware description languages. 2nd ed. Boston: Kluwer Academic, 2000.

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Smith, Gina R. FPGAs: Everything you need to know to get started. Amsterdam: Newnes, 2010.

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FPGAs: Getting started. Amsterdam: Newnes, 2010.

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VHDL 101: Everything you need to know to get started. Oxford: Newnes/Elsevier, 2011.

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D, Furman Michael, ed. Rapid prototyping of digital systems. Boston: Kluwer Academic, 2000.

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D, Furman Michael, ed. Rapid prototyping of digital systems: A tutorial approach. 2nd ed. Boston: Kluwer Academic Publishers, 2001.

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Conference papers on the topic "Field programmable gate arrays. Programmable array logic. Computer engineering"

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Sayem, Abu Sadat Md, and Sajib Kumar Mitra. "Efficient approach to design low power reversible logic blocks for Field Programmable Gate Arrays." In 2011 IEEE International Conference on Computer Science and Automation Engineering (CSAE). IEEE, 2011. http://dx.doi.org/10.1109/csae.2011.5952845.

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Naito, Itsuki, Taisuke Koyamada, Keisuke Yamamoto, Kingo Igarashi, Hideo Harada, and Hirotsugu Suzuki. "Development of Instrumentation and Control Systems for UK ABWR." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-67866.

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This paper introduces the Instrumentation and Control (I&C) system for the proposed UK Advanced Boiling Water Reactor (UK ABWR) offered by Hitachi-GE Nuclear Energy, Ltd (Hitachi-GE). Hitachi-GE has been progressing the UK Generic Design Assessment (GDA) licensing process over the last 3 years. This is the process through which the Office for Nuclear Regulations (ONR) assesses the UK ABWR for suitability from a nuclear safety, security, environmental protection and waste management perspective and it is the first step towards proceeding with the construction phase in the UK. ONR’s regulatory expectations setting out relevant good practice are described in the Safety Assessment principles (SAPs), which are considered into the I&C design for UK ABWR. In addition, it has also been designed to take into account relevant good practices and regulations. In accordance with expectations derived from SAPs, the UK ABWR I&C systems are categorized and classified as required by IEC 61513 and IEC 61226. In addition, the overall I&C architecture, including all associated Human-Machine Interfaces (HMIs), abides by the principles independence and diversity of safety measures, segregation and separation of the protection and control systems. As a result, the UK ABWR I&C architecture is composed of major eight sub-systems. The eight sub-systems are: -Safety System Logic and Control system (SSLC) -Hardwired Backup System (HWBS) -Safety Auxiliary Control System (SACS) -Plant Control System (PCntlS) -Reactor/Turbine Auxiliary Control System (RTACS) -Plant Computer System (PCS) -Severe Accident Control and Instrumentation system (SA C&I) -Other dedicated C&I systems. The features for each sub-system such as redundancy of safety train or segregation among divisions are specified so that each sub-system will achieve its reliability as well as increase availability. While in the Japanese ABWR safety I&C system, the main protection system (SSLC), is microprocessor-based from the decades of successful operating experience in the past BWR, to meet the UK regulatory regime expectation on diversity between Class 1 platform and non-Class 1 platform, the SSLC (Class 1) for the UK ABWR is by Field Programmable Gate Array (FPGA). This system is currently under development and complies with IEC 62556. Its safety integrity level is planned to be SIL 3 (as a single division) and SIL 4 (as a four division system) as defined in IEC 61508. The HMIs which constitute an integral part of the I&C systems are also designed to comply with the I&C architecture regarding their categorization and classification with consideration of Human Factors (HF) modern methods taken into accounts.
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Harriman, Mark, Farbod Zorriassatine, Rob Parkin, Mike Jackson, and Jo Coy. "Application of FPGAs to High-Speed Condition Based Maintenance of Rolling Element Bearings." In ASME 7th Biennial Conference on Engineering Systems Design and Analysis. ASMEDC, 2004. http://dx.doi.org/10.1115/esda2004-58372.

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Field-Programmable Gate Array (FPGA) technology has been applied widely in electronic engineering and computing industries, but it has not had the same level of reception in other disciplines including mechanical engineering [1]. The purpose of this paper is to examine FPGA implementations of signal processing techniques that are used in the context of bearing condition monitoring. As the number of bearings can be large sparse sensor arrays are used to locate and detect their condition. The demands of realtime process monitoring [2] [3] can place a heavy burden upon the monitoring system. Field-Programmable Gate Array (FPGA) technology [4] in this application makes it possible to implement more sophisticated algorithms. These exploit its high-speed, parallel, reconfigurable architecture. Bring forth the advantages of FPGA technology to condition monitoring. The techniques covered are: cross-correlation, digital signal processing (DSP) Infinite Impulse Response (IIR) filters, neural networks and signature matching. The implemented designs are optimised for both execution time and the amount of logic area consumed. Results were obtained from each technique and were assessed and compared in terms of execution time and also the amount of logic consumed on the FPGA. Over the past 15 years FPGA technology has been applied extensively in electronic engineering but its scope has not been as vastly in mechanical engineering. The objective of this paper was to examine an application in mechanical engineering. Ideally this would be done with a mechanical engineering compatible approach, giving rise to a methodology, which would allow FPGA programming [5] to become a transferable skill.
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