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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.
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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.
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John, Lizy Kurian. "Memory Chips with Adjustable Configurations." VLSI Design 10, no. 2 (January 1, 1999): 203–15. http://dx.doi.org/10.1155/1999/62801.
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In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax can be constructed with the extra cost of Wmax – 1 pass gates, (Wmax/2) 2-to-1 multiplexers, and ⌈log2[log2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.
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Wiśniewski, Remigiusz, Alexander Barkalov, Larisa Titarenko, and Wolfgang Halang. "Design of microprogrammed controllers to be implemented in FPGAs." International Journal of Applied Mathematics and Computer Science 21, no. 2 (June 1, 2011): 401–12. http://dx.doi.org/10.2478/v10006-011-0030-1.
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Design of microprogrammed controllers to be implemented in FPGAs In the article we propose a new design method for microprogrammed controllers. The traditional structure is improved by modifying internal modules and connections. Such a solution allows reducing the total number of logic elements needed for implementation in programmable structures, especially Field Programmable Gate Arrays (FPGAs). Detailed results of experiments show that on the average the application of the proposed methods yields up to 30% savings as far as the destination device is considered.
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Howard, Neil J., Andrew M. Tyrrell, and Nigel M. Allinson. "The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks." VLSI Design 4, no. 2 (January 1, 1996): 135–39. http://dx.doi.org/10.1155/1996/17505.
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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.
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Lu, Shyue-Kung, Fu-Min Yeh, and Jen-Sheng Shih. "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs." VLSI Design 15, no. 1 (January 1, 2002): 397–406. http://dx.doi.org/10.1080/1065514021000012011.
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In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.
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Wiedemann, Thomas, and Julian Spengler. "Gaussian Belief Propagation on a Field-Programmable Gate Array for Solving Linear Equation Systems." Electronics 10, no. 14 (July 15, 2021): 1695. http://dx.doi.org/10.3390/electronics10141695.
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Solving Linear Equation System (LESs) is a common problem in numerous fields of science. Even though the problem is well studied and powerful solvers are available nowadays, solving LES is still a bottleneck in many numerical applications concerning computation time. This issue especially pertains to applications in mobile robotics constrained by real-time requirements, where on-top power consumption and weight play an important role. This paper provides a general framework to approximately solve large LESs by Gaussian Belief Propagation (GaBP), which is extremely suitable for parallelization and implementation in hardware on a Field-Programmable Gate Array (FPGA). We derive the simple update rules of the Message Passing Algorithm for GaBP and show how to implement the approach efficiently on a System on a Programmable Chip (SoPC). In particular, multiple dedicated co-processors take care of recurring computations in GaBP. Exploiting multiple Direct Memory Access (DMA) controllers in scatter-gather mode and available arithmetic logic slices for numerical calculations accelerate the algorithm. Presented evaluations demonstrate that the approach does not only provide an accurate approximative solution of the LES. It also outperforms traditional solvers with respect to computation time for certain LESs.
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Cherepacha, Don, and David Lewis. "DP-FPGA: An FPGA Architecture Optimized for Datapaths." VLSI Design 4, no. 4 (January 1, 1996): 329–43. http://dx.doi.org/10.1155/1996/95942.
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This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.This paper discusses the requirements of logic blocks and routing structures that can be used to implement typical circuits containing a number of regularly structured datapaths of various sizes, as well as a small number of irregularities. It proposes a specific set of logic block architectures and analyzes it empirically. Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry skip circuit, a four-bit register with enable and direct input capabilities, and four three-state buffers. Further estimates of implementation area predict that the area of a design's datapath can be reduced by a factor of approximately two compared to a conventional FPGA through the use of programming bit sharing.
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Barkalov, Alexander, Larysa Titarenko, and Jacek Bieganowski. "Reduction in the number of LUT elements for control units with code sharing." International Journal of Applied Mathematics and Computer Science 20, no. 4 (December 1, 2010): 751–61. http://dx.doi.org/10.2478/v10006-010-0057-8.
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Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.
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Abdelazim, Sameh, David Santoro, Mark Arend, Fred Moshary, and Sam Ahmed. "A Hardware Implemented Autocorrelation Technique for Estimating Power Spectral Density for Processing Signals from a Doppler Wind Lidar System." Sensors 18, no. 12 (November 28, 2018): 4170. http://dx.doi.org/10.3390/s18124170.
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A signal processing technique utilizing autocorrelation of backscattered signals was designed and implemented in a 1.5 µm all-fiber wind sensing Coherent Doppler Lidar (CDL) system to preprocess atmospheric signals. The signal processing algorithm’s design and implementation are presented. The system employs a 20 kHz pulse repetition frequency (PRF) transmitter and samples the return signals at 400 MHz. The logic design of the autocorrelation algorithm was developed and programmed into a field programmable gate array (FPGA) located on a data acquisition board. The design generates and accumulates real time correlograms representing average autocorrelations of the Doppler shifted echo from a series of adjustable range gates. Accumulated correlograms are streamed to a host computer for subsequent processing to yield a line of sight wind velocity. Wind velocity estimates can be obtained under nominal aerosol loading and nominal atmospheric turbulence conditions for ranges up to 3 km.
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Lee, JunKyu, Gregory D. Peterson, Robert J. Harrison, and Robert J. Hinde. "Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators." VLSI Design 2010 (March 1, 2010): 1–11. http://dx.doi.org/10.1155/2010/930821.
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The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo π-estimator for the Cray XD1. The RC Monte Carlo π-estimator shows a 19.1× speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1. In this paper we describe the FPGA implementation for HASPRNG and a π-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.
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Abdul Abbas, Huda M., Raad Farhood Chisab, and Mohannad Jabbar Mnati. "Monitoring and controlling the speed and direction of a DC motor through FPGA and comparison of FPGA for speed and performance optimization." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 5 (October 1, 2021): 3903. http://dx.doi.org/10.11591/ijece.v11i5.pp3903-3912.
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<span lang="EN-US">We are living in the 21<sup>st</sup> century, an era of acquiring necessity in one click. As we, all know that technology is continuously reviving to stay ahead of advancements taking place in this world of making things easier for mankind. Technology has been putting his part in introducing different projects as we have used the field programmable gate arrays (FPGAs) development board of low cost and programmable logic done by the new evolvable cyclone software is optimized for specific energy based on Altera Cyclone II (EP2C5T144) through which we can control the speed of any electronic device or any Motor Control IP product targeted for the fan and pump. Altera Cyclone FPGAs’ is a board through which we can monitor the speed and direction of the DC motor. As we know how to make understand, dynamic analog input using an A-to-D convertor and we know how to create pulse width modulation (PWM) output with FPGA. Therefore, by combining these two functions we can create an FPGA DC motor controller. Our paper is divided into three parts: First, all of us will attempt to imitate the issue and can try to look for its answer. Secondly, we will try to verify the solution for real-time. In addition, in the last step, we will verify the solution on the real-time measurements.</span>
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Rajapaksha, Nilanka, Amila Edirisuriya, Arjuna Madanayake, Renato J. Cintra, Dennis Onen, Ihab Amer, and Vassil S. Dimitrov. "Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA." Journal of Electrical and Computer Engineering 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/834793.
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Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65 nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained.
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Sharma, Poonam, Ashwani Kumar Dubey, and Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier." Recent Patents on Engineering 13, no. 2 (May 27, 2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.
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Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.
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Rashid, Muhammad, Sajjad Shaukat Jamal, Sikandar Zulqarnain Khan, Adel R. Alharbi, Amer Aljaedi, and Malik Imran. "Elliptic-Curve Crypto Processor for RFID Applications." Applied Sciences 11, no. 15 (July 31, 2021): 7079. http://dx.doi.org/10.3390/app11157079.
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This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.
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Döbrich, Stefan, and Christian Hochberger. "Low-Complexity Online Synthesis for AMIDAR Processors." International Journal of Reconfigurable Computing 2010 (2010): 1–15. http://dx.doi.org/10.1155/2010/953693.
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Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. Using this type of technology typically requires a lot of expert knowledge, which is not sufficiently available. Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. In this paper, we show that even a relative simplistic synthesis approach with low computational complexity can have a strong impact on the performance of compute intensive applications.
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Bartnykas, Kęstutis. "PROJECT DESIGN FOR COMPUTER ARCHITECTURE PRACTICAL SESSIONS BASED ON FIELD-PROGRAMMABLE GATE ARRAY." Mokslas - Lietuvos ateitis 13 (September 2, 2021): 1–5. http://dx.doi.org/10.3846/mla.2021.15184.
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Field-programmable logic arrays are often used in courses on computer architecture. The student must describe the processor with the external components necessary for its operation in the specified HDL (hardware description language) language according to the provided specification during a certain number of projects. The weakness of this approach is that the basis of such projects is a processor of one specific architecture, so the lecturer faces the issue of individualization of projects. This article proposes a solution based on dedicated processors instead of one programmable processor of a specific architecture. It’s shown here that the issue of project individualization is easier solvable in the proposed way, and it does not deviate from the theory of computer architecture, because the programmable processor is a generalization of a dedicated processor. The article describes project design ideas based on dedicated processors and gives some examples. Represented different instance than was applied during practical sessions of Computer Architecture that are held at the Department of Electronic Systems within VILNIUS TECH, i.e. certain modifications, and additions were applied.
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Mu`ñoz, Daniel M., Diego F. Sanchez, Carlos H. Llanos, and Mauricio Ayala-Rincón. "Tradeoff of FPGA Design of a Floating-point Library for Arithmetic Operators." Journal of Integrated Circuits and Systems 5, no. 1 (November 21, 2010): 42–52. http://dx.doi.org/10.29292/jics.v5i1.309.
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Many scientific and engineering applications require to perform a large number of arithmetic operations that must be computed in an efficient manner using a high precision and a large dynamic range. Commonly, these applications are implemented on personal computers taking advantage of the floating-point arithmetic to perform the computations and high operational frequencies. However, most common software architectures execute the instructions in a sequential way due to the von Neumann model and, consequently, several delays are introduced in the data transfer between the program memory and the Arithmetic Logic Unit (ALU). There are several mobile applications which require to operate with a high performance in terms of accuracy of the computations and execution time as well as with low power consumption. Modern Field Programmable Gate Arrays (FPGAs) are a suitable solution for high performance embedded applications given the flexibility of their architectures and their parallel capabilities, which allows the implementation of complex algorithms and performance improvements. This paper describes a parameterizable floating-point library for arithmetic operators based on FPGAs. A general architecture was implemented for addition/subtraction and multiplication and two different architectures based on the Goldschmidt’s and the Newton-Raphson algorithms were implemented for division and square root. Additionally, a tradeoff analysis of the hardware implementation was performed, which enables the designer to choose, for general purpose applications, the suitable bit-width representation and error associated, as well as the area cost, elapsed time and power consumption for each arithmetic operator. Synthesis results have demonstrated the effectiveness of the implemented cores on commercial FPGAs and showed that the most critical parameter is the dedicated Digital Signal Processing (DSP) slices consumption. Simulation results were addressed to compute the mean square error (MSE) and maximum absolute error demonstrating the correctness of the implemented floating-point library and achieving and experimental error analysis. The Newton-Raphson algorithm achieves similar MSE results as the Goldschmidt’s algorithm, operating with similar frequencies; however, the first one saves more logic area and dedicated DSP blocks.
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Vandendriessche, Jurgen, Bruno da Silva, Lancelot Lhoest, An Braeken, and Abdellah Touhafi. "M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera." Electronics 10, no. 3 (January 29, 2021): 317. http://dx.doi.org/10.3390/electronics10030317.
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Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints.
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Hamidi, Ibrahem M. T., and Farah S. H. Al-aassi. "High Speed FPGA Based 128-bit Advance Encryption Standard (AES)." International Journal of Sensors, Wireless Communications and Control 11 (February 1, 2021). http://dx.doi.org/10.2174/2210327911666210201104151.
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Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.
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Said, Ismail, and M. S. Çavuş. "ALU Design by VHDL Using FPGA Technology and Micro Learning in Engineering Education." British Journal of Computer, Networking and Information Technology, November 15, 2018, 1–18. http://dx.doi.org/10.52589/bjcnit/m4uwnh4j.
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The aim of this study is to develop case-study called Allowing Complexity to Complex Project (ACCP) for micro- learning in order to achieve high performance in computer architecture education and to test the legitimacy of classical teaching methods. The Arithmetic/Logic Unit (ALU) design was used as an example of the ACCP which consists of many examples and models aimed at developing students' skills in using complex arithmetic logical shifting and rotation instructions. Moreover, in this study, a real-world project on Field Programmable Gate Arrays (FPGA) devices was also developed using micro learning (ML). To this end, various hardware and software programs designed for computer architecture education and training were combined with improved instructional and attractive examples.
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Yap, Roderick, Kevin Lam, Rovi Bugayong, Edward Hernandez, and Joey De Guzman. "HARDWARE DESIGN AND IMPLEMENTATION OF GENETIC ALGORITHM FOR THE CONTROLLER OF A DC TO DC BOOST CONVERTER." Jurnal Teknologi 78, no. 5-7 (May 19, 2016). http://dx.doi.org/10.11113/jt.v78.8725.
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Controllers for DC to DC Boost Converters have evolved from simple control method to those that involve the use of fuzzy logic controllers. In many implementations, Proportional Integral Derivative (PID) controllers are commonly employed. In this paper, a genetic algorithm for tuning the PID controller of a DC to DC Boost Converter is hardware modelled and implemented on a Field Programmable Gate Array (FPGA) using Verilog as tool for the design entry. The goal of embedding genetic algorithm into the controller is to search for the best PID parameters that will yield fast settling time of the booster at an output of 6V. The hardware implementation allows the controller to tune itself by searching for the best Kp, Ki and Kd values that will give the best settling time. Significantly, this eliminates the need for a separate computer to do the searching routine. Test results of the circuit implemented yielded promising results. When compared to previous researches, the genetic algorithm employed yielded good PID parameters that resulted to a settling time as low as less than 60msec.
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Ahmed, Islam, Ahmed Nader Mohieldin, and Hassan Mostafa. "Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio." Journal of Circuits, Systems and Computers, August 19, 2020, 2150042. http://dx.doi.org/10.1142/s0218126621500420.
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Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle.
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Schumann, Johann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, and Corey Ippolito. "Towards Real-time, On-board, Hardware-supported Sensor and Software Health Management for Unmanned Aerial Systems." International Journal of Prognostics and Health Management 6, no. 1 (November 1, 2020). http://dx.doi.org/10.36001/ijphm.2015.v6i1.2243.
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For unmanned aerial systems (UAS) to be successfully deployed and integrated within the national airspace, it is imperative that they possess the capability to effectively complete their missions without compromising the safety of other aircraft, as well as persons and property on the ground. This necessity creates a natural requirement for UAS that can respondto uncertain environmental conditions and emergent failures in real-time, with robustness and resilience close enough to those of manned systems. We introduce a system that meets this requirement with the design of a real-time onboard system health management (SHM) capability to continuously monitor sensors, software, and hardware components. This system can detect and diagnose failures and violations of safety or performance rules during the flight of a UAS. Our approach to SHM is three-pronged, providing: (1) real-time monitoring of sensor and software signals; (2) signal analysis, preprocessing, and advanced on-the-fly temporal and Bayesian probabilistic fault diagnosis; and (3) an unobtrusive, lightweight, read-only, low-power realization using Field Programmable Gate Arrays (FPGAs) that avoids overburdening limited computing resources or costly re-certification of flight software. We call this approach rt-R2U2, a name derived from its requirements. Our implementation provides a novel approach of combining modular building blocks, integrating responsive runtime monitoring of temporal logic system safety requirements with model-based diagnosis and Bayesian network-based probabilistic analysis. We demonstrate this approach using actual flight data from theNASA Swift UAS.
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Nayak, Jayant Kumar, Vatsala Prasad, and Ranjan Ganguli. "A Field Programmable Gate Array (FPGA) Based Non-Linear Filters for Gas Turbine Prognostics." International Journal of Prognostics and Health Management 12, no. 3 (April 27, 2021). http://dx.doi.org/10.36001/ijphm.2021.v12i3.2960.
Full textAbstract:
The removal of noise from signals obtained through the health monitoring systems in gas turbines is an important consideration for accurate prognostics. Several filters have been designed and tested for this purpose, and their performance analysis has been conducted. Linear filters are inefficient in the removal of outliers and noise because they cause smoothening of the sharp features in the signal which can indicate the onset of a fault event. On the other hand, non-linear filters based on image processing methods can provide more precise results for gas turbine health signals. Among others, the weighted recursive median (WRM) filter has been shown to provide greater accuracy due to its weight adaptability depending on the signal type. However, sampling data at high rates is possible which needs hardware implementation of the filter. In this paper, the design, simulation and implementation of WRM filters on the FPGA (Field Programmable Gate Arrays) platforms Vivado Design Suite by Xilinx and Quartus Pro Lite Edition 19.3 has been performed. The architectural detail and performance result with the FPGA filters when subjected to abrupt and gradual fault signal is presented.