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Relevant bibliographies by topics / Field programmable gate arrays. System design. Computer architecture

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Academic literature on the topic 'Field programmable gate arrays. System design. Computer architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 9 February 2022

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Journal articles on the topic "Field programmable gate arrays. System design. Computer architecture"

1

Bartnykas, Kęstutis. "PROJECT DESIGN FOR COMPUTER ARCHITECTURE PRACTICAL SESSIONS BASED ON FIELD-PROGRAMMABLE GATE ARRAY." Mokslas - Lietuvos ateitis 13 (September 2, 2021): 1–5. http://dx.doi.org/10.3846/mla.2021.15184.

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Field-programmable logic arrays are often used in courses on computer architecture. The student must describe the processor with the external components necessary for its operation in the specified HDL (hardware description language) language according to the provided specification during a certain number of projects. The weakness of this approach is that the basis of such projects is a processor of one specific architecture, so the lecturer faces the issue of individualization of projects. This article proposes a solution based on dedicated processors instead of one programmable processor of

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VENKATESWARAN, N., S. PATTABIRAMAN, J. DESOUZA, et al. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 263–301. http://dx.doi.org/10.1142/s0218001495000134.

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The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable P

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Lee, Edmund, Guy Lemieux, and Shahriar Mirabbasi. "Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays." Journal of Signal Processing Systems 51, no. 1 (2007): 57–76. http://dx.doi.org/10.1007/s11265-007-0141-y.

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Leon, Vasileios, George Lentaris, Evangelos Petrongonas, et al. "Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC." ACM Transactions on Embedded Computing Systems 20, no. 3 (2021): 1–23. http://dx.doi.org/10.1145/3440885.

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The advent of powerful edge devices and AI algorithms has already revolutionized many terrestrial applications; however, for both technical and historical reasons, the space industry is still striving to adopt these key enabling technologies in new mission concepts. In this context, the current work evaluates an heterogeneous multi-core system-on-chip processor for use on-board future spacecraft to support novel, computationally demanding digital signal processors and AI functionalities. Given the importance of low power consumption in satellites, we consider the Intel Movidius Myriad2 system-

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Baskaran, S., L. Mubark Ali, A. Anitharani, E. Annal Sheeba Rani, and N. Nandhagopal. "Pupil Detection System Using Intensity Labeling Algorithm in Field Programmable Gate Array." Journal of Computational and Theoretical Nanoscience 17, no. 12 (2020): 5364–67. http://dx.doi.org/10.1166/jctn.2020.9429.

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Pupil detection techniques are an essential diagnostic technique in medical applications. Pupil detection becomes more complex because of the dynamic movement of the pupil region and it’s size. Eye-tracking is either the method of assessing the point of focus (where one sees) or the orientation of an eye relative to the head. An instrument used to control eye positions and eye activity is the eye tracker. As an input tool for human-computer interaction, eye trackers are used in research on the visual system, in psychology, psycholinguistics, marketing, and product design. Eye detection is one

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Figueiredo, Marco A., Clay S. Gloster, Mark Stephens, Corey A. Graves, and Mouna Nakkar. "Implementation of Multispectral Image Classification on a Remote Adaptive Computer." VLSI Design 10, no. 3 (2000): 307–19. http://dx.doi.org/10.1155/2000/31983.

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As the demand for higher performance computers for the processing of remote sensing science algorithms increases, the need to investigate new computing paradigms is justified. Field Programmable Gate Arrays enable the implementation of algorithms at the hardware gate level, leading to orders of magnitude performance increase over microprocessor based systems. The automatic classification of spaceborne multispectral images is an example of a computation intensive application that can benefit from implementation on an FPGA-based custom computing machine (adaptive or reconfigurable computer). A p

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Pasha, Muhammad Adeel, Umer Farooq, and Bilal Siddiqui. "A framework for high-level simulation and optimization of fine-grained reconfigurable architectures." SIMULATION 95, no. 8 (2018): 737–51. http://dx.doi.org/10.1177/0037549718796272.

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Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designin

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Nannipieri, Pietro, Stefano Di Matteo, Luca Baldanzi, et al. "True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA." Applied Sciences 11, no. 8 (2021): 3330. http://dx.doi.org/10.3390/app11083330.

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Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and prog

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Silva, Vítor, Paulo Pinto, Paulo Cardoso, Jorge Cabral, and Adriano Tavares. "HAL-ASOS Accelerator Model: Evolutive Elasticity by Design." Electronics 10, no. 17 (2021): 2078. http://dx.doi.org/10.3390/electronics10172078.

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To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class com

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Pilz, Sarah, Florian Porrmann, Martin Kaiser, Jens Hagemeyer, James M. Hogan, and Ulrich Rückert. "Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs." Algorithms 13, no. 2 (2020): 47. http://dx.doi.org/10.3390/a13020047.

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This paper is concerned with Field Programmable Gate Arrays (FPGA)-based systems for energy-efficient high-throughput string comparison. Modern applications which involve comparisons across large data sets—such as large sequence sets in molecular biology—are by their nature computationally intensive. In this work, we present a scalable FPGA-based system architecture to accelerate the comparison of binary strings. The current architecture supports arbitrary lengths in the range 16 to 2048-bit, covering a wide range of possible applications. In our example application, we consider DNA sequences

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Dissertations / Theses on the topic "Field programmable gate arrays. System design. Computer architecture"

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邢山震 and Shanzhen Xing. "A fundamental study on prototyping flexible computing systems." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1999. http://hub.hku.hk/bib/B31239547.

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Xing, Shanzhen. "A fundamental study on prototyping flexible computing systems /." Hong Kong : University of Hong Kong, 1999. http://sunzi.lib.hku.hk/hkuto/record.jsp?B20568356.

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Vyas, Dhaval N. "FPGA-based hardware accelerator design for performance improvement of a system-on-a-chip application." Diss., Online access via UMI:, 2005.

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Hilton, Clint Richard. "A Flexible Circuit-Switched Communication Network for FPGA-Based SOC Design." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd799.pdf.

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Ramineni, Narahari. "Tree Restructuring Approach to Mapping Problem in Cellular Architecture FPGAS." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4914.

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This thesis presents a new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs. We represent the netlist as the binary tree with decision variables associated with each node of the tree. The functionality of the tree nodes is chosen based on the target FPGA architecture. The proposed tree restructuring algorithms preserve local connectivity and allow direct mapping of the trees to the cellular array, thus eliminating the traditional routing phase. Also, predictability of the signal delays is a very important advantage of the developed approach. The developed

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Groom, Eddie L. "Ethernet controller design for an embedded system using FPGA technology." Birmingham, Ala. : University of Alabama at Birmingham, 2008. https://www.mhsl.uab.edu/dt/2008m/groom.pdf.

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Kakkeroda, Anupriya. "Hardware Design And Certification Aspects Of A Field Programmable Gate Array-Based Terrain Database Integrity Monitor For A Synthetic Vision System." Ohio University / OhioLINK, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1102708816.

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Al-Araje, Abdul-Nasser. "Micronetwork based system-on-FPGA (SOFPGA) architecture." Connect to resource, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1122609799.

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Mutigwe, Charles. "Automatic synthesis of application-specific processors." Thesis, Bloemfontein : Central University of Technology, Free State, 2012. http://hdl.handle.net/11462/163.

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Thesis (D. Tech. (Engineering: Electrical)) -- Central University of technology, Free State, 2012<br>This thesis describes a method for the automatic generation of appli- cation speci_c processors. The thesis was organized into three sepa- rate but interrelated studies, which together provide: a justi_cation for the method used, a theory that supports the method, and a soft- ware application that realizes the method. The _rst study looked at how modern day microprocessors utilize their hardware resources and it proposed a metric, called core density, for measuring the utilization rate. The co

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"High-level synthesis for dynamically reconfigurable systems." 1999. http://library.cuhk.edu.hk/record=b6073215.

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by Xue-jie Zhang.<br>"December 1999."<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 1999.<br>Includes bibliographical references (p. 144-[152]).<br>Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Mode of access: World Wide Web.<br>Abstracts in English and Chinese.

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Books on the topic "Field programmable gate arrays. System design. Computer architecture"

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George, Varghese. Low-Energy FPGAs - Architecture and Design. Springer US, 2001.

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Mohab, Anis, ed. Low-power design of nanometer FPGAs: Architecture and EDA. Morgan Kaufmann, 2010.

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1958-, Rose Jonathan Scott, and Marquardt Alexander, eds. Architecture and CAD for deep-submicron FPGAs. Kluwer Academic, 1999.

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F, Harding Benjamin, ed. Rapid system prototyping with FPGAs. Elsevier/Newnes, 2005.

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5

Kuon, Ian. FPGA architecture: Survey and challenges. Now Publishers, 2008.

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Nikhil, Rishiyur S. BSV by example: The next-generation language for electronic system design. Bluespec, 2010.

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7

Low-Energy FPGAs - Architecture and Design. Springer, 2011.

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8

Introduction To Embedded System Design Using Field Programmable Gate Arrays. Springer, 2008.

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Low-Energy FPGAs: Architecture and Design (The Springer International Series in Engineering and Computer Science). Springer, 2001.

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Betz, Vaughn, Alexander Marquardt, and Jonathan Rose. Architecture and Cad For Deep-Submicron Fpgas. Springer, 2012.

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Book chapters on the topic "Field programmable gate arrays. System design. Computer architecture"

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Sangiovanni-Vincentelli, Alberto. "Some considerations on Field Programmable Gate Arrays and their impact on system design." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/3-540-57091-8_26.

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Harb, Naim, Smail Niar, and Mazen A. R. Saghir. "Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6194-3.ch014.

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Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.

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Conference papers on the topic "Field programmable gate arrays. System design. Computer architecture"

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Jiang, Cindy X., Tom T. Hartley, and Joan E. Carletta. "High Performance Low Cost Implementation of FPGA-Based Fractional-Order Operators." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84796.

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Hardware implementation of fractional-order differentiators and integrators requires careful consideration of issues of system quality, hardware cost, and speed. This paper proposes using field programmable gate arrays (FPGAs) to implement fractional-order systems, and demonstrates the advantages that FPGAs provide. As an illustration, the fundamental operators to a real power is approximated via the binomial expansion of the backward difference. The resulting high-order FIR filter is implemented in a pipelined multiplierless architecture on a low-cost Spartan-3 FPGA. Unlike common digital imp

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Naito, Itsuki, Taisuke Koyamada, Keisuke Yamamoto, Kingo Igarashi, Hideo Harada, and Hirotsugu Suzuki. "Development of Instrumentation and Control Systems for UK ABWR." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-67866.

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This paper introduces the Instrumentation and Control (I&C) system for the proposed UK Advanced Boiling Water Reactor (UK ABWR) offered by Hitachi-GE Nuclear Energy, Ltd (Hitachi-GE). Hitachi-GE has been progressing the UK Generic Design Assessment (GDA) licensing process over the last 3 years. This is the process through which the Office for Nuclear Regulations (ONR) assesses the UK ABWR for suitability from a nuclear safety, security, environmental protection and waste management perspective and it is the first step towards proceeding with the construction phase in the UK. ONR’s regulato

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Kulic, Dana, and Elizabeth Croft. "Mechatronic System Integration for Senior Students." In ASME 2006 International Mechanical Engineering Congress and Exposition. ASMEDC, 2006. http://dx.doi.org/10.1115/imece2006-13761.

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This paper describes the design and implementation of a senior level course in mechatronic system integration for students completing a mechatronics engineering option in mechanical engineering. The course is designed to give students theoretical and practical experience with a large-scale mechatronic system, and a variety of control, sensing and actuating architectures. The lecture component of the course introduces students to large-scale project integration and interface design, as well as system architecture design. Students learn about alternative control hardware platforms commonly used

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Harriman, Mark, Farbod Zorriassatine, Rob Parkin, Mike Jackson, and Jo Coy. "Application of FPGAs to High-Speed Condition Based Maintenance of Rolling Element Bearings." In ASME 7th Biennial Conference on Engineering Systems Design and Analysis. ASMEDC, 2004. http://dx.doi.org/10.1115/esda2004-58372.

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Field-Programmable Gate Array (FPGA) technology has been applied widely in electronic engineering and computing industries, but it has not had the same level of reception in other disciplines including mechanical engineering [1]. The purpose of this paper is to examine FPGA implementations of signal processing techniques that are used in the context of bearing condition monitoring. As the number of bearings can be large sparse sensor arrays are used to locate and detect their condition. The demands of realtime process monitoring [2] [3] can place a heavy burden upon the monitoring system. Fiel

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