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Journal articles on the topic 'Field programmable gate arrays. System design. Computer architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 9 February 2022

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1

Bartnykas, Kęstutis. "PROJECT DESIGN FOR COMPUTER ARCHITECTURE PRACTICAL SESSIONS BASED ON FIELD-PROGRAMMABLE GATE ARRAY." Mokslas - Lietuvos ateitis 13 (September 2, 2021): 1–5. http://dx.doi.org/10.3846/mla.2021.15184.

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Field-programmable logic arrays are often used in courses on computer architecture. The student must describe the processor with the external components necessary for its operation in the specified HDL (hardware description language) language according to the provided specification during a certain number of projects. The weakness of this approach is that the basis of such projects is a processor of one specific architecture, so the lecturer faces the issue of individualization of projects. This article proposes a solution based on dedicated processors instead of one programmable processor of

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VENKATESWARAN, N., S. PATTABIRAMAN, J. DESOUZA, et al. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 263–301. http://dx.doi.org/10.1142/s0218001495000134.

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The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable P

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Lee, Edmund, Guy Lemieux, and Shahriar Mirabbasi. "Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays." Journal of Signal Processing Systems 51, no. 1 (2007): 57–76. http://dx.doi.org/10.1007/s11265-007-0141-y.

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Leon, Vasileios, George Lentaris, Evangelos Petrongonas, et al. "Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC." ACM Transactions on Embedded Computing Systems 20, no. 3 (2021): 1–23. http://dx.doi.org/10.1145/3440885.

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The advent of powerful edge devices and AI algorithms has already revolutionized many terrestrial applications; however, for both technical and historical reasons, the space industry is still striving to adopt these key enabling technologies in new mission concepts. In this context, the current work evaluates an heterogeneous multi-core system-on-chip processor for use on-board future spacecraft to support novel, computationally demanding digital signal processors and AI functionalities. Given the importance of low power consumption in satellites, we consider the Intel Movidius Myriad2 system-

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Baskaran, S., L. Mubark Ali, A. Anitharani, E. Annal Sheeba Rani, and N. Nandhagopal. "Pupil Detection System Using Intensity Labeling Algorithm in Field Programmable Gate Array." Journal of Computational and Theoretical Nanoscience 17, no. 12 (2020): 5364–67. http://dx.doi.org/10.1166/jctn.2020.9429.

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Pupil detection techniques are an essential diagnostic technique in medical applications. Pupil detection becomes more complex because of the dynamic movement of the pupil region and it’s size. Eye-tracking is either the method of assessing the point of focus (where one sees) or the orientation of an eye relative to the head. An instrument used to control eye positions and eye activity is the eye tracker. As an input tool for human-computer interaction, eye trackers are used in research on the visual system, in psychology, psycholinguistics, marketing, and product design. Eye detection is one

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Figueiredo, Marco A., Clay S. Gloster, Mark Stephens, Corey A. Graves, and Mouna Nakkar. "Implementation of Multispectral Image Classification on a Remote Adaptive Computer." VLSI Design 10, no. 3 (2000): 307–19. http://dx.doi.org/10.1155/2000/31983.

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As the demand for higher performance computers for the processing of remote sensing science algorithms increases, the need to investigate new computing paradigms is justified. Field Programmable Gate Arrays enable the implementation of algorithms at the hardware gate level, leading to orders of magnitude performance increase over microprocessor based systems. The automatic classification of spaceborne multispectral images is an example of a computation intensive application that can benefit from implementation on an FPGA-based custom computing machine (adaptive or reconfigurable computer). A p

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Pasha, Muhammad Adeel, Umer Farooq, and Bilal Siddiqui. "A framework for high-level simulation and optimization of fine-grained reconfigurable architectures." SIMULATION 95, no. 8 (2018): 737–51. http://dx.doi.org/10.1177/0037549718796272.

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Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designin

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Nannipieri, Pietro, Stefano Di Matteo, Luca Baldanzi, et al. "True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA." Applied Sciences 11, no. 8 (2021): 3330. http://dx.doi.org/10.3390/app11083330.

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Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and prog

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Silva, Vítor, Paulo Pinto, Paulo Cardoso, Jorge Cabral, and Adriano Tavares. "HAL-ASOS Accelerator Model: Evolutive Elasticity by Design." Electronics 10, no. 17 (2021): 2078. http://dx.doi.org/10.3390/electronics10172078.

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To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class com

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Pilz, Sarah, Florian Porrmann, Martin Kaiser, Jens Hagemeyer, James M. Hogan, and Ulrich Rückert. "Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs." Algorithms 13, no. 2 (2020): 47. http://dx.doi.org/10.3390/a13020047.

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This paper is concerned with Field Programmable Gate Arrays (FPGA)-based systems for energy-efficient high-throughput string comparison. Modern applications which involve comparisons across large data sets—such as large sequence sets in molecular biology—are by their nature computationally intensive. In this work, we present a scalable FPGA-based system architecture to accelerate the comparison of binary strings. The current architecture supports arbitrary lengths in the range 16 to 2048-bit, covering a wide range of possible applications. In our example application, we consider DNA sequences

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López-Valcárcel, Luis A., and Manuel García Sánchez. "A Wideband Radio Channel Sounder for Non-Stationary Channels: Design, Implementation and Testing." Electronics 10, no. 15 (2021): 1838. http://dx.doi.org/10.3390/electronics10151838.

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The increasing bandwidths and frequencies proposed for new mobile communications give rise to new challenges for system designers. Channel sounding and channel characterization are important tasks to provide useful information for the design of systems, protocols, and techniques to fight the propagation impairments. In this paper, we present a novel radio channel sounder capable of dealing with non-stationary channels. It can be operated in real-time and has a compact size to ease transport. For versatility and cost purposes, the core of the system is implemented in Field Programmable Gate Arr

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Yang, X., N. Wu, and J. H. Andrian. "Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure." VLSI Design 2017 (October 23, 2017): 1–7. http://dx.doi.org/10.1155/2017/4914301.

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This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.

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Deabes, Wael. "FPGA Implementation of ECT Digital System for Imaging Conductive Materials." Algorithms 12, no. 2 (2019): 28. http://dx.doi.org/10.3390/a12020028.

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This paper presents the hardware implementation of a stand-alone Electrical Capacitance Tomography (ECT) system employing a Field Programmable Gate Array (FPGA). The image reconstruction algorithms of the ECT system demand intensive computation and fast processing of large number of measurements. The inner product of large vectors is the core of the majority of these algorithms. Therefore, a reconfigurable segmented parallel inner product architecture for the parallel matrix multiplication is proposed. In addition, hardware-software codesign targeting FPGA System-On-Chip (SoC) is applied to ac

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Zamiri, Elyas, Alberto Sanchez, Marina Yushkova, Maria Sofia Martínez-García, and Angel de Castro. "Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters." Electronics 10, no. 8 (2021): 926. http://dx.doi.org/10.3390/electronics10080926.

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This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods

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Kumari, Cms Amrutha, and Syed Jahangir Badashah. "Image Edge Detection Using FPGA." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 1 (2013): 1192–200. http://dx.doi.org/10.24297/ijct.v10i1.3323.

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Medical imaging often involves the injection of contrast agents and subsequent analysis of tissue enhancement patterns. X-ray angiograms are projections of 3D reality into 2D representations, there is a fair amount of self occlusion among the vessels, hence one cannot extract the vessels directly using the image intensities or gradients (edge) alone. Vessels extraction from angiogram images is useful for blood vessels measurement and computer visualizations of the coronary artery. This project describes the algorithm for automatic segmentation of coronary arteries in digital X-ray projections

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Abbas, S. Syed Ameer, S. J. Thiruvengadam, and S. Susithra. "Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity." VLSI Design 2014 (June 5, 2014): 1–15. http://dx.doi.org/10.1155/2014/825183.

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Physical control format indicator channel (PCFICH) carries the control information about the number of orthogonal frequency division multiplexing (OFDM) symbols used for transmission of control information in long term evolution-advanced (LTE-A) downlink system. In this paper, two novel low complexity receiver architectures are proposed to implement the maximum likelihood- (ML-) based algorithm which decodes the CFI value in field programmable gate array (FPGA) at user equipment (UE). The performance of the proposed architectures is analyzed in terms of the timing cycles, operational resource

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Liu, Xianping, Xiaodong Ju, Wenxiao Qiao, et al. "Research on Test-bench for Sonic Logging Tool." Earth Sciences Research Journal 20, no. 1 (2016): 1–4. http://dx.doi.org/10.15446/esrj.v20n1.54141.

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<p>In this paper, the test-bench for sonic logging tool is proposed and designed to realize automatic calibration and testing of the sonic logging tool. The test-bench System consists of Host Computer, Embedded Controlling Board, and functional boards. The Host Computer serves as the Human Machine Interface (HMI) and processes uploaded data. The software running on Host Computer is designed on VC++, which is developed based on multithreading, Dynamic Linkable Library (DLL) and Multiple Document Interface (MDI) techniques. The Embedded Controlling Board uses ARM7 as the microcontroller an

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Walton, M., O. Ahmed, G. Grewal, and S. Areibi. "An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C." VLSI Design 2012 (February 1, 2012): 1–11. http://dx.doi.org/10.1155/2012/793196.

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Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard optimization problems. However, the time required to find high-quality solutions can become prohibitive as problem sizes grow. In this paper, we present a hardware implementation of Scatter Search on a field-programmable gate array (FPGA). Our objective is to improve the run time of Scatter Search by exploiting the potentially massive performance benefits that are available through the native parallelism in hardware. When implementing Scatter Search we employ two differen

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Siswoyo, Bambang, M. Agus Choiron, I. N. G. Wardana, and Yudy Surya Irawan. "Architectural System Design of Six Channels Compact Fuzzy Logic Controller for Arm Robot Joints Using FPGA Technology." Applied Mechanics and Materials 541-542 (March 2014): 1127–31. http://dx.doi.org/10.4028/www.scientific.net/amm.541-542.1127.

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The purpose of this study is to develop the architectural system design of the Six Channels Compact Fuzzy Logic Controller (SCC-FLC) ready to be embedded into the FPGA (Field Programmable Gate Array) for joints of arm robot's manipulator. The FPGA based system design of this study could controlled independently six servo of arm robot manipulators to reduce workload of computer system. The method of this study divided into four steps. The first step, the FLC-P (Fuzzy Logic Controller Processor) block module of single channel C-FLC (Compact Fuzzy Logic Controller) on the previous study is redesi

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Kumar S., Druva, and Roopa M. "Design and analysis of multiple read port techniques using bank division with XOR method for multi-ported-memory on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 6 (2021): 4785. http://dx.doi.org/10.11591/ijece.v11i6.pp4785-4793.

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<span lang="EN-US">The multiple read and write operations are performed simultaneously by multi-ported memories and are used in advanced digital design applications on reprogrammable field-programmable gate arrays (FPGAs) to achieve higher bandwidth. The Memory modules are configured by block RAM (BRAMs), which utilizes more area and power on FPGA. In this manuscript, the techniques to increase the read ports for multi-ported memory modules are designed using the bank division with XOR (BDX) approach. The read port techniques like two read-one write (2R1W) memory, hybrid mode approach ei

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N., Sridevi, and M. Meenakshi. "Efficient reconfigurable architecture for moving object detection with motion compensation." Indonesian Journal of Electrical Engineering and Computer Science 23, no. 2 (2021): 802. http://dx.doi.org/10.11591/ijeecs.v23.i2.pp802-810.

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The detection and tracking of object in large data surveillance requires a proper motion estimation and compensation techniques which are generally used to detect accurate movement from video stream. In this paper, a novel hardware level architecture involving motion detection, estimation, and compensation is proposed for real-time implementation. The motion vectors are obtained using 16×16 sub-blocks with a novel parallel D flip flop architecture in this work to arrive at an optimised architecture. The sum of absolute difference (SAD) is then calculated by optimized absolute difference and ad

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Davalos-Guzman, Ulises, Carlos E. Castañeda, Lina Maria Aguilar-Lobo, and Gilberto Ochoa-Ruiz. "Design and Implementation of a Real Time Control System for a 2DOF Robot Based on Recurrent High Order Neural Network Using a Hardware in the Loop Architecture." Applied Sciences 11, no. 3 (2021): 1154. http://dx.doi.org/10.3390/app11031154.

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In this paper, a real-time implementation of a sliding-mode control (SMC) in a hardware-in-loop architecture is presented for a robot with two degrees of freedom (2DOF). It is based on a discrete-time recurrent neural identification method, as well as the high performance obtained from the advantages of this architecture. The identification process uses a discrete-time recurrent high-order neural network (RHONN) trained with a modified extended Kalman filter (EKF) algorithm. This is a method for calculating the covariance matrices in the EKF algorithm, using a dynamic model with the associated

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Hanafy, Yasmin Adel, Maggie Mashaly, and Mohamed A. Abd El Ghany. "An Efficient Hardware Design for a Low-Latency Traffic Flow Prediction System Using an Online Neural Network." Electronics 10, no. 16 (2021): 1875. http://dx.doi.org/10.3390/electronics10161875.

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Neural networks are computing systems inspired by the biological neural networks in human brains. They are trained in a batch learning mode; hence, the whole training data should be ready before the training task. However, this is not applicable for many real-time applications where data arrive sequentially such as online topic-detection in social communities, traffic flow prediction, etc. In this paper, an efficient hardware implementation of a low-latency online neural network system is proposed for a traffic flow prediction application. The proposed model is implemented with different Machi

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Oh, Hyun Woo, Ji Kwang Kim, Gwan Beom Hwang, and Seung Eun Lee. "The Design of a 2D Graphics Accelerator for Embedded Systems." Electronics 10, no. 4 (2021): 469. http://dx.doi.org/10.3390/electronics10040469.

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Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variet

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Desai, Latika, and Suresh Mali. "Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding." VLSI Design 2018 (September 27, 2018): 1–8. http://dx.doi.org/10.1155/2018/4804729.

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Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms o

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Saber, Mohamed, and El-sayed M.El-Kenawy. "Design and implementation of accurate frequency estimator depend on deep learning." International Journal of Engineering & Technology 9, no. 2 (2020): 367. http://dx.doi.org/10.14419/ijet.v9i2.30473.

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An Accurate, efficient, and stable system to estimate the unknown input frequency of a sinusoidal signal is presented. The proposed design solves the main drawback of the existing phase-based estimator which called a derivative estimator depend on deep learning. These limitations are the inability to estimate low frequencies and the large estimation errors for the frequencies near the Nyquist rate. A Brief mathematical analysis in discrete-time of the proposed system is presented. Proposed estimator performance when the input is a single sinusoid, multiple sinusoids in the presence of additive

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Perri, Stefania, Cristian Sestito, Fanny Spagnolo, and Pasquale Corsonello. "Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip." Journal of Imaging 6, no. 9 (2020): 85. http://dx.doi.org/10.3390/jimaging6090085.

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Today, convolutional and deconvolutional neural network models are exceptionally popular thanks to the impressive accuracies they have been proven in several computer-vision applications. To speed up the overall tasks of these neural networks, purpose-designed accelerators are highly desirable. Unfortunately, the high computational complexity and the huge memory demand make the design of efficient hardware architectures, as well as their deployment in resource- and power-constrained embedded systems, still quite challenging. This paper presents a novel purpose-designed hardware accelerator to

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Dimopoulos, Alexandros C., Christos Pavlatos, and George Papakonstantinou. "Hardware Inexact Grammar Parser." International Journal of Pattern Recognition and Artificial Intelligence 31, no. 11 (2017): 1759025. http://dx.doi.org/10.1142/s021800141759025x.

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In this paper, a platform is presented, that given a Stochastic Context-Free Grammar (SCFG), automatically outputs the description of a parser in synthesizable Hardware Description Language (HDL) which can be downloaded in an FPGA (Field Programmable Gate Arrays) board. Although the proposed methodology can be used for various inexact models, the probabilistic model is analyzed in detail and the extension to other inexact schemes is described. Context-Free Grammars (CFG) are augmented with attributes which represent the probability values. Initially, a methodology is proposed based on the fact

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Magyari, Alexander, and Yuhua Chen. "FPGA Remote Laboratory Using IoT Approaches." Electronics 10, no. 18 (2021): 2229. http://dx.doi.org/10.3390/electronics10182229.

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Field-Programmable Gate Arrays (FPGAs) are relatively high-end devices that are not easily shared between multiple users. In this work, we achieved a remotely accessible FPGA framework using accessible Internet of Things (IoT) approaches. We sought to develop a method for students to receive the same level of educational quality in a remote environment that they would receive in a typical, in-person course structure for a university-level digital design course. Keeping cost in mind, we are able to combine the functionality of an entry-level FPGA and a Raspberry Pi Zero to provide IoT access fo

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Liu, Hailiang, Jiade Cheng, and Asnidar Hanim Yusuf. "Design of Light Emitting Diodes (LEDs) Lighting System and Its Application in Garden Landscape Decoration." Journal of Nanoelectronics and Optoelectronics 15, no. 6 (2020): 734–42. http://dx.doi.org/10.1166/jno.2020.2793.

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Light Emitting Diode (LED) is widely used in garden landscape decoration because of its small size, low power, concentrated light, and the capability of showing more vivid colors. While designing the LED lighting system, considering that a single Advanced RISC Machine (ARM)-based control system cannot achieve large-scale LED display, and a single Field Programmable Gate Array (FPGA)-based control system cannot control the lighting system well, an LED system with the combination of ARM processor-FPGA is proposed. In this system, the ARM processor is used as the major control component. The Linu

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Nascimento, Maikon, Jing Li, and Dileepan Joseph. "Efficient Pipelined Circuits for Histogram-based Tone Mapping of Nonlinear CMOS Image Sensors." Journal of Imaging Science and Technology 65, no. 4 (2021): 40503–1. http://dx.doi.org/10.2352/j.imagingsci.technol.2021.65.4.040503.

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Abstract Tone mapping is extensively researched to address the issue of displaying high dynamic range (DR) scenes on low DR displays. Even though several tone-mapping operators (TMOs) exist, not all are designed for hard real time. The operator has to be capable of scaling up the spatial resolution without compromising the frame rate. The implementation of a TMO should also be simple enough to embed in low-cost platforms for imaging systems. A computationally efficient, and well accepted, class of TMOs are global ones based on histograms. This work presents a method to implement TMOs that use

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Ramadurgam, Srikanth, and Darshika G. Perera. "An Efficient FPGA-Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms." Electronics 10, no. 11 (2021): 1323. http://dx.doi.org/10.3390/electronics10111323.

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Machine learning is becoming the cornerstones of smart and autonomous systems. Machine learning algorithms can be categorized into supervised learning (classification) and unsupervised learning (clustering). Among many classification algorithms, the Support Vector Machine (SVM) classifier is one of the most commonly used machine learning algorithms. By incorporating convex optimization techniques into the SVM classifier, we can further enhance the accuracy and classification process of the SVM by finding the optimal solution. Many machine learning algorithms, including SVM classification, are

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Wang, Guoqing, He Chen, and Yizhuang Xie. "An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing." Electronics 10, no. 6 (2021): 662. http://dx.doi.org/10.3390/electronics10060662.

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With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Ga

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Cirugeda-Roldán, Eva M., María Sofía Martínez-García, Alberto Sanchez, and Angel de Castro. "Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx." Electronics 10, no. 16 (2021): 1952. http://dx.doi.org/10.3390/electronics10161952.

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Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for th

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Tian, Haowen, Shixu Guo, Peng Zhao, Minyu Gong, and Chao Shen. "Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP." Sensors 21, no. 4 (2021): 1425. http://dx.doi.org/10.3390/s21041425.

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Aiming at addressing the contradiction between the high-speed real-time positioning and multi-channel signal processing in multi-beam sonar systems, in this work we present a real-time multi-beam sonar system based on a Field Programmable Gate Array (FPGA) and Digital Signal Processing (DSP) from two perspectives, i.e., hardware implementation and software optimization. In terms of hardware, an efficient high-voltage pulse transmitting module and a multi-channel data acquisition module with time versus gain (TVG) compensation with characteristics such as low noise and high phase amplitude cons

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Chi, Tao, and Ming Chen. "Interconnection algorithm of a wide range of pervasive devices for the Internet of things." International Journal of Distributed Sensor Networks 14, no. 1 (2018): 155014771875601. http://dx.doi.org/10.1177/1550147718756014.

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With the rapid development of wireless communications for network of things, more and more models for such networks-on-chip architectures have been created and used in a wide range of applications. In this article, the behaviors of wireless communications for such networks-on-chip architectures are analyzed at two layers. The physical layer behaviors consist of what frequency is used, how and when signals are transmitted, and how transceivers’ responses are decoded. The medium access control layer behavior consists of how to provide a reliable link between two peer medium access control entiti

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Bhatia, Dinesh. "Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

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Park, Chester Sungchung, Sunwoo Kim, Jooho Wang, and Sungkyung Park. "Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation." Electronics 10, no. 3 (2021): 231. http://dx.doi.org/10.3390/electronics10030231.

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A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded in

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Vidhyapathi, C. M., Alex Noel Joseph Raj, and S. Sundar. "The 3D-DTW Custom IP based FPGA Hardware Acceleration for Action Recognition." Journal of Imaging Science and Technology 65, no. 1 (2021): 10401–1. http://dx.doi.org/10.2352/j.imagingsci.technol.2021.65.1.010401.

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Abstract This article proposes an implementation of an action recognition system, which allows the user to perform operations in real time. The Microsoft Kinect (RGB-D) sensor plays a central role in this system, which provides the skeletal joint information of humans directly. Computationally efficient skeletal joint position features are considered for describing each action. The dynamic time warping algorithm (DTW) is a widely used algorithm in many applications such as similarity sequence search, classification, and speech recognition. It provides the highest accuracy compared to all other

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Charitopoulos, George, Dionisios N. Pnevmatikatos, and Georgi Gaydadjiev. "MC-DeF." ACM Transactions on Architecture and Code Optimization 18, no. 3 (2021): 1–25. http://dx.doi.org/10.1145/3447970.

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Executing complex scientific applications on Coarse-Grain Reconfigurable Arrays ( CGRAs ) promises improvements in execution time and/or energy consumption compared to optimized software implementations or even fully customized hardware solutions. Typical CGRA architectures contain of multiple instances of the same compute module that consist of simple and general hardware units such as ALUs, simple processors. However, generality in the cell contents, while convenient for serving a wide variety of applications, penalizes performance and energy efficiency. To that end, a few proposed CGRAs use

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Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam, and Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays." International Journal of Handheld Computing Research 7, no. 4 (2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation

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Bhatia, Dinesh, and Amit Chowdhary. "A Multi-Terminal Net Router for Field-Programmable Gate Arrays." VLSI Design 4, no. 1 (1996): 1–10. http://dx.doi.org/10.1155/1996/79127.

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This paper presents a router for routing multi-terminal nets in field-programmable gate arrays (FPGAs). The router does not require pre-assignment of routing channels, a phase that is normally accomplished during global routing. This direct routing approach greatly enhances the probability of routing (routability). The multi-terminal routing greatly reduces the total wire length as it approximates a Steiner tree. The total number of segments required to route the circuits is usually less as compared to other routing approaches. The router has generated excellent routing results for some indust

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CROSBIE, ROY. "USING FIELD-PROGRAMMABLE GATE ARRAYS FOR HIGH-SPEED REAL-TIME SIMULATION." International Journal of Modeling, Simulation, and Scientific Computing 01, no. 01 (2010): 99–115. http://dx.doi.org/10.1142/s1793962310000031.

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Some applications of real-time simulation now require frame times that are shorter in duration than can be delivered by traditional methods such as real-time versions of Linux (RT-Linux). RT-Linux can be satisfactory for frames as short as 10μS, but there is now a need, for example in the simulation of power-electronic systems, for frame times as short as 1 μS or even less. Techniques based on the interfacing of digital signal processors (DSPs) to a Windows PC have achieved a 2 μS frame time for a typical power electronics application and less than 1 μS is shown to be possible using field-prog

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Simpkins, Alex. "Introduction to Embedded System Design Using Field Programmable Gate Arrays [On the Shelf]." IEEE Robotics & Automation Magazine 20, no. 4 (2013): 163–64. http://dx.doi.org/10.1109/mra.2013.2283188.

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John, Lizy Kurian. "Memory Chips with Adjustable Configurations." VLSI Design 10, no. 2 (1999): 203–15. http://dx.doi.org/10.1155/1999/62801.

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In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on th

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Brown, Stephen, Muhammad Khellah, and Guy Lemieux. "Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (1996): 275–91. http://dx.doi.org/10.1155/1996/45983.

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This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed rout

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Juang, Ying-Shen, Lu-Ting Ko, Jwu-E. Chen, Tze-Yun Sung, and Hsi-Chin Hsin. "Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems." Computational and Mathematical Methods in Medicine 2012 (2012): 1–9. http://dx.doi.org/10.1155/2012/651564.

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Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline data path has advantages of high data rate, high precision, high performance, and less hardware cost. The design procedure with performance and hardware analysis for optimization has also been given. It i

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Howard, Neil J., Andrew M. Tyrrell, and Nigel M. Allinson. "The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks." VLSI Design 4, no. 2 (1996): 135–39. http://dx.doi.org/10.1155/1996/17505.

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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.

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Allani, Mohamed Yassine, Jamel Riahi, Silvano Vergura, and Abdelkader Mami. "FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load." Energies 14, no. 8 (2021): 2108. http://dx.doi.org/10.3390/en14082108.

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The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the syste

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ROSENDAHL, G. K., R. D. MCLEOD, and H. C. CARD. "A DSP–FPGA-BASED RECONFIGURABLE COMPUTER." Journal of Circuits, Systems and Computers 08, no. 04 (1998): 453–59. http://dx.doi.org/10.1142/s0218126698000250.

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In order to exploit architectural advantages associated with specific computations while at the same time having flexibility in those computations, we have designed a reconfigurable parallel machine architecture. A prototype reconfigurable computer has been constructed based on digital signal processing (DSP) chips and field-programmable gate arrays (FPGAs). Communications are based upon a broadcast network that employs FPGA-based message pre-processing and post-processing. Tradeoffs between computational and communication performance are made possible by software reconfiguration of the FPGAs.

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