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Wunderlich, Richard Bryan. "Floating-gate-programmable and reconfigurable, digital and mixed-signal systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51815.
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This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, digital, and neuromorphic techniques to solving general problems. Typically, this is a very difficult task, and one that few attempt to undertake. However, when done right, solutions can be found with orders-of-magnitude improvement over existing solutions restricted to using only one type computational domain. To that end, I have helped build large and complicated reconfigurable systems (and software tools for helping to use these systems) capable of implementing solutions to problems in all three of those domains simultaneously. These systems are used to explore and implement these cross domain solutions to difficult problems. The earlier work was involved with simply applying floating-gate technology to improving the building blocks of digital systems. Through that early work a new logic family built from floating-gate transistors was discovered, a Logical Effort compatible power analysis technique was developed, and low power floating-gate based FPGA was implemented. This work was then merged with existing research in the group involving solving problems using reconfigurable analog, and neuromorphic techniques. Thus converging on the mentioned systems that allow one to solve problems using techniques from all three domains: analog, neuromorphic, and digital.
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Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Nease, Stephen H. "Neural and analog computation on reconfigurable mixed-signal platforms." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53999.
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This work addresses neural and analog computation on reconfigurable mixed-signal platforms.
Many engineered systems could gain tremendous benefits by emulating neural systems.
For example, neural systems are incredibly power efficient and fault-tolerant.
They are also capable of types of computation that we cannot yet match with conventional computers.
Neuromorphic engineers typically implement neural computation using analog circuits because they are low-power and naturally model some aspects of neurobiology.
One problem with analog circuits is that they are typically inflexible.
To address this shortcoming, our lab has developed reconfigurable analog systems known as Field Programmable Analog Arrays (FPAAs).
This dissertation consists of two main parts.
The first is the implementation of neural and analog circuits on FPAAs.
We first implemented an adaptive winner-take-all circuit, which could model attention in neural systems.
Next, we modeled the dendrite, which is the conductive tissue that relays inputs from synapses to the neuron cell body.
We also implemented a subtractive music synthesizer, perhaps providing the electronic music synthesis community with a good platform for experimentation.
Finally, we conducted a number of neural learning experiments on a neuromorphic platform.
The second part of this dissertation includes design aspects of new FPAAs, including configurable blocks that can be used as current-mode DACs in a digitally-enhanced FPAA, the RASP 2.9v.
We also consider the design of a new neuromorphic platform containing 256 neurons and over 200,000 synapses, many with learning capability.
We also created an active delay line that could be used for beamforming or FIR filter applications.
In summary, this work adds to the field of reconfigurable systems by both showing how to implement circuits with them and creating new systems based on lessons learned while working with previous systems.
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Ortiz, Gual Fernando Enrique. "Novel reconfigurable computing architectures for embedded high performance signal processing and numerical applications." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 1.73 Mb., 102 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3221141.
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Moeller, Tyler J. (Tyler John) 1975. "Field programmable gate arrays for radar front-end digital signal processing." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80555.
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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (p. 113-116).
by Tyler J. Moeller.
S.B.and M.Eng.
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Stevenson, Jeremy C. Duren Russell Walker Thompson Michael Wayne. "A comparison of field programmable gate arrays and digital signal processors in acoustic array processing." Waco, Tex. : Baylor University, 2006. http://hdl.handle.net/2104/4186.
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Alaqeeli, Abdulqadir A. "Global Positioning System signal acquisition and tracking using field programmable gate arrays." Ohio : Ohio University, 2002. http://www.ohiolink.edu/etd/view.cgi?ohiou1178735512.
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Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.
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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment.
Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques.
These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented
in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic
architecture.
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Hooper, Mark S. "Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-12032004-155022/unrestricted/Hooper%5FMark%5FS%5F200505%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.
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Twigg, Christopher M. "Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11601.
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Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).
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Leonov, Maxim. "Method and implementation of multi-channel correlation in the hybrid CPU+FPGA system a thesis submitted to Auckland University of Technology in partial fulfilment of the requirements for the degree of Master of Engineering, 2009 /." Click here to access this resource online, 2008. http://hdl.handle.net/10292/678.
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Ng, Chiu-wa. "Bit-stream signal processing on FPGA." Click to view the E-thesis via HKUTO, 2009. http://sunzi.lib.hku.hk/hkuto/record/B41633842.
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GANESAN, SREELAKSHMI. "SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041.
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Abramson, David. "A mite based translinear fpaa and its practical implementation." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26494.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam; Committee Member: Hamblen, James; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Petre, Csaba. "Sim2spice a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits /." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31820.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Alexander, Steven Wilson. "Efficient arithmetic for high speed DSP implementation on FPGAs." Thesis, Connect to e-thesis, 2007. http://theses.gla.ac.uk/856/.
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Thesis (Eng.D.) - University of Glasgow, 2007.Eng.D. thesis submitted to the Faculty of Engineering, Department of Civil Engineering, University of Glasgow, 2007. Includes bibliographical references. Print version also available.
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Ng, Chiu-wa, and 吳潮華. "Bit-stream signal processing on FPGA." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2009. http://hub.hku.hk/bib/B41633842.
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Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.
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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.
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Simon, Wesley A. "Optimization of a cyclostationary signal processing algorithm using multiple field programmable gate arrays on the SRC-6 reconfigurable computer." Thesis, Monterey, California : Naval Postgraduate School, 2009. http://edocs.nps.edu/npspubs/scholarly/theses/2009/Sep/09Sep%5FSimon.pdf.
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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 2009.Thesis Advisor(s): Fouts, Douglas J. ; Pace, Phillip E. "September 2009." Description based on title screen as viewed on November 6, 2009. Author(s) subject terms: SRC-6, reconfigurable computers, FPGA, cyclostationary processing, Time- Smoothing FFT Accumulation Method. Includes bibliographical references (p. 101-102). Also available in print.
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Manoranjan, Jotham Vaddaboina. "Relative timing based verification and design with delay insensitive signal path modeling with application for field programmable gate arrays." Thesis, The University of Utah, 2017. http://pqdtopen.proquest.com/#viewpdf?dispub=10272453.
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The relative timing (RT) based asynchronous design methodology has been successfully used to create application specific integrated circuit (ASIC) designs that are a process generation ahead of their synchronous counterparts in terms of power, performance and energy. However, while the implementation of RT asynchronous circuits has been dealt with successfully in the ASIC domain, there has been limited exploration of utilizing the design methodology on field programmable gate arrays (FPGAs). This dissertation seeks to address the challenges in implementing RT asynchronous circuits on FPGAs. Relative Timing uses path-based timing constraints to guarantee that a circuit conforms to its behavioral specification. A methodology for the design of glitch free burstmode asynchronous controllers on FPGAs is presented. Path based timing constraints are implement to ensure circuit functionality. A flow for the modeling of the circuit, extraction of relative timing constraints, and implementation of the extracted constraints is presented. Optimizations that enable faster implementation and more robust designs are discussed. The dissertation also presents a framework to evaluate and rank relative timing constraint sets for a given circuit. Multiple constraint sets are possible for a single circuit. The constraint sets are evaluated on the basis of robustness of the constraints and conflicts between constraints in the same set. The methodology is used to optimize the extraction of relative timing constraints. An FPGA architecture capable of relative timing based digital implementations is designed. Modifications are made to a traditional synchronous FPGA architecture to make it asynchronous capable, while retaining its capability as a fully functional synchronous FPGA. A Microprocessor without Interlocked Pipeline Stages (MIPS) design is used to test the FPGA. A performance improvement of 1.7x and a power improvement of 2.3x is achieved. Furthermore, a novel reconfigurable circuit capable of implementing the entire family of 2-phase and 4-phase latch protocols is presented. The circuit is implemented on the International Business Machine Artisan 65nm node and its performance is compared with implementations on a Xilinx Virtex-5 chip that is manufactured on a similar node. A 4x improvement in speed and 2.7x improvement in energy per cycle is achieved.
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Meyers, Tom. "UTILIZATION OF FIELD PROGRAMMABLE GATE ARRAYS AND DIGITAL SIGNAL PROCESSING MICROPROCESSORS IN AN ADVANCED PC TT&C SATCOM SYSTEM." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/606819.
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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, NevadaL-3 Communications Telemetry & Instrumentation (L-3 T&I) has developed an advanced IBM PC-AT Telemetry, Tracking, and Commanding (TT&C) SATCOM system based on the utilization of Field Programmable Gate Array / Digital Signal Processing (FPGA/DSP) microprocessors. This system includes up-link, down-link, and range processing sections. Physically, the system consists of one IF Transceiver and two or more FPGA/DSP microprocessor boards called Advanced Processing Microprocessors (APMs). The form factor of these PWBs is compliant with full length, full height IBM PC PCI bus cards. This paper describes the features and functionality of an advanced Telemetry, Tracking, and Commanding Processing System (TT&CPS) based on the implementation of FPGA and DSP microprocessors. The high-level functional attributes of the TT&CPS are depicted in Figure 1. There are four main functional blocks: the IF Transceiver, the Down-Link Processing Section, the Up-Link Processing Section, and the Range Processor. The analog/IF circuitry in the IF Transceiver card interfaces between the 68–72 MHz (70 MHz, nominal) IF I/O signals and the Up-Link and Down-Link Processing Section's DSP equipment. The down-link portion of the IF Transceiver card has two user-selected input ports. From the selected input, the signal is processed through selectable bandwidth limiting, gain control, Doppler correction (optional), quadrature down-conversion to zero hertz (baseband), selectable baseband filtering, and precision Analog-to-Digital (A/D) conversion. The up-link portion of the IF Transceiver card takes I/Q digital data from the APM performing the up-link processing functions. This baseband I/Q digital data is Digital-to-Analog (D/A) converted, filtered, quadrature up-converted to 68–72 MHz, up-link Doppler corrected (optional), output level detected and level controlled, and sent to a two-position output selector switch. The down-link portion of the TT&CPS provides main carrier linear PM or BPSK or QPSK demodulation and can also, in composite linear PM demodulation mode, receive and demodulate FSK and/or BPSK subcarriers and ranging signals. The demodulators use symbol timing loops and bit decision circuits (matched filters) to perform the bit synchronization function. Several decoding algorithms, including differential, de-interleaving, Viterbi, and Reed-Solomon, are available for the down-link telemetry. Command format checking and CRC status is also available on FSK-demodulated data. Direct carrier BPSK/QPSK demodulation has decoding and frame synchronization capabilities. Because of the modular construction of the firmware and the use of FPGAs and DSPs, the system can be loaded with only the functions in use, lowering initial setup time while increasing overall system capability. To support a particular function, the card is downloaded with an “image,” which programs the FPGAs and DSPs at initialization. The user can change configurations by simply downloading a new set of instructions to the FPGA/DSP on the fly to keep the ground station running with minimal downtime. The flexibility of the design minimizes spare board costs, while achieving greater programmability at the end-user location.
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Parthasarathy, Anand Kumar. "Feasibility analysis of FPGA based spindle motor controller." Diss., Online access via UMI:, 2009.
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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2009.Includes bibliographical references.
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Szalkowski, Michael James. "An FPGA architecture design of a high performance adaptive notch filter /." Online version of thesis, 2008. http://hdl.handle.net/1850/7773.
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Schlottmann, Craig Richard. "A coordinated approach to reconfigurable analog signal processing." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/49021.
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The purpose of this research is to create a solid framework for embedded system design with field-programmable analog arrays (FPAAs). To achieve this goal, we've created a unified approach to the three phases of FPAA system design: (1) the hardware architecture; (2) the circuit design and modeling; and (3) the high-level software tools. First, we describe innovations to the reconfigurable analog hardware that enable advanced signal processing and integration into embedded systems. We introduce the multiple-input translinear element (MITE) FPAA and the dynamically-reconfigurable RASP 2.9v FPAA, which was designed explicitly for interfacing with external digital systems. This compatibility creates a streamlined workflow for dropping the FPAA hardware into mixed-signal embedded systems. The second phase, algorithm analysis and modeling, is important to create a useful and reliable library of components for the system designer. We discuss the concept and procedure of analog abstraction that empowers non-circuit design engineers to take full advantage of analog techniques. We use the analog vector-matrix multiplier as an example for a detailed discussion on computational analog analysis and system mapping to the FPAA. Lastly, we describe high-level software tools, which are an absolute necessity for the design of large systems due to the size and complexity of modern FPAAs. We describe the Sim2Spice tool, which allows system designers to develop signal processing systems in the Simulink environment. The tool then compiles the system to the FPAA hardware. By coordinating the development of these three phases, we've created a solid unified framework that empowers engineers to utilize FPAAs.
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McBride, Justin D. (Justin Donald) 1980. "High speed DSP implementation in run-time partially reconfigurable FPGAs." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/16982.
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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (leaves 99-100).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
This thesis investigates the feasibility of utilizing a run-time partially reconfigurable FPGA to implement a sequence of high-speed digital signal processing filters. Rather than reconfiguring the entire device to modify part of a configuration, a modular architecture is designed to allow smaller segments of the device to be individually reconfigured while the remainder of the device continues to operate. This document describes the design, implementation, simulation, and benchmarking of a five-socket modular DSP architecture and compares the results to the performance of alternative digital signal processing methods, particularly that of software DSP subroutines run on a PowerPC processor. The result is a highly flexible architecture that supports the use of timing verified hardware subroutines that could be partially reconfigured onto the FPGA within 3ms. The highly parallel processing power of the FPGA design yields a performance of 5.825 billion multiply and accumulate operations per second while simulated running at 72.8MHz, more than 76 times faster than similar calculations measured on a MPC7410 processor.
by Justin D. McBride.
M.Eng.and S.B.
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Shumba, Angela-Tafadzwa. "Channel coding on a nano-satellite platform." Thesis, Cape Peninsula University of Technology, 2018. http://hdl.handle.net/20.500.11838/2768.
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Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017.The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly reduced communication system performance. One of the effects of these constraints is the limitation on the type of channel coding technique that can be implemented in these communication systems. Another limiting factor on nano-satellite communication systems is the limited space available due to the compact nature of these satellites, where numerous complex systems are tightly packed into a space as small as 10x10x10cm. With the miniaturisation of Integrated-Circuit (IC) technology and the affordability of Field-Programmable-Gate-Arrays (FPGAs) with reduced power consumption, complex circuits can now be implemented within small form factors and at low cost. This thesis describes the design, implementation and cost evaluation of a ½-rate convolutional encoder and the corresponding Viterbi decoder on an FPGA for nano-satellites applications. The code for the FPGA implementation is described in VHDL and implemented on devices from the Artix7 (Xilinx), Cyclone V (Intel-fpga), and Igloo2 (Microsemi) families. The implemented channel code has a coding gain of ~3dB at a BER of 10-3. It can be noted that the implementation of the encoder is quite straightforward and that the main challenge is in the implementation of the decoder.
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Lowe, Darryn W. "Real-time FPGA realization of an UWB transceiver physical layer." Access electronically, 2005. http://www.library.uow.edu.au/adt-NWU/public/adt-NWU20060726.161825/index.html.
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Brown, Michelle M. "Hardware study on the H.264/AVC video stream parser /." Online version of thesis, 2008. http://hdl.handle.net/1850/7766.
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Ingram, David. "An Evaluation of Harmonic Isolation Techniques for Three Phase Active Filtering." Thesis, University of Canterbury. Electrical and Computer Engineering, 1998. http://hdl.handle.net/10092/1260.
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Recent advances in power electronics have lead to the wide spread adoption of advanced power supplies and energy efficient devices. This has lead to increased levels of harmonic currents in power systems, degrading the performance of electrical machinery and interfering with telecommunication services. Active filters provide a solution to these problems by compensating for the distorted currents drawn by non-linear loads. Optimal methods for controlling these active filters have been determined by computer simulation and experimental implementation. Methods used for isolating the harmonic content of an unbalanced three phase load current were compared by computer simulations. A technique based on the Fast Fourier Transform (FFT) was developed as part of this work and shown to perform favourably. Notch Filtering, Sinusoidal Subtraction, Instantaneous Reactive Power Theory, Synchronous Reference Frame and Fast Fourier Transform methods were simulated. The methods shown to be suitable for compensation of three phase unbalanced loads were implemented in a Digital Signal Processor to evaluate true performance. These methods were Notch Filtering, Sinusoidal Subtraction, Fast Fourier Transform, and a High Pass Filter based method. A completely digital hysteresis current controller for a three phase active filter inverter has been developed and implemented with a Field Programmable Gate Array. This controller interfaces directly to a digital signal processor and is resistant to electromagnetic interference. Results from the experimental hardware verified that the active filter model used for simulation is accurate, and may be used for further development of harmonic isolation methods. A technique using notch filtering gives the best performance for steady loads, with the FFT based technique giving the most flexible operation for a range of load current characteristics. Novel use of the FFT based harmonic isolation technique allows selective cancellation of individual harmonics, with particular application to multiple shunt filters connected in parallel.
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Migdadi, Hassan S. O. "The realization of signal processing methods and their hardware implementation over multi-carrier modulation using FPGA technology. Validation and implementation of multi-carrier modulation on FPGA, and signal processing of the channel estimation techniques and filter bank architectures for DWT using HDL coding for mobile and wireless applications." Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/8720.
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First part of this thesis presents the design, validation, and implementation of an Orthogonal
Frequency Division Multiplexing (OFDM) transmitter and receiver on a Cyclone II FPGA chip using DSP builder and Quartus II high level design tools. The resources in terms of logical elements (LE) including combinational functions and logic registers allocated by the model have been investigated and addressed. The result shows that implementing the basic OFDM transceiver allocates about 14% (equivalent to 6% at transmitter and 8% at receiver) of the available LE resources on an Altera Cyclone II EP2C35F672C6 FPGA chip, largely taken up by the FFT, IFFT and soft decision encoder.
Secondly, a new wavelet-based OFDM system based on FDPP-DA based channel estimation is proposed as a reliable ECG Patient Monitoring System, a Personal Wireless telemedicine application. The system performance for different wavelet mothers has been investigated. The effects of AWGN and multipath Rayleigh fading channels have also been studied in the analysis. The performances of FDPP-DA and HDPP-DA-based channel estimations are compared based on both DFT-based OFDM and wavelet-based OFDM systems. The system model was studied using MATLAB software in which the average BER was addressed for randomized data. The main error differences that reflect the quality of the received ECG signals between the reconstructed and original ECG signals are established.
Finally a DA-based architecture for 1-D iDWT/DWT based on an OFDM model is implemented for an ECG-PMS wireless telemedicine application. In the portable wireless body transmitter unit at the patient site, a fully Serial-DA-based scheme for iDWT is realized to support higher hardware utilization and lower power consumption; whereas a fully Parallel-DA-based scheme for DWT is applied at the base unit of the hospital site to support a higher throughput. It should be noted that the behavioural level of HDL models of the proposed system was developed and implemented to confirm its correctness in simulation. Then, after the simulation process the design models were synthesised and implemented for the target FPGA to confirm their validation.
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Migdadi, Hassan Saleh Okleh. "The realization of signal processing methods and their hardware implementation over multi-carrier modulation using FPGA technology : validation and implementation of multi-carrier modulation on FPGA, and signal processing of the channel estimation techniques and filter bank architectures for DWT using HDL coding for mobile and wireless applications." Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/8720.
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First part of this thesis presents the design, validation, and implementation of an Orthogonal Frequency Division Multiplexing (OFDM) transmitter and receiver on a Cyclone II FPGA chip using DSP builder and Quartus II high level design tools. The resources in terms of logical elements (LE) including combinational functions and logic registers allocated by the model have been investigated and addressed. The result shows that implementing the basic OFDM transceiver allocates about 14% (equivalent to 6% at transmitter and 8% at receiver) of the available LE resources on an Altera Cyclone II EP2C35F672C6 FPGA chip, largely taken up by the FFT, IFFT and soft decision encoder. Secondly, a new wavelet-based OFDM system based on FDPP-DA based channel estimation is proposed as a reliable ECG Patient Monitoring System, a Personal Wireless telemedicine application. The system performance for different wavelet mothers has been investigated. The effects of AWGN and multipath Rayleigh fading channels have also been studied in the analysis. The performances of FDPP-DA and HDPP-DA-based channel estimations are compared based on both DFT-based OFDM and wavelet-based OFDM systems. The system model was studied using MATLAB software in which the average BER was addressed for randomized data. The main error differences that reflect the quality of the received ECG signals between the reconstructed and original ECG signals are established. Finally a DA-based architecture for 1-D iDWT/DWT based on an OFDM model is implemented for an ECG-PMS wireless telemedicine application. In the portable wireless body transmitter unit at the patient site, a fully Serial-DA-based scheme for iDWT is realized to support higher hardware utilization and lower power consumption; whereas a fully Parallel-DA-based scheme for DWT is applied at the base unit of the hospital site to support a higher throughput. It should be noted that the behavioural level of HDL models of the proposed system was developed and implemented to confirm its correctness in simulation. Then, after the simulation process the design models were synthesised and implemented for the target FPGA to confirm their validation.
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Bousselham, Abdel Kader. "FPGA based data acquistion and digital pulse processing for PET and SPECT." Doctoral thesis, Stockholm University, Department of Physics, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:su:diva-6618.
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The most important aspects of nuclear medicine imaging systems such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT) are the spatial resolution and the sensitivity (detector efficiency in combination with the geometric efficiency). Considerable efforts have been spent during the last two decades in improving the resolution and the efficiency by developing new detectors. Our proposed improvement technique is focused on the readout and electronics. Instead of using traditional pulse height analysis techniques we propose using free running digital sampling by replacing the analog readout and acquisition electronics with fully digital programmable systems.
This thesis describes a fully digital data acquisition system for KS/SU SPECT, new algorithms for high resolution timing for PET, and modular FPGA based decentralized data acquisition system with optimal timing and energy. The necessary signal processing algorithms for energy assessment and high resolution timing are developed and evaluated. The implementation of the algorithms in field programmable gate arrays (FPGAs) and digital signal processors (DSP) is also covered. Finally, modular decentralized digital data acquisition systems based on FPGAs and Ethernet are described.
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Stehlík, Jiří. "Obvody s proudovou zpětnou vazbou pro zpracování analogových signálů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-233459.
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This dissertation thesis deals with design of new functional blocks usable in area of analogue signal processing, focusing on sensor signal processing. Versatility of these circuits will find applications in programmable analogue array structures that will be possible to control and configure via a digital signal. Hereby build-up array would be fully a reconfigurable digital control system for sensor signal processing and usable for a wide range of different sensors. It offers possibility to build-up a control code for each specific sensor system, with which it would be possible to achieve optimal results of the entire system and consequently place the system on a chip. The presented programmable array is designed from configurable analogue blocks. The current feedback circuits, which in a suitable configuration can operate in voltage or current mode, are used here. This allows to achieve very good results in the systems with very low power supply, which is closely associated with mobility and autonomous behavioral (that are very important and observed parameters today) of the entire sensor-based framework. The work deals in detail with particular blocks, which are described theoretically and evaluated for using in the programmable analogue array. Design of the structure of programmable analogue array as well the use of these circuits in the part of whole system (that will be realized on a chip) are presented at the end of this thesis.
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Morgan, Keith S. "SEU-Induced Persistent Error Propagation in FPGAs." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1377.pdf.
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Bonamy, Robin. "Modélisation, exploration et estimation de la consommation pour les architectures hétérogènes reconfigurables dynamiquement." Phd thesis, Université Rennes 1, 2013. http://tel.archives-ouvertes.fr/tel-00931849.
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L'utilisation des accélérateurs reconfigurables, pour la conception de system-on-chip hétérogènes, offre des possibilités intéressantes d'augmentation des performances et de réduction de la consommation d'énergie. En effet, ces accélérateurs sont couramment utilisés en complément d'un (ou de plusieurs) processeur(s) pour permettre de décharger celui-ci (ceux-ci) des calculs intensifs et des traitements de flots de données. Le concept de reconfiguration dynamique, supporté par certains constructeurs de FPGA, permet d'envisager des systèmes beaucoup plus flexibles en offrant notamment la possibilité de séquencer temporellement l'exécution de blocs de calcul sur la même surface de silicium, réduisant alors les besoins en ressources d'exécution. Cependant, la reconfiguration dynamique n'est pas sans impact sur les performances globales du système et il est difficile d'estimer la répercussion des décisions de configuration sur la consommation d'énergie. L'objectif principal de cette thèse consiste à proposer une méthodologie d'exploration permettant d'évaluer l'impact des choix d'implémentation des différentes tâches d'une application sur un system-on-chip contenant une ressource reconfigurable dynamiquement, en vue d'optimiser la consommation d'énergie ou le temps d'exécution. Pour cela, nous avons établi des modèles de consommation des composants reconfigurables, en particulier les FPGAs, qui permettent d'aider le concepteur dans son design. À l'aide d'une méthodologie de mesure sur Virtex-5, nous montrons dans un premier temps qu'il est possible de générer des accélérateurs matériels de tailles variées ayant des performances temporelles et énergétiques diverses. Puis, afin de quantifier les coûts d'implémentation de ces accélérateurs, nous construisons trois modèles de consommation de la reconfiguration dynamique partielle. Finalement, à partir des modèles définis et des accélérateurs produits, nous développons un algorithme d'exploration des solutions d'implémentation pour un système complet. En s'appuyant sur une plate-forme de modélisation à haut niveau, celui-ci analyse les coûts d'implémentation des tâches et leur exécution sur les différentes ressources disponibles (processeur ou région configurable). Les solutions offrant les meilleures performances en fonction des contraintes de conception sont retenues pour être exploitées.
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Voigt, Sven-Ole. "Dynamically reconfigurable dataflow architecture for high performance digital signal processing on multi FPGA platforms." Aachen Shaker, 2008. http://d-nb.info/992481694/04.
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Fernandes, Anderson Luiz. "Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência." Universidade Tecnológica Federal do Paraná, 2016. http://repositorio.utfpr.edu.br/jspui/handle/1/1785.
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A presença de cargas não-lineares em um ponto do sistema de distribuição pode deformar a forma de onda de tensão devido ao consumo de correntes não senoidais. O uso de filtros ativos de potência permite uma redução significativa do conteúdo harmônico da corrente de alimentação. Entretanto, as estruturas digitais de controle para estes filtros, particularmente o cálculo das correntes de referência, pode necessitar de processamento de alto desempenho. Neste trabalho se propõe o desenvolvimento de estruturas de controle com alto desempenho de processamento, para aplicação em filtros ativos de potência. Neste sentido, é considerada uma arquitetura que permite processamento paralelo utilizando dispositivos lógicos programáveis. A estrutura desenvolvida utiliza um modelo híbrido com um DSP e uma FPGA. O DSP é utilizado para aquisição de sinais de tensão e corrente, controladores adicionais relacionados a fundamental e acionamento PWM. A FPGA é utilizada para o processamento intensivo do sinal de compensação de harmônicas. Desta forma, através da análise experimental são obtidas reduções significativas nos tempos de processamento comparadas as abordagens tradicionais utilizando somente DSP. Os resultados experimentais validam a estrutura projetada e são comparados com outras arquiteturas relatadas na literatura.The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.
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Assef, Amauri Amorin. "Arquitetura de hardware multicanal reconfigurável com excitação multinível para desenvolvimento e testes de novos métodos de geração de imagens por ultrassom." Universidade Tecnológica Federal do Paraná, 2013. http://repositorio.utfpr.edu.br/jspui/handle/1/889.
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UTFPR; CNPq; CAPES; Fundação Araucária; Ministério da SaúdeOs sistemas de diagnóstico por imagem de ultrassom (US) figuram entre os mais sofisticados equipamentos de processamento de sinais na atualidade. Apesar da alta tecnologia envolvida, a maioria dos sistemas comerciais de imagem possui arquitetura típica “fechada”, não atendendo às exigências de flexibilidade e acesso aos dados de radiofrequência (RF) para desenvolvimento e teste de novas modalidades e técnicas do US. Este trabalho apresenta uma nova arquitetura modular de hardware (front-end), baseada em dispositivos FPGA (Field Programmable Gated Array), e software (back-end), baseada em PC ou DSP, totalmente programável, aberta e flexível, para pesquisa e investigação de técnicas inovadoras para geração de imagens médicas por US. A plataforma desenvolvida ULTRA-ORS (do inglês Ultrasound Open Research System) permite conexão com transdutores multielementos dos tipos lineares, convexos e phased array com frequência central entre 500 kHz e 20 MHz, e capacidade de expansão para operação com transdutores de até 1024 elementos multiplexados. O módulo eletrônico lógico para formação do feixe (beamformer transmitter) possibilita excitação simultaneamente, através de sinais PWM, de 128 canais com formas de ondas arbitrárias, abertura programável, e tensão de excitação de até 200 Vpp, permitindo controle individual de habilitação, amplitude de apodização com até 256 níveis, ângulo de fase e atraso temporal de disparo adequado para focalização na transmissão. O módulo de recepção (beamformer receiver) realiza a aquisição simultânea de 128 canais com taxa de amostragem programável até 50 MHz e resolução de 12 bits. Como item imprescindível deste trabalho, a plataforma proposta possibilita acesso e transferência dos dados de RF digitalizados para um computador através de interfaces seriais ou para kits de DSP para processamento das imagens. Como resultado do projeto de pesquisa, é apresentado um novo sistema digital de US que pode ser utilizado para avaliações das imagens geradas pela técnica beamforming, utilizando como referência a ferramenta de simulação Field II e comparações com as imagens geradas por equipamentos comerciais em phantom mimetizador de tecidos biológicos de US.
Medical ultrasound (US) scanners are amongst the most sophisticated signal processing machines in use today. Even with the recent advances in electronic technology, their typical architecture is often “closed” and does not fit the requirements of flexibility and RF data access to the development and test of new modalities and US techniques. This work presents the development of a novel modular hardware architecture (front-end), FPGA-based (Field Programmable Gated Array) and software (back-end), PC-based or DSP-based, fully programmable, open and flexible, for research and investigation of new techniques for medical US imaging. The proposed platform, ULTRA-ORS (Ultrasound Open Research System), allows connection to linear, convex and phased array transducers with center frequency between 500 kHz and 20 MHz, and expansion capability for operation with transducers up to 1024 multiplexed elements. The transmitter beamformer can excite simultaneously, using PWM signals, 128-channel with arbitrary waveform, programmable aperture, and 200 Vpp excitation voltage, allowing individual enable control, amplitude apodization up to 256 levels, phase angle and proper time delay for focusing on transmission. The receiver beamformer can handle simultaneous 128-channels acquisition with programmable sampling rate up to 50 MHz and 12-bit resolution. As essential item of this work, the platform enables access to the raw RF signals to be transferred to a computer through serial ports or DSP kits for imaging processing. As a result of the research project, we present a new digital US system that can be used for evaluation of images generated by the beamforming technique, using as reference the Field II simulation tool and comparisons with commercial equipment using US tissue-mimicking phantom.
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Kamp, William Hermanus Michael. "Redundant Number Systems for Optimising Digital Signal Processing Performance in Field Programmable Gate Array." Thesis, University of Canterbury. Electrical and Computer Engineering, 2010. http://hdl.handle.net/10092/4623.
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Speeding up addition is the key to faster digital signal processing (DSP). This can be achieved by exploiting the properties of redundant number systems. Their expanded symbol (digit) alphabet gives them multiple representations for most values. Utilising redundant representations at the output of an adder permits addition to be performed without carry-propagation, yielding fast, constant time performance irrespective of the word length. A resource efficient implementation of this fast adder structure is developed that re-purposes the fast carry logic of low-cost field programmable gate arrays (FPGAs). Experiments confirm constant time addition and show that it outperforms binary ripple carry addition at word lengths of greater than 44 bits in a Xilinx Spartan 3 FPGA and 24 bits in an Altera Cyclone III FPGA.
Redundancy also provides other properties that can be exploited for performance gain. Some redundant representations will have more zero-symbols than others. These maximise the opportunities to exploit the multiplicative absorbing and additive identity properties of zero that when exercised reduce superfluous calculations. A serial recoding algorithm is developed that generates a redundant representation for a specified value with as few nonzero symbols as possible. Unlike previously published methods, it accepts a wide specification of number systems including those with irregularly spaced symbol alphabets. A Markov analysis and analysis of the elementary cycles in the formulated state machine provides average and worst case measures for the tested number system. Typically, the average number of non-zero symbols is less than a third and the worst case is less than a half.
Further to the increase in zero-symbols, zero-dominance is proposed as a new property of redundant number representations. It promotes a set of representations that have uniquely positioned zero-symbols, in a Pareto-optimal sense. This set covers all representations of a value and is used to select representations to optimise the calculation of a dot-product.
The dot-product or vector-multiply is a fundamental operation in DSP, since it is employed in filtering, correlation and convolution. The nonzero partial products can be packed together, substantially reducing the calculation time. The application of redundant number systems provides a two-fold benefit. Firstly, the number of nonzero partial products is reduced. Secondly, a novel opportunity is identified to use the representations in the zero-dominant set to optimise the packing further, gaining an extra 18% improvement.
An implementation of the proposed dot-product with partial product packing is developed for a Cyclone II FPGA. It outperforms a quad-multiplier binary implementation in throughput by 50% .
Redundant number systems excel at increasing performance in particular DSP subsystems, those that are numerically intensive and consist of considerable accumulation. The conversion back to a binary result is the performance bottleneck in the DSP algorithm, taking a time proportional to a binary adder. Therefore, redundant number systems are best utilised when this conversion cost can be amortised over many fast redundant additions, which is typical in many DSP and communications applications.
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Balavoine, Aurèle. "Implementation of the locally competitive algorithm on a field programmable analog array." Thesis, Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37255.
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Sparse approximation is an important class of optimization problem in signal and image processing applications. This thesis presents an analog solution to this problem, based on the Locally Competitive Algorithm (LCA). A Hopfield-Network-like analog system, operating on sub-threshold currents is proposed as a solution.
The results of the circuit components' implementation on the RASP2.8a chip, a Field Programmable Analog Array, are presented.
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Pelan, Justin Darrell. "Modular Multi-Signal Tracking Pulse Descriptor Word (PDW) Generator WithField Programmable Gate Array (FPGA) Implementation." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1472223866.
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Papenfuss, Frank. "Digital signal processing of nonuniform sampled signals contributions to algorithms & hardware architectures." Aachen Shaker, 2007. http://d-nb.info/987695959/04.
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Milford, Matthew Thomas Ian. "Memory centric compilers for embedded streaming systems." Thesis, Queen's University Belfast, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675446.
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Silva, Tiago Polizer da. "Anemômetro ultrassônico unidimensional baseado em correlação cruzada." Universidade Tecnológica Federal do Paraná, 2016. http://repositorio.utfpr.edu.br/jspui/handle/1/1929.
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Este trabalho descreve o desenvolvimento de um medidor de velocidade de vento aplicando técnicas da teoria de erros, como a correlação cruzada, bem como sensores de ultrassom. Ele pode ser utilizado em encanamentos, onde se busca obter a velocidade de fluídos, em estações climáticas, em aeroportos, no momento de se aplicar pesticidas assim como em fazendas eólicas, onde o conhecimento da velocidade do vento é necessário, dentre outras aplicações. O sistema desenvolvido é composto pela placa de desenvolvimento de0-nano, uma placa de circuito impresso (PCB) para aquisição de sinais e dois pares de sensores de ultrassom. A PCB também possui circuitos para excitação dos sensores de ultrassom bem como comunicação com o PC para armazenamento dos sinais amostrados. A teoria de erros foi discutida e os resultados do protótipo foram analisados utilizando métodos probabilísticos necessários para verificar a incerteza. Dentro da FPGA da placa de0-nano foi desenvolvido um sistema baseado no processador NIOS, o qual foi construído através da ferramenta QSYS. Além disso, blocos em VHDL foram desenvolvidos para interfaceamento do sistema com o PC. Um pequeno túnel de vento foi construído e um anemômetro de mão foi adquirido para validar o protótipo. Simulações foram realizadas no Microsoft Excel 2007 para comparar a correlação cruzada dada pelo protótipo e a teoria. É comum que DSPs e Microprocessadores estejam dentro de medidores de velocidade do vento, no entanto um sistema desenvolvido com FPGA aumenta a velocidade de processamento devido ao paralelismo. Blocos descritos em VHDL podem ser facilmente replicados dentro da FPGA e existe uma grande coleção de bibliotecas, literatura extensiva e exemplos de código para o NIOS. Com isso há um menor tempo de desenvolvimento de um protótipo/sistema e há facilidade de desenvolver um System on Chip (SoC) de sistemas baseados em FPGA, reduzindo os custos de um futuro produto comercial.This work describes the development of one axis wind speed measurement equipment applying error theory techniques, as the cross correlation, and ultrasound sensors. It can be used in tubes, where fluid speed knowledge is needed, climate stations, airports, in the moment of applying pesticides and in wind farms, where wind speed knowledge is necessary. The built prototype is a connected set of a de0-nano development board, a signal acquisition printed circuit board and two pairs of ultrasound sensors. The PCB also has circuits for ultrasound sensors exciting and PC communications to store the sampled signals. The error theory was discussed and the prototype's results were developed using probabilistic methods needed to verify the uncertainty. Inside de0-nano board FPGA chip, a system based in NIOS processor was developed and built through QSYS tool. There are some blocks described in VHDL for PCB interfacing. A small wind tunnel was built and a hand anemometer was acquired to validate the proposed system. Simulations were done in Microsoft Excel 2007 to compare the cross correlation given by the prototype and the theory. It is common DSPs and microprocessors inside this type of equipments to measure wind speed, but a system developed with a FPGA increases the processing speed due to parallelism. Blocks described in VHDL can be easily replicated inside the FPGA and there is a large collection of libraries, extensive literature and code examples for NIOS. Thereby there are small system/prototype developing times and there is an easy development of a System on Chip (SOC) of FPGA based systems, reducing the costs for a future commercial product.
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Aliaga, Varea Ramón José. "Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end." Doctoral thesis, Universitat Politècnica de València, 2016. http://hdl.handle.net/10251/63271.
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[EN] Positron Emission Tomography (PET) is a non-invasive nuclear medical imaging modality that makes it possible to observe the distribution of metabolic substances within a patient's body after marking them with radioactive isotopes and arranging an annular scanner around him in order to detect their decays. The main applications of this technique are the detection and tracing of tumors in cancer patients and metabolic studies with small animals.
The Electronic Design for Nuclear Applications (EDNA) research group within the Instituto de Instrumentación para Imagen Molecular (I3M) has been involved in the study of high performance PET systems and maintains a small experimental setup with two detector modules. This thesis is framed within the necessity of developing a new data acquisition system (DAQ) for the aforementioned setup that corrects the drawbacks of the existing one. The main objective is to define a DAQ architecture that is completely scalable, modular, and guarantees the mobility and the possibility of reusing its components, so that it admits any extension of modification of the setup and it is possible to export it directly to the configurations used by other groups or experiments. At the same time, this architecture should be compatible with the best possible resolutions attainable at the present instead of imposing artificial limits on system performance. In particular, the new DAQ system should outperform the previous one.
As a first step, a general study of DAQ arquitectures is carried out in the context of experimental setups for PET and other high energy physics applications. On one hand, the conclusion is reached that the desired specifications require early digitization of detector signals, exclusively digital communication between modules, and the absence of a centralized trigger. On the other hand, the necessity of a very precise distributed synchronization scheme between modules becomes apparent, with errors in the order of 100 ps, and operating directly over the data links. A study of the existing methods reveals their severe limitations in terms of achievable precision. A theoretical analysis of the situation is carried out with the goal of overcoming them, and a new synchronization algorithm is proposed that is able to reach the desired resolution while getting rid of the restrictions on clock alignment that are imposed by virtually all usual schemes. Since the measurement of clock phase difference plays a crucial role in the proposed algorithm, extensions to the existing methods are defined and analyzed that improve them significantly. The proposed scheme for synchronism is validated using commercial evaluation boards.
Taking the proposed synchronization method as a starting point, a DAQ architecture for PET is defined that is composed of two types of module (acquisition and concentration) whose replication makes it possible to arrange a hierarchic system of arbitrary size, and circuit boards are designed and commissioned that implement a realization of the architecture for the particular case of two detectors. This DAQ is finally installed at the experimental setup, where their synchronization properties and resolution as a PET system are characterized and its performance is verified to have improved with respect to the previous system.[ES] La Tomografía por Emisión de Positrones (PET) es una modalidad de imagen médica nuclear no invasiva que permite observar la distribución de sustancias metabólicas en el interior del cuerpo de un paciente tras marcarlas con isótopos radioactivos y disponer después un escáner anular a su alrededor para detectar su desintegración. Las principales aplicaciones de esta técnica son la detección y seguimiento de tumores en pacientes con cáncer y los estudios metabólicos en animales pequeños. El grupo de investigación Electronic Design for Nuclear Applications (EDNA) del Instituto de Instrumentación para Imagen Molecular (I3M) ha estado involucrado en el estudio de sistemas PET de alto rendimiento y mantiene un pequeño setup experimental con dos módulos detectores. La presente tesis se enmarca dentro de la necesidad de desarrollar un nuevo sistema de adquisición de datos (DAQ) para dicho setup que corrija los inconvenientes del ya existente. En particular, el objetivo es definir una arquitectura de DAQ que sea totalmente escalable, modular, y que asegure la movilidad y la posibilidad de reutilización de sus componentes, de manera que admita cualquier ampliación o alteración del setup y pueda exportarse directamente a los de otros grupos o experimentos. Al mismo tiempo, se desea que dicha arquitectura no limite artificialmente el rendimiento del sistema sino que sea compatible con las mejores resoluciones disponibles en la actualidad, y en particular que sus prestaciones superen a las del DAQ instalado previamente. En primer lugar, se lleva a cabo un estudio general de las arquitecturas de DAQ para setups experimentales para PET y otras aplicaciones de física de altas energías. Por un lado, se determina que las características deseadas implican la digitalización temprana de las señales del detector, la comunicación exclusivamente digital entre módulos, y la ausencia de trigger centralizado. Por otro lado, se hace patente la necesidad de un esquema de sincronización distribuida muy preciso entre módulos, con errores del orden de 100 ps, que opere directamente sobre los enlaces de datos. Un estudio de los métodos ya existentes revela sus graves limitaciones a la hora de alcanzar esas precisiones. Con el fin de paliarlos, se lleva a cabo un análisis teórico de la situación y se propone un nuevo algoritmo de sincronización que es capaz de alcanzar la resolución deseada y elimina las restricciones de alineamiento de reloj impuestas por casi todos los esquemas usuales. Dado que la medida de desfase entre relojes juega un papel crucial en el algoritmo propuesto, se definen y analizan extensiones a los métodos ya existentes que suponen una mejora sustancial. El esquema de sincronismo propuesto se valida utilizando placas de evaluación comerciales. Partiendo del método de sincronismo propuesto, se define una arquitectura de DAQ para PET compuesta de dos tipos de módulos (adquisición y concentración) cuya replicación permite construir un sistema jerárquico de tamaño arbitrario, y se diseñan e implementan placas de circuito basadas en dicha arquitectura para el caso particular de dos detectores. El DAQ así construído se instala finalmente en el setup experimental, donde se caracterizan tanto sus propiedades de sincronización como su resolución como sistema PET y se comprueba que sus prestaciones son superiores a las del sistema previo.
[CAT] La Tomografia per Emissió de Positrons (PET) és una modalitat d'imatge mèdica nuclear no invasiva que permet observar la distribució de substàncies metabòliques a l'interior del cos d'un pacient després d'haver-les marcat amb isòtops radioactius disposant un escàner anular al seu voltant per a detectar la seua desintegració. Aquesta tècnica troba les seues principals aplicacions a la detecció i seguiment de tumors a pacients amb càncer i als estudis metabòlics en animals petits. El grup d'investigació Electronic Design for Nuclear Applications (EDNA) de l'Instituto de Instrumentación para Imagen Molecular (I3M) ha estat involucrat en l'estudi de sistemes PET d'alt rendiment i manté un petit setup experimental amb dos mòduls detectors. Aquesta tesi neix de la necessitat de desenvolupar un nou sistema d'adquisició de dades (DAQ) per al setup esmentat que corregisca els inconvenients de l'anterior. En particular, l'objectiu és definir una arquitectura de DAQ que sigui totalment escalable, modular, i que asseguri la mobilitat i la possibilitat de reutilització dels seus components, de tal manera que admeta qualsevol ampliació o alteració del setup i pugui exportar-se directament a aquells d'altres grups o experiments. Al mateix temps, es desitja que aquesta arquitectura no introduisca límits artificials al rendiment del sistema sinó que sigui compatible amb les millors resolucions disponibles a l'actualitat, i en particular que les seues prestacions siguin superiors a les del DAQ instal.lat amb anterioritat. En primer lloc, es porta a terme un estudi general de les arquitectures de DAQ per a setups experimentals per a PET i altres aplicacions de física d'altes energies. Per una banda, s'arriba a la conclusió que les característiques desitjades impliquen la digitalització dels senyals del detector el més aviat possible, la comunicació exclusivament digital entre mòduls, i l'absència de trigger centralitzat. D'altra banda, es fa palesa la necessitat d'un mecanisme de sincronització distribuïda molt precís entre mòduls, amb errors de l'ordre de 100 ps, que treballi directament sobre els enllaços de dades. Un estudi dels mètodes ja existents revela les seues greus limitacions a l'hora d'assolir aquest nivell de precisió. Amb l'objectiu de pal.liar-les, es duu a terme una anàlisi teòrica de la situació i es proposa un nou algoritme de sincronització que és capaç d'obtindre la resolució desitjada i es desfà de les restriccions d'alineament de rellotges imposades per gairebé tots els esquemes usuals. Atès que la mesura del desfasament entre rellotges juga un paper cabdal a l'algoritme proposat, es defineixen i analitzen extensions als mètodes ja existents que suposen una millora substancial. L'esquema de sincronisme proposat es valida mitjançant plaques d'avaluació comercials. Prenent el mètode proposat com a punt de partida, es defineix una arquitectura de DAQ per a PET composta de dos tipus de mòduls (d'adquisició i de concentració) tals que la replicació d'aquests elements permet construir un sistema jeràrquic de mida arbitrària, i es dissenyen i implementen plaques de circuit basades en aquesta arquitectura per al cas particular de dos detectors. L'electrònica desenvolupada s'instal.la finalment al setup experimental, on es caracteritzen tant les seues propietats de sincronització com la seua resolució com a sistema PET i es comprova que les seues prestacions són superiors a les del sistema previ.
Aliaga Varea, RJ. (2016). Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/63271
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Jarrah, Amin. "Development of Parallel Architectures for Radar/Video Signal Processing Applications." University of Toledo / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1415806786.
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Doré, Jean-Baptiste. "Optimisation conjointe de codes LDPC (Low Density Parity Check) et de leurs architectures de décodage et mise en oeuvre sur FPGA (Field Programmable Gate Array)." Rennes, INSA, 2007. https://tel.archives-ouvertes.fr/tel-00191155v2.
Full textAbstract:
La découverte dans les années 90 des Turbo-codes et, plus généralement du principe itératif appliqué au traitement du signal, a révolutionné la manière d'appréhender un système de communications numériques. Cette avancée notable a permis la re-découverte des codes correcteurs d'erreurs inventés par R. Gallager en 1963, appelés codes Low Density Parity Check (LDPC). L'intégration des techniques de codage dites avancées, telles que les Turbo-codes et les codes LDPC, se généralise dans les standards de communications. Dans ce contexte, l'objectif de cette thèse est d'étudier de nouvelles structures de codage de type LDPC associées à des architectures de décodeurs alliant performances et flexibilité. Dans un premier temps, une large présentation des codes LDPC est proposée incluant les notations et les outils algorithmiques indispensables à la compréhension. Cette introduction des codes LDPC souligne l'intérêt qu'il existe à concevoir conjointement le système de codage/décodage et les architectures matérielles. Dans cette optique, une famille de codes LDPC particulièrement intéressante est décrite. En particulier nous proposons des règles de construction de codes pour en contraindre le spectre des distances de Hamming. Ces contraintes sont intégrées dans la définition d'un nouvel algorithme de définition de codes travaillant sur une représentation compressée du code par un graphe. Les propriétés structurelles du code sont ensuite exploitées pour définir l'algorithme de décodage. Cet algorithme, caractérisé par le fait qu'il considère une partie du code comme un code convolutif, converge plus rapidement que les algorithmes habituellement rencontrés tout en permettant une grande flexibilité en termes de rendements de codage. Différentes architectures de décodeurs sont alors décrites et discutées. Des contraintes sur les codes sont ensuite exposées pour exploiter pleinement les propriétés des architectures. Dans un dernier temps, une des architectures proposées est évaluée par l'intégration d'un décodeur sur un composant programmable. Dans différents contextes, des mesures de performances et de complexité montrent l'intérêt de l'architecture proposéeThe introduction of Turbo-codes in the early 90's and, more generally the iterative principle, has deeply modified the methods for the design of communication systems. This breakthrough has also resurrected the Low Density Parity Check (LDPC) codes invented by R. Gallager in 1963. Advanced channel coding techniques such as Turbo-codes and LDPC, are now increasingly considered for introduction into communication systems and standards. This evolution towards industrialization motivates the definition of new flexible and efficient decoding architecture for LDPC codes. In this thesis, we focus our research on the iterative decoding of LDPC codes and their hardware implementation. We first introduce basic concepts and notations for LDPC codes, which are necessary for a good comprehension. This introduction underlines the interest of jointly designing codes, decoding algorithm and architecture. From this perspective, a family of LDPC codes is described. We define some design rules to constrain the distance spectrum of the code. These constraints are introduced into a new algorithm for the design of the code working on a compact representation of the code graph. A new decoding algorithm is also defined, taking advantage of the intrinsic properties of the code structure. Convergence of the decoding algorithm is increased compared to classical decoding algorithm for LDPC codes. Performance and flexibility of this algorithm is discussed. Different architectures are then described and studied. Some constraints on the codes are derived to target an architecture. The last part of the thesis illustrates the implementation of one of the architectures discussed into a field-programmable gate array (FPGA). Performance and complexity measures are presented for various contexts, showing the interest of the concept for all these cases
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Hudson, Robert Dearn. "Development of an integrated co-processor based power electronic drive / by Robert D. Hudson." Thesis, North-West University, 2008. http://hdl.handle.net/10394/3723.
Full textAbstract:
The McTronX research group at the North-West University is currently researching self-sensing techniques for Active Magnetic Bearings (AMB). The research is part of an ongoing effort to expand the knowledge base on AMBs in the School of Electrical, Electronic and Computer Engineering to support industries that make use of the technology. The aim of this project is to develop an integrated co-processor based power electronic drive with the emphasis placed on the ability of the co-processor to execute AMB self-sensing algorithms.
The two primary techniques for implementing self-sensing in AMBs are state estimation and modulation. This research focuses on hardware development to facilitate the implementation of the modulation method. Self-sensing algorithms require concurrent processing power and speed that are well suited to an architecture that combines a digital signal processor (DSP) and a field programmable gate array (FPGA). A comprehensive review of various power amplifier topologies shows that the pulse width modulation (PWM) switching amplifier is best suited for controlling the voltage and current required to drive the AMB coils. Combining DSPs and power electronics to form an integrated co-processor based power electronic drive requires detail attention to aspects of PCB design, including signal integrity and grounding.
A conceptual design is conducted and forms part of the process of compiling a subsystem development specification for the integrated drive, in conjunction with the McTronX Research Group. Component selection criteria, trade-off studies and various circuit simulations serve as the basis for this essential phase of the project. The conceptual design and development specification determines the architecture, functionality and interfaces of the integrated drive. Conceptual designs for the power amplifier, digital controller, electronic supply and mechanical layout of the integrated drive is provided.
A detail design is performed for the power amplifier, digital controller and electronic supply. Issues such as component selection, power supply requirements, thermal design, interfacing of the various circuit elements and PCB design are covered in detail. The output of the detail design is a complete set of circuit diagrams for the integrated controller.
The integrated drive is interfaced with existing AMB hardware and facilitates the successful implementation of two self-sensing techniques. The hardware performance of the integrated coprocessor based power electronic drive is evaluated by means of measurements taken from this experimental self-sensing setup. The co-processor performance is evaluated in terms of resource usage and execution time and performs satisfactorily in this regard.
The integrated co-processor based power electronic drive provided sufficient resources, processing speed and flexibility to accommodate a variety of self-sensing algorithms thus contributing to the research currently underway in the field of AMBs by the McTronX research group at the North-West University.Thesis (M.Ing. (Electrical Engineering))--North-West University, Potchefstroom Campus, 2009.
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Sousa, Éricles Rodrigues. "Arquitetura computacional híbrida baseada em DSP e FPGA para processamento digital de sinais." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259485.
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Orientador: Luís Geraldo Pedroso MeloniDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-19T09:59:52Z (GMT). No. of bitstreams: 1 Sousa_EriclesRodrigues_M.pdf: 2046025 bytes, checksum: 14fd32eefec8c8da68e3337d5e033567 (MD5) Previous issue date: 2011
Resumo: Atualmente, aplicações multimídias exigem grande esforço computacional para manipular dados com elevadas taxas de precisão. Visando otimizar a capacidade de processamento sem elevar demasiadamente o custo do desenvolvimento em sistemas embarcados, este trabalho descreve a proposta de uma arquitetura computacional hibrida, para processamento digital de sinais, baseado-se no uso cooperativo entre DSP (Digital Signal Processor) e FPGA (Field Programmable Gate Array). Neste estudo e realizada uma abordagem sobre o uso de um coprocessador para a acelerar rotinas que demandam grande esforço computacional em um DSP. Também e proposto um modelo matemático capaz de mensurar a eficiência do particionamento de códigos processados de forma descentralizada. Para validação da proposta, foi construído um cenários de testes para a estimação de vetores movimento, um dos principais agentes envolvidos no processo de codificação de vídeo em alta definição. A partir do cenário elaborado foi possível constatar a eficiência da arquitetura proposta. Sendo que, considerando um código de referencia otimizado e baseado na descrição feita em [30], obteve-se mais de 97% de eficiência computacional. Assim, este estudo permite concluir que o uso cooperativo entre DSP e FPGA se mostra muito vantajoso devido a possibilidade de unir em um único sistema as vantagens fornecidas por ambos dispositivos, caracterizando um ambiente de total sinergia e de elevada capacidade de computacional
Abstract: Nowadays, multimedia applications require high computational effort to manipulate data with high precision. In order to optimize the processing power without significantly increasing the cost of development in embedded systems, this work describes the proposal for a hybrid computing architecture applied to digital signal processing, based on the cooperative work between DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array). An approach about the use of coprocessor able to accelerate a process which requires great computational effort of a DSP is provided by this study. It is also describes a mathematical model able to measure the efficiency of a partitioning code processed in a distributed system. To validate our proposal we developed a tested for calculate the motion estimation vector, which is one of key elements involved on high definition video coding. From the elaborated tested, we could found a high efficiency provided by the architecture proposed. Therefore, considering a optimized reference code based on [30], was possible achieve a computing efficiency around 97%. This study show that cooperative work between DSP and FPGA that provides a very advantageous scenario applied to embedded systems, due to joining the features of both devices, building then, a synergy environment of high computing performance
Mestrado
Telecomunicações e Telemática
Mestre em Engenharia Elétrica
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Pagano, Danilo Morais. "Proposta de uma arquitetura de processamento de sinais utilizando FPGA." [s.n.], 2012. http://repositorio.unicamp.br/jspui/handle/REPOSIP/264121.
Full textAbstract:
Orientador: Eurípedes Guilherme de Oliveira NóbregaDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica
Made available in DSpace on 2018-08-20T08:18:33Z (GMT). No. of bitstreams: 1 Pagano_DaniloMorais_M.pdf: 25950218 bytes, checksum: f9af4571e3d7f1f88caed4d997e809ba (MD5) Previous issue date: 2012
Resumo: Esta dissertação apresenta um sistema para processamento digital de sinais através de dispositivos de hardware reconfigurável. Uma implementação do algoritmo FFT foi adotada como meio para avaliar o desempenho da arquitetura proposta para o sistema. O processamento digital de sinais tradicionalmente tem um alto custo computacional, pois os algoritmos são implementados em software, o que pode não atender as restrições de tempo de aplicações reais. O objetivo principal deste trabalho é desenvolver uma arquitetura para adquirir os sinais através de módulos de aquisição de dados distribuídos em uma rede e processá-los usando um FPGA. Um microcontrolador da FreeScale Semiconductors'MARCA REGISTRADA' foi adotado como módulo de aquisição de dados, executando um sistema operacional de tempo real (RTOS) para garantir os requisitos temporais. Foi implementado o processador soft-core NIOS 2 da Altera'MARCA REGISTRADA' executando também um RTOS com recursos de comunicação em rede, incluindo um periférico escrito em VHDL para o processamento da FFT usando uma estrutura de pipeline baseada em estágios e comunicação direta ao barramento do processador. A versão em hardware do algoritmo obteve uma redução de até 2000 vezes no tempo de processamento da FFT comparado com a mesma versão implementada em software, alcançando um tempo de processamento de 3.9 microssegundos para sinais discretizados em 256 pontos, quando usado 100MHz de clock. A quantidade de pontos pode ser facilmente aumentada alterando-se apenas o núcleo do periférico desenvolvido, e os resultados permitem adotar a arquitetura proposta para aplicações em tempo real de processamento digital de sinais
Abstract: This work presents a digital signal processing system based on reconfigurable hardware. Implementation of the FFT algorithm is used as a mean to assess the adopted configuration performance. Digital signal processing algorithms are in general software implemented, incurring high computational cost, which may not attend the real-time constraints of real applications. The main objective of this work is to develop an FPGA based architecture to process signals acquired through a distributed network of data acquisition modules. A microcontroller from FreeScale Semiconductors'TRADE MARK' was adopted as data acquisition module, running a real-time operating system (RTOS) to guarantee timing requirements. The soft-core processor NIOS 2 from Altera'TRADE MARK' , also running an RTOS with network communication capabilities, was implemented including a peripheral module written in VHDL for the computation of the FFT, which uses a pipeline-based stage structure and directly communicates with the processor bus. The hardware version of the algorithm achieved a reduction up to 2000 times in the FFT processing time compared to the same version implemented in software, reaching a processing time of 3.9 microseconds for 256 points sampled signals when using 100MHz of clock. The number of points can be easily increased just changing the core of the developed peripheral module, and the results permit to expect adequate real-time application of digital signal processing adopting the proposed configuration
Mestrado
Mecanica dos Sólidos e Projeto Mecanico
Mestre em Engenharia Mecânica