Journal articles: 'Field programmable mixed-signal arrays'

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Wunderlich, Richard B., Farhan Adil, and Paul Hasler. "Floating Gate-Based Field Programmable Mixed-Signal Array." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 8 (August 2013): 1496–505. http://dx.doi.org/10.1109/tvlsi.2012.2211049.

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Lakshmanan, S. K., and A. Koenig. "Towards a generic operational amplifier with dynamic reconfiguration capability." Advances in Radio Science 4 (September 6, 2006): 259–62. http://dx.doi.org/10.5194/ars-4-259-2006.

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Abstract. Analog and analog-digital mixed signal electronics needed for sensor systems are indispensable components which tend to drifts from the normal phase of operation due to the impact of manufacturing conditions and environmental influences like etching, aging etc. Precise design methodology, trimming / calibration are essential to restore functionality of the system. Recent block level granular approaches using Field Programmable Analog Array and the more recent approaches from evolutionary electronics providing transistor level granularity using Field Programmable Transistor Arrays offers considerable extensions. In our work, we started on a new medium granular level approach called Field Programmable medium-granular Mixed-signal Array (FPMA) providing basic building blocks of heterogeneous array of active and passive devices to configure established circuit structures which are adaptive, biologically inspired and dynamically re-configurable. Our design objective is to create components of clear compatibility to that of the industrial standards having predictable behavior along with the incorporation of existing design knowledge. The cells can be used in as a single instance or multiple instances. Further, we will focus on a generic dynamic reconfigurable amplifier cell with flexible topology and dimension called Generic Operational Amplifier (GOPA). The incentive of our work comes from recent development in the field of measurement and instrumentation. The digital programming of analog devices is carried out using range of algorithms from simple to evolutionary. Physical realization of the basic cells is carried out in 0.35 μm CMOS technology.

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Liu, Lintao, Yuhan Gao, and Jun Deng. "Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays." Journal of Semiconductors 38, no. 11 (November 2017): 115001. http://dx.doi.org/10.1088/1674-4926/38/11/115001.

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Mintzer, Les. "FIR filters with field-programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 2 (August 1993): 119–27. http://dx.doi.org/10.1007/bf01607876.

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Louie, Marianne E., and Milos D. Ercegovac. "Implementing division with field programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 7, no. 3 (October 1994): 271–85. http://dx.doi.org/10.1007/bf02409403.

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Portniagin, N. N., Y. V. Repina, and V. N. Portniagin. "Field-Programmable Gate Arrays: Application in the Digital Signal Processing." Journal of Computational and Theoretical Nanoscience 16, no. 7 (July 1, 2019): 2900–2906. http://dx.doi.org/10.1166/jctn.2019.8193.

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Hall, T. S., C. M. Twigg, J. D. Gray, P. Hasler, and D. V. Anderson. "Large-scale field-programmable analog arrays for analog signal processing." IEEE Transactions on Circuits and Systems I: Regular Papers 52, no. 11 (November 2005): 2298–307. http://dx.doi.org/10.1109/tcsi.2005.853401.

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Sugimoto, Yohei, Satoru Ozawa, and Noriyasu Inaba. "Spaceborne synthetic aperture radar signal processing using field-programmable gate arrays." Journal of Applied Remote Sensing 12, no. 03 (July 25, 2018): 1. http://dx.doi.org/10.1117/1.jrs.12.035007.

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Deng, Jun, Hua Yong Tan, Lun Cai Liu, and Lin Tao Liu. "Research of a Mixed-Signal Programmable SoC Based on FPAA." Applied Mechanics and Materials 556-562 (May 2014): 1741–44. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1741.

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This paper presents a novel architecture for mixed-signal SoC, which integrates a Field Programmable Analog Array (FPAA) into a SoC based on 32-bit RISC CPU. The FPAA unit can be configured as Filter, Comparator, Gain Amplifier, and so on. The proposed mixed-signal SoC can transform the intermediate frequency (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing, besides this, which can transmit the modulated IF signals which are converted from baseband signals by digital up-conversion (DUC). The proposed mixed-signal SoC is a transceiver on chip actually, due to the internal integrated IPs, such as ADC, DAC, DDC and DUC, which can provide smaller board area, lower power consumption and the system cost for the product development of transceiver. This design will have a good potential for wireless communication applications.

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Tan, H., M. Walby, W. Hennig, W. Warburton, P. Grudberg, C. Reintsema, D. Bennett, W. Doriese, and J. Ullom. "A Digital Signal Processing Module for Time-Division Multiplexed Microcalorimeter Arrays." Applied Superconductivity, IEEE Transactions on 23, no. 3 (January 2013): 2500305. http://dx.doi.org/10.1109/tasc.2012.2236632.

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We have developed a digital signal processing module for real time processing of time-division multiplexed data from SQUID-coupled transition-edge sensor microcalorimeter arrays. It is a 3U PXI card consisting of a standardized core processor board and a daughter board. Through fiber-optic links on its front panel, the daughter board receives time-division multiplexed data (comprising error and feedback signals) and clocks from the digital-feedback cards developed at the National Institute of Standards and Technology. After mixing the error signal with the feedback signal in a field-programmable gate array, the daughter board transmits demultiplexed data to the core processor. Real-time processing in the field-programmable gate array of the core processor board includes pulse detection, pileup inspection, pulse height computation, and histogramming into on-board spectrum memory. Data from up to 128 microcalorimeter pixels can be processed by a single module in real time. Energy spectra, waveform, and run statistics data can be read out in real time through the PCI bus by a host computer at a maximum rate of ~100 MB/s. The module's hardware architecture, mechanism for synchronizing with NIST's digital-feedback, and count rate capability are presented.

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Bojja Venkatakrishnan, Satheesh, Elias A. Alwan, and John L. Volakis. "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer." International Journal of Reconfigurable Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/7802735.

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

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Suszynski, R., and K. Wawryn. "Rapid prototyping of algorithmic A/D converters based on FPAA devices." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 3 (September 1, 2013): 691–96. http://dx.doi.org/10.2478/bpasts-2013-0073.

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Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.

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Snider, Ross K., Trevor Vannoy, James Eaton, Matthew Blunt, E. Bailey Galacci, Justin Williams, and Tyler B. Davis. "Real-time audio signal processing using system-on-chip field programmable gate arrays." Journal of the Acoustical Society of America 146, no. 4 (October 2019): 2879. http://dx.doi.org/10.1121/1.5136987.

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Halupka, David, Alireza Seyed Rabi, Parham Aarabi, and Ali Sheikholeslami. "Low-Power Dual-Microphone Speech Enhancement Using Field Programmable Gate Arrays." IEEE Transactions on Signal Processing 55, no. 7 (July 2007): 3526–35. http://dx.doi.org/10.1109/tsp.2007.893918.

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Le, Khoa N., Ivan W. H. Fung, Vivian W. Y. Tam, Leslie Yip, and Eric W. M. Lee. "Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays." International Journal of Information Technology Project Management 5, no. 4 (October 2014): 24–49. http://dx.doi.org/10.4018/ijitpm.2014100102.

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Genetic algorithms (GAs) have found many applications in various fields such as physics, signal processing, artificial intelligence and recently construction engineering management. For a long time, GAs are usually criticized to be time-consuming, making it unpractical for real-time applications. This paper presents a new technique which can be used: (1) to automate construction activities, and (2) to improve building information modeling which has become an attractive research topic around the world. Different from the generic GA techniques employed in the literature, this paper proposes a new GA using hardware with field-programmable gate arrays. The proposed technique is shown to improve speed and lessen computational power. Hardware implementation of GA using static random access memory-based field-programmable gate arrays with synthesizable very hardware description language coding is introduced. Detailed analyses on the field-programmable gate arrays are given which show that it is suitable for real-time applications. As a result, GA is modified so that it can be implemented in series and parallel which can greatly improve computational hardware performance. Configuration of parallelization is available with a peripheral component interconnect interface, which further helps to form a fast optimization tool for real-time applications. The ultimate goal of this paper is thus to design an effective GA technique which can be employed to support building information modeling and to effectively automate critical processes in construction projects.

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CROSBIE, ROY. "USING FIELD-PROGRAMMABLE GATE ARRAYS FOR HIGH-SPEED REAL-TIME SIMULATION." International Journal of Modeling, Simulation, and Scientific Computing 01, no. 01 (March 2010): 99–115. http://dx.doi.org/10.1142/s1793962310000031.

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Some applications of real-time simulation now require frame times that are shorter in duration than can be delivered by traditional methods such as real-time versions of Linux (RT-Linux). RT-Linux can be satisfactory for frames as short as 10μS, but there is now a need, for example in the simulation of power-electronic systems, for frame times as short as 1 μS or even less. Techniques based on the interfacing of digital signal processors (DSPs) to a Windows PC have achieved a 2 μS frame time for a typical power electronics application and less than 1 μS is shown to be possible using field-programmable gate arrays (FPGAs). Combining these high-speed techniques with simulations of the rest of the system necessitates the use of multi-rate techniques. Software tools, interfacing issues, and system architecture for a high-speed, real-time, distributed, multi-rate (HRDM) simulator are discussed.

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Saleh, Shukur Bin, Sulaiman Bin Mazlan, Nik Iskandar Bin Hamzah, Ahmad Zahid Zakwan Bin Abdul Karim, Mohd Shamian Bin Zainal, Shipun Anuar Bin Hamzah, Danial Bin Md Nor, and Hazwaj Bin Mhd Poad. "Smart Home Security Access System Using Field Programmable Gate Arrays." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (July 1, 2018): 152. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp152-160.

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Nowadays, the rapid growth of burglary and theft cases over the world has been threatening to the vulnerability of traditional home security systems. Therefore the development home security with intelligent control wherein focus to enhance conventional technique to theadvanced digital security systemand to be more interestinginhome or building owner for preventing intruders in smart home implementation. However, using avariety of type conventional lock doors for security purposes and analog intruder sensor with individual function system is not secure enoughin order to protect the person or company properties. That why the emergence of new technology such as integrated circuit network will apply in Smart Home system for abetter security solution to prevent the houses from theintruder and hazardous fire incident. Therefore, this project is done to design and build a smart system with consist of digital security entry for automatic lock doors and also for activating or deactivate all security sensor in houses which is function for detecting the irregular movement and hot temperature (fire incident) in-house for the domestic residential sector. This product includeswith doors automatic lock system using servo motor and detect irregular movement intruder using PIR motion sensor (HC-SR501) and also measure hot temperature using temperature sensor (LM35). The sensor will transmit theanalog signal to Field Programmable Gate Array (FPGA) the Altera DE2-115 board to be processed and which will then display the status entry after key-in password and activation security system on the LED seven segment displays. The entry login controller will use apush button or switchesavailable on FPGA board that are used to login password for automatic door accessand also able maintained for control home smart security system.

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Bamford, Simeon A., Roni Hogri, Andrea Giovannucci, Aryeh H. Taub, Ivan Herreros, Paul F. M. J. Verschure, Matti Mintz, and Paolo Del Giudice. "A VLSI Field-Programmable Mixed-Signal Array to Perform Neural Signal Processing and Neural Modeling in a Prosthetic System." IEEE Transactions on Neural Systems and Rehabilitation Engineering 20, no. 4 (July 2012): 455–67. http://dx.doi.org/10.1109/tnsre.2012.2187933.

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Hall, T. S., and D. V. Anderson. "A Framework for Teaching Real-Time Digital Signal Processing With Field-Programmable Gate Arrays." IEEE Transactions on Education 48, no. 3 (August 2005): 551–58. http://dx.doi.org/10.1109/te.2005.853069.

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Meyer-Base, Uwe, Alonzo Vera, Anke Meyer-Base, Marios S. Pattichis, and Reginald J. Perry. "An Undergraduate Course and Laboratory in Digital Signal Processing With Field Programmable Gate Arrays." IEEE Transactions on Education 53, no. 4 (November 2010): 638–45. http://dx.doi.org/10.1109/te.2009.2039216.

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Kulakovskis, Darius. "INTRAVENINIO GLIUKOZĖS TOLERANCIJOS TESTO METABOLINĖS P SISTEMOS ĮGYVENDINIMAS APIBENDRINTUOJU KOMBINACINIU BŪDU / INTRAVENOUS GLUCOSE TOLERANCE TEST METABOLIC P SYSTEM IMPLEMENTED USING UNIFIED COMBINATIVE TECHNIQUE." Mokslas - Lietuvos ateitis 11 (April 15, 2019): 1–5. http://dx.doi.org/10.3846/mla.2019.9429.

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Metabolic P (MP) systems are a part of the infobiotics research field. The intravenous glucose tolerance test (IVGTT) MP system models glucose-insulin interactions. MP system implementation in software is well researched, although there is a lack of techniques for hardware implementation, specifically with field programmable gate arrays. In this article the existing techniques are examined first, including combinative, single digital signal processor element, and pipelined. Then the specifics of six different IVGTT MP systems are analyzed. Having in mind these specifics, a new unified combinative IVGTT MP system implementation in field programmable gate arrays is proposed. Carried out experimental investigation results confirm, that the proposed unified system in comparison with single IVGTT MP systems, uses 36% less digital signal processor and 49% less look-up table resources of the field programmable gate arrays. Santrauka Metabolinė P (MP) sistema yra naujos infobiotikos mokslo srities dalis. Intraveninio gliukozės tolerancijos testo (IVGTT) MP sistema modeliuojama gliukozės ir insulino sąveika. MP sistemų įgyvendinimas programinėmis priemonėmis yra gerai ištirtas, tačiau trūksta MP sistemoms įgyvendinti aparatinėje įrangoje, konkrečiai – lauku programuojamose loginėse matricose (LPLM), skirtų metodų. Šiame straipsnyje iš pradžių aptariami taikytini žinomi įgyvendinimo būdai: kombinacinis, vieno skaitmeninio signalų apdorojimo elemento ir srautinis. Vėliau nagrinėjamos šešios skirtingos IVGTT MP sistemos ir nustatomi jų ypatumai. Atsižvelgiant į bendras IVGTT MP sistemų savybes, pasiūlomas naujas apibendrintas kombinacinis IVGTT MP sistemų įgyvendinimo būdas, kuris sujungia visas minėtas sistemas vienoje LPLM. Palyginus apibendrintą sistemą su atskiromis IVGTT MP sistemomis, nustatyta, kad apibendrinta sistema naudoja 36 % mažiau skaitmeninių signalų apdorojimo elementų ir 49 % mažiau peržvalgos lentelių visoms šešioms žinomoms IVGTT MP sistemoms apskaičiuoti.

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KOCZ, J., L. J. GREENHILL, B. R. BARSDELL, G. BERNARDI, A. JAMESON, M. A. CLARK, J. CRAIG, et al. "A SCALABLE HYBRID FPGA/GPU FX CORRELATOR." Journal of Astronomical Instrumentation 03, no. 01 (March 2014): 1450002. http://dx.doi.org/10.1142/s2251171714500020.

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Radio astronomical imaging arrays comprising large numbers of antennas, O(102–103), have posed a signal processing challenge because of the required O (N2) cross correlation of signals from each antenna and requisite signal routing. This motivated the implementation of a Packetized Correlator architecture that applies Field Programmable Gate Arrays (FPGAs) to the O (N) "F-stage" transforming time domain to frequency domain data, and Graphics Processing Units (GPUs) to the O (N2) "X-stage" performing an outer product among spectra for each antenna. The design is readily scalable to at least O(103) antennas. Fringes, visibility amplitudes and sky image results obtained during field testing are presented.

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Peng, Bo, Guang Min Sun, and De Qun Zhao. "Design of Transient Electromagnetic Signal Acquisition System Based on FPGA." Applied Mechanics and Materials 602-605 (August 2014): 2184–87. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2184.

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An acquisition system applying in transient electromagnetic method (TEM) receiver has been designed in this paper. The accuracy of acquisition has been improved by using a floating-point A/D with high input dynamic range, which is composed of programmable gain amplifiers (PGA) and a dual-channel 16 bit resolution ADC. The real-time performance can be ensured by using a field-programmable gate arrays (FPGA) as the main control unit to control ADC, PGA, data storage and communication interface. By integrating a soft core CPU, Nios II, in FPGA, the complexity of circuit design was decreased, and the work efficiency of system was improved. This system, which has good performance of real-time and high integration level, can meet the needs of TEM signal acquisition.

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Zhang, Xiao‐Wei, Lei Zuo, Wen‐Zhun Huang, and Jian‐Xin Guo. "Efficient method for the field‐programmable gate arrays calculation of Wigner‐Ville distribution." IET Signal Processing 13, no. 6 (August 2019): 589–95. http://dx.doi.org/10.1049/iet-spr.2018.5522.

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Vandenbussche, Jean‐Jacques, Peter Lee, and Joan Peuteman. "Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays." IET Signal Processing 9, no. 5 (July 2015): 449–56. http://dx.doi.org/10.1049/iet-spr.2014.0143.

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Hasler, Jennifer, Aishwarya Natarajan, and Sihwan Kim. "Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse." Journal of Low Power Electronics and Applications 8, no. 4 (November 24, 2018): 47. http://dx.doi.org/10.3390/jlpea8040047.

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This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. Abstraction is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches.

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Lee, Edmund, Guy Lemieux, and Shahriar Mirabbasi. "Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays." Journal of Signal Processing Systems 51, no. 1 (October 4, 2007): 57–76. http://dx.doi.org/10.1007/s11265-007-0141-y.

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Sinha, Amitabha, Soumojit Acharyya, Suranjan Chakraborty, and Mitrava Sarkar. "Field Programmable DSP Arrays - A Novel Reconfigurable Architecture for Efficient Reliazation of Digital Signal Processing Functions." Signal & Image Processing : An International Journal 4, no. 2 (April 30, 2013): 41–58. http://dx.doi.org/10.5121/sipij.2013.4204.

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Pandiev, Ivailo M., and Mariya P. Aleksandrova. "Dynamic FPAA-based Mixed-Signal Processing Circuit for Thin-Film CdTe/Lead-Free Perovskite Photodetectors." Elektronika ir Elektrotechnika 27, no. 2 (April 29, 2021): 22–30. http://dx.doi.org/10.5755/j02.eie.28751.

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New photodetector structure combining thinned CdTe film with lead-free perovskite photoelectric film was produced and investigated. This setting of the CdTe thickness results in photodetector parameters’ competitiveness to the state-of-the-art in the field of advanced photoelectric materials. The device shows a promising sensitivity of ~40 μA/W, maximum responsivity of 10.6 mA/W at 460 nm, equal rise and fall times of 30 ms, and high linearity (maximum linearization error is less than 0.6 %). However, the optoelectronic performance of CdTe/lead-free perovskite structures integrated with signal processing circuit remains unexplored. For this purpose, Field Programmable Analogue Array (FPAA)-based mixed-signal processing circuit is developed for pulse width modulated electrical signal with duty cycle controlled by the illumination degree of the detecting photoelement. This novel approach guarantees a smooth change of the electrical output at a smooth change of the input illumination between the light and dark switching states and can be practically applied as a precise position detector of moving objects. The paper represents a synergistic connection between microelectronics, electronics, and signal technology.

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Barkalov, Alexander, Larysa Titarenko, and Sławomir Chmielewski. "Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs." Journal of Circuits, Systems and Computers 28, no. 08 (July 2019): 1950131. http://dx.doi.org/10.1142/s0218126619501317.

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A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.

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da Silva, Bruno, An Braeken, and Abdellah Touhafi. "FPGA-Based Architectures for Acoustic Beamforming with Microphone Arrays: Trends, Challenges and Research Opportunities." Computers 7, no. 3 (August 3, 2018): 41. http://dx.doi.org/10.3390/computers7030041.

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Over the past decades, many systems composed of arrays of microphones have been developed to satisfy the quality demanded by acoustic applications. Such microphone arrays are sound acquisition systems composed of multiple microphones used to sample the sound field with spatial diversity. The relatively recent adoption of Field-Programmable Gate Arrays (FPGAs) to manage the audio data samples and to perform the signal processing operations such as filtering or beamforming has lead to customizable architectures able to satisfy the most demanding computational, power or performance acoustic applications. The presented work provides an overview of the current FPGA-based architectures and how FPGAs are exploited for different acoustic applications. Current trends on the use of this technology, pending challenges and open research opportunities on the use of FPGAs for acoustic applications using microphone arrays are presented and discussed.

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ROSENDAHL, G. K., R. D. MCLEOD, and H. C. CARD. "A DSP–FPGA-BASED RECONFIGURABLE COMPUTER." Journal of Circuits, Systems and Computers 08, no. 04 (August 1998): 453–59. http://dx.doi.org/10.1142/s0218126698000250.

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In order to exploit architectural advantages associated with specific computations while at the same time having flexibility in those computations, we have designed a reconfigurable parallel machine architecture. A prototype reconfigurable computer has been constructed based on digital signal processing (DSP) chips and field-programmable gate arrays (FPGAs). Communications are based upon a broadcast network that employs FPGA-based message pre-processing and post-processing. Tradeoffs between computational and communication performance are made possible by software reconfiguration of the FPGAs. The system has been successfully tested on several applications in signal processing.

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Nauber, Richard, Lars Büttner, and Jürgen Czarske. "Measurement uncertainty analysis of field-programmable gate-array-based, real-time signal processing for ultrasound flow imaging." Journal of Sensors and Sensor Systems 9, no. 2 (July 31, 2020): 227–38. http://dx.doi.org/10.5194/jsss-9-227-2020.

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Abstract. Research in magnetohydrodynamics (MHD) aims to understand the complex interactions of electrically conductive fluids and magnetic fields. A promising approach for investigating complex instationary flow phenomena are lab-scale experiments with low-melting alloys. They require a noninvasive flow instrumentation for opaque liquids with a high spatiotemporal resolution, a low velocity uncertainty and a long measurement duration. Ultrasound Doppler velocimetry can achieve multiplane, multicomponential flow imaging with multiple linear ultrasound arrays. However the average raw data output amounts to 1.2 GBs−1 at a frame rate of 33 Hz in a typical configuration for 200 transducers. This usually prevents long-duration measurements when offline signal processing is used. In this paper, we propose an online signal-processing chain for pulsed-wave Doppler velocimetry that is tailored to the specific requirements of flow imaging for lab-scale experiments. The trade-off between measurement uncertainty and computational complexity is evaluated for different algorithmic variants in relation to the Cramér–Rao bound. By utilizing selected approximations and parameter choices, a prepossessing could be efficiently implemented on a field-programmable gate array (FPGA), enabling a typical reduction of the data bandwidth of 6.5:1 and online flow visualization. We validated the performance of the signal processing on a test rig, yielding a velocity standard deviation that is a factor of 3 above the theoretical limit despite a low computational complexity. Potential applications for this signal processing include multihour flow measurements during a crystal-growth process and closed-loop velocity feedback for model experiments.

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Kocz, J., L. J. Greenhill, B. R. Barsdell, D. Price, G. Bernardi, S. Bourke, M. A. Clark, et al. "Digital Signal Processing Using Stream High Performance Computing." Journal of Astronomical Instrumentation 04, no. 01n02 (June 2015): 1550003. http://dx.doi.org/10.1142/s2251171715500038.

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A “large-N” correlator that makes use of Field Programmable Gate Arrays and Graphics Processing Units has been deployed as the digital signal processing system for the Long Wavelength Array station at Owens Valley Radio Observatory (LWA-OV), to enable the Large Aperture Experiment to Detect the Dark Ages (LEDA). The system samples a [Formula: see text][Formula: see text]MHz baseband and processes signals from 512 antennas (256 dual polarization) over a [Formula: see text][Formula: see text]MHz instantaneous sub-band, achieving 16.8[Formula: see text]Tops[Formula: see text]s[Formula: see text] and 0.236 Tbit[Formula: see text]s[Formula: see text] throughput in a 9[Formula: see text]kW envelope and single rack footprint. The output data rate is 260 MB[Formula: see text]s[Formula: see text] for 9-s time averaging of cross-power and 1[Formula: see text]s averaging of total power data. At deployment, the LWA-OV correlator was the largest in production in terms of N and is the third largest in terms of complex multiply accumulations, after the Very Large Array and Atacama Large Millimeter Array. The correlator’s comparatively fast development time and low cost establish a practical foundation for the scalability of a modular, heterogeneous, computing architecture.

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Callegari, Sergio, Giuseppe Merendino, Alessandro Golfarelli, Michele Zagnoni, and Marco Tartagni. "Applicability of Field Programmable Analog Arrays to Capacitive Sensing in the Sub-pF Range." Analog Integrated Circuits and Signal Processing 47, no. 1 (April 2006): 39–51. http://dx.doi.org/10.1007/s10470-006-2776-1.

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Snider, Ross K., Christopher N. Casebeer, and Raymond J. Weber. "An open computational platform for low-latency real-time audio signal processing using field programmable gate arrays." Journal of the Acoustical Society of America 143, no. 3 (March 2018): 1737. http://dx.doi.org/10.1121/1.5035667.

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Bhattacharyya, Swagat, Steven Andryzcik, and David W. Graham. "An Acoustic Vehicle Detector and Classifier Using a Reconfigurable Analog/Mixed-Signal Platform." Journal of Low Power Electronics and Applications 10, no. 1 (February 20, 2020): 6. http://dx.doi.org/10.3390/jlpea10010006.

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The wireless sensor nodes used in a growing number of remote sensing applications are deployed in inaccessible locations or are subjected to severe energy constraints. Audio-based sensing offers flexibility in node placement and is popular in low-power schemes. Thus, in this paper, a node architecture with low power consumption and in-the-field reconfigurability is evaluated in the context of an acoustic vehicle detection and classification (hereafter “AVDC”) scenario. The proposed architecture utilizes an always-on field-programmable analog array (FPAA) as a low-power event detector to selectively wake a microcontroller unit (MCU) when a significant event is detected. When awoken, the MCU verifies the vehicle class asserted by the FPAA and transmits the relevant information. The AVDC system is trained by solving a classification problem using a lexicographic, nonlinear programming algorithm. On a testing dataset comprising of data from ten cars, ten trucks, and 40 s of wind noise, the AVDC system has a detection accuracy of 100%, a classification accuracy of 95%, and no false alarms. The mean power draw of the FPAA is 43 μ W and the mean power consumption of the MCU and radio during its validation and wireless transmission process is 40.9 mW. Overall, this paper demonstrates that the utilization of an FPAA-based signal preprocessor can greatly improve the flexibility and power consumption of wireless sensor nodes.

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Figuli, Shalina Percy Delicia, Peter Figuli, Alberto Sonnino, and Juergen Becker. "A Generic Reconfigurable Mixed Time and Frequency Domain QAM Transmitter with Forward Error Correction." International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems 6, no. 2 (July 13, 2017): 80. http://dx.doi.org/10.11601/ijates.v6i2.219.

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In the past three decades, Field Programmable Gate Arrays (FPGAs) have emerged to be the backbone of digital signal processing, especially in high-speed communication systems. However, today, these devices are clocked below 1GHz and improvement in performance stays a big challenge on all abstraction layers, right from system architecture down to physical technology. Far and wide, myriad number of researches are done on methodologies and techniques which can deliver higher throughput with lower operating frequencies. Towards this projected objective, in this paper an efficient modulation technique like Quadrature Amplitude Modulation (QAM) along with mixed time and frequency domain approach and Forward Error Correction (FEC) technique have been utilized to employ a generic scalable FPGA based QAM transmitter with filter parallelization being executed in mixed domain. The system developed in this paper achieves an effective throughput of 12.8Gb/s for 256-QAM with 16 parallel inputs having an operating frequency of 201.25MHz, while a 18.7Gb/s effective throughput is realized with 32 parallel inputs at 146MHz. Thereby, it paves down a promising methodology for applications where having higher clock frequencies is a hard limit.

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ZAHARIADIS, Th, S. APOSTOLACOS, I. GRAMMATIKAKIS, D. MEXIS, N. ZERVOS, and N. VOGIATZIS. "BLOCK FLOATING POINT FFT IMPLEMENTATION FOR DMT xDSL SYSTEMS." Journal of Circuits, Systems and Computers 13, no. 05 (October 2004): 1147–64. http://dx.doi.org/10.1142/s0218126604001878.

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The development of multiple Discrete Multitone (DMT) Digital Subscriber Line (DSL) flavors on a single platform can benefit considerably by a programmable architecture, which feature Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA), especially when fast prototyping is targeted. However, the flexibility assumed to be offered by algorithmic partitioning does not automatically and proportionally simplify the digital signal processing algorithms, unless the effects of overflow/saturation in intermediate processing stages are carefully studied. The effects of overflow/saturation in intermediate stages is very critical throughout the design process, since the operations involved are nonlinear in nature and affect the most significant bits of the computational process. This paper presents an efficient soft-core implementation of a Block Floating Point FFT (BLFP) algorithm, designed for a Very high-speed DSL (VDSL) DMT systems and for the full variety of other xDSL DMT flavors, as the latter demand an extended dynamic range to achieve performance that may otherwise be only warranted by costly floating-point chip implementations.

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Huang, Yong Yi, and Jian Feng Zhou. "The Characters of Dual Harmonic Frames of Subspaces and Applications in Signal Processing Theory." Applied Mechanics and Materials 457-458 (October 2013): 731–35. http://dx.doi.org/10.4028/www.scientific.net/amm.457-458.731.

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Digital signal processing is the processing of digitized discrete-time samp-led signals. Processing is done by general-purpose computers or by digital circuits such as ASICs, field-programmable gate arrays or specialized digital signal processors. Information science focuses on understanding problems from the perspective of the stakeholders involved and then applying information and other technologies as needed. The definition of multiple pseudofames for subspaces with integer translation is proposed. The notion of a generalized multiresolution structure (GMS) of is also introduced. The construction of a generalized multiresolution structure of Paley-Wiener subspaces of is investigated. The pyramid decomposition scheme is derived based on a generalized multiresolution structure.

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Reddy, Naresh Kumar, and N. Suresh. "An Efficient approach for Design and Testing of FPGA Programming using LabVIEW." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 192. http://dx.doi.org/10.11591/ijres.v4.i3.pp192-200.

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Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.

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Wang, Yan Long, Jun Hua Zhang, Lu Lu Bu, Jun Yang, and Xin Ling Shi. "Flow Measurement with Digital Correlator Realized by FPGA." Advanced Materials Research 462 (February 2012): 641–46. http://dx.doi.org/10.4028/www.scientific.net/amr.462.641.

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Cross correlator is the core device of the cross-correlation flow measurement system. This paper describes the theory of the cross-correlation flow measurement system and realizes the digital correlator for flow measurement based on field programmable gate arrays (FPGA). The correlation algorithm is realized by verilog language, and the result of Modelsim simulation shows that this correlator can be used to calculate the cross functions of random signal. This correlator which has a simple hardware structure, high reliability and high accuracy, can meet the demand of the real-time flow measurement system.

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Kumar Reddy, B. Naresh, N. Suresh, and J. V. N. Ramesh. "A Gracefully Degrading and Energy-Efﬁcient FPGA Programming using LabVIEW." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (November 1, 2016): 165. http://dx.doi.org/10.11591/ijres.v5.i3.pp165-175.

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<p>Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.</p>

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Vandendriessche, Jurgen, Bruno da Silva, Lancelot Lhoest, An Braeken, and Abdellah Touhafi. "M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera." Electronics 10, no. 3 (January 29, 2021): 317. http://dx.doi.org/10.3390/electronics10030317.

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Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints.

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Han, Haopeng, Thomas Wilhelm Eigentler, Shuailin Wang, Egor Kretov, Lukas Winter, Werner Hoffmann, Eckhard Grass, and Thoralf Niendorf. "Design, Implementation, Evaluation and Application of a 32-Channel Radio Frequency Signal Generator for Thermal Magnetic Resonance Based Anti-Cancer Treatment." Cancers 12, no. 7 (June 28, 2020): 1720. http://dx.doi.org/10.3390/cancers12071720.

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Thermal Magnetic Resonance (ThermalMR) leverages radio frequency (RF)-induced heating to examine the role of temperature in biological systems and disease. To advance RF heating with multi-channel RF antenna arrays and overcome the shortcomings of current RF signal sources, this work reports on a 32-channel modular signal generator (SGPLL). The SGPLL was designed around phase-locked loop (PLL) chips and a field-programmable gate array chip. To examine the system properties, switching/settling times, accuracy of RF power level and phase shifting were characterized. Electric field manipulation was successfully demonstrated in deionized water. RF heating was conducted in a phantom setup using self-grounded bow-tie RF antennae driven by the SGPLL. Commercial signal generators limited to a lower number of RF channels were used for comparison. RF heating was evaluated with numerical temperature simulations and experimentally validated with MR thermometry. Numerical temperature simulations and heating experiments controlled by the SGPLL revealed the same RF interference patterns. Upon RF heating similar temperature changes across the phantom were observed for the SGPLL and for the commercial devices. To conclude, this work presents the first 32-channel modular signal source for RF heating. The large number of coherent RF channels, wide frequency range and accurate phase shift provided by the SGPLL form a technological basis for ThermalMR controlled hyperthermia anti-cancer treatment.

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Price, D. C., J. Kocz, M. Bailes, and L. J. Greenhill. "Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy." Journal of Astronomical Instrumentation 05, no. 04 (December 2016): 1602002. http://dx.doi.org/10.1142/s2251171716020025.

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Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

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Buch, Kaushal D., Yashwant Gupta, and B. Ajith Kumar. "Variable Correlation Digital Noise Source on FPGA — A Versatile Tool for Debugging Radio Telescope Backends." Journal of Astronomical Instrumentation 03, no. 03n04 (December 2014): 1450007. http://dx.doi.org/10.1142/s225117171450007x.

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Contemporary wideband radio telescope backends are generally developed on Field Programmable Gate Arrays (FPGA) or hybrid (FPGA+GPU) platforms. One of the challenges faced while developing such instruments is the functional verification of the signal processing backend at various stages of development. In the case of an interferometer or pulsar backend, the typical requirement is for one independent noise source per input, with provision for a common, correlated signal component across all the inputs, with controllable level of correlation. This paper describes the design of a FPGA-based variable correlation Digital Noise Source (DNS), and its applications to built-in testing and debugging of correlators and beamformers. This DNS uses the Central Limit Theorem-based approach for generation of Gaussian noise, and the architecture is optimized for resource requirements and ease of integration with existing signal processing blocks on FPGA.

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Leon, Vasileios, George Lentaris, Evangelos Petrongonas, Dimitrios Soudris, Gianluca Furano, Antonis Tavoularis, and David Moloney. "Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC." ACM Transactions on Embedded Computing Systems 20, no. 3 (April 2021): 1–23. http://dx.doi.org/10.1145/3440885.

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The advent of powerful edge devices and AI algorithms has already revolutionized many terrestrial applications; however, for both technical and historical reasons, the space industry is still striving to adopt these key enabling technologies in new mission concepts. In this context, the current work evaluates an heterogeneous multi-core system-on-chip processor for use on-board future spacecraft to support novel, computationally demanding digital signal processors and AI functionalities. Given the importance of low power consumption in satellites, we consider the Intel Movidius Myriad2 system-on-chip and focus on SW development and performance aspects. We design a methodology and framework to accommodate efficient partitioning, mapping, parallelization, code optimization, and tuning of complex algorithms. Furthermore, we propose an avionics architecture combining this commercial off-the-shelf chip with a field programmable gate array device to facilitate, among others, interfacing with traditional space instruments via SpaceWire transcoding. We prototype our architecture in the lab targeting vision-based navigation tasks. We implement a representative computer vision pipeline to track the 6D pose of ENVISAT using megapixel images during hypothetical spacecraft proximity operations. Overall, we achieve 2.6 to 4.9 FPS with only 0.8 to 1.1 W on Myriad2 , i.e., 10-fold acceleration versus modern rad-hard processors. Based on the results, we assess various benefits of utilizing Myriad2 instead of conventional field programmable gate arrays and CPUs.

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Kelly, Jamie S., Vittal S. Rao, Hardy J. Pottinger, and H. Clifford Bowman. "Design and implementation of digital controllers for smart structures using field programmable gate arrays." Smart Materials and Structures 6, no. 5 (October 1, 1997): 559–72. http://dx.doi.org/10.1088/0964-1726/6/5/007.

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Zhao, Yizhen, Xinhua Wang, Mingfei Wang, Yu Duan, Lin Yang, Qingfeng Pan, and Xuyun Yang. "Harmonic Detection System and Identification Algorithm for Steel Pipeline Defects." European Journal of Electrical Engineering 23, no. 1 (February 28, 2021): 17–26. http://dx.doi.org/10.18280/ejee.230103.

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Aiming at the problem of defects detection of steel pipeline, a harmonic detection system was developed based on electromagnetic principle, and the target signal identification algorithm was studied. The Advanced RISC Machine (ARM) Cortex-M3 was adopted to design digital adjustable harmonic excitation source, and its effective output power can up to 70 W. The Field Programmable Gate Arrays (FPGA) and ARM Cortex-M4 were introduced to design 15 channels high speed data collector, which parallel local-storage rate of each channel can reach 4.7 kHz. The electromagnetic focusing excitation array and Tunnel Magneto Resistance (TMR) sensors array were constructed to improve the spatial resolution of the detection system. Meanwhile, the system also integrated GPS positioning and LCD real-time display functions. Furthermore, the algorithm combining Empirical Mode Decomposition (EMD) and variable-scale Stochastic Resonance (SR) was proposed to process signal and enhance the targets. The effectiveness of the instrument and algorithm are well verified in both simulation and experiment. The results show that this method has higher integration and better detection effect, which provides a novel method for non-contact detection of metal material defects and is suitable for engineering applications.

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Journal articles on the topic 'Field programmable mixed-signal arrays'

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