Relevant bibliographies by topics / Filed Programmable Gate Array (FPGA)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Filed Programmable Gate Array (FPGA)'

Author: Grafiati
Published: 7 June 2025
Last updated: 2 August 2025

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Journal articles on the topic "Filed Programmable Gate Array (FPGA)"

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krishna, Mr P. V. Murali, and Kantumajji Navyasri. "ACCELERATING HIGH-PERFORMANCE VOLTAGE SOURCE INVERTER PROTOTYPING WITH FPGA IMPLEMENTATION." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (2023): 1–10. http://dx.doi.org/10.55041/ijsrem27818.

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This paper highlights the advantages of FPGA-based rapid prototyping as a powerful tool for accelerating the development cycle of high-performance Voltage Source Inverters. By providing a flexible and efficient platform for algorithm testing, hardware evaluation, and performance optimization, it contributes to advancements in power electronics and facilitates the deployment of robust VSIs in diverse application domains. Through extensive experimentation, we demonstrate the effectiveness of the FPGA-based rapid prototyping platform in achieving high- performance VSI control. The FPGA's real-tim
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Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, and Rahul Khanna. "Field Programmable Gate Array Applications—A Scientometric Review." Computation 7, no. 4 (2019): 63. http://dx.doi.org/10.3390/computation7040063.

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram
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Xu, Heyang. "FPGA: The super chip in the age of artificial intelligence." Journal of Physics: Conference Series 2649, no. 1 (2023): 012018. http://dx.doi.org/10.1088/1742-6596/2649/1/012018.

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Abstract In modern society, artificial intelligence (AI) is developing more rapidly. And the Field Programmable Gate Array (FPGA) has always been the focus of research as a driving platform. This paper studies in detail the theoretical basis, applications, defects, and future development directions of FPGAs. It is concluded that FPGA has three characteristics: gate array, programmable, and scene, and the detailed positioning of FPGA, the structure, principle, tools, process, and description language of FPGA design. And the unique advantages of FPGA in the field of artificial intelligence: flex
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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier inje
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., Karthik S. "REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB." International Journal of Research in Engineering and Technology 03, no. 04 (2014): 842–45. http://dx.doi.org/10.15623/ijret.2014.0304149.

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Chen, Yonghao, Tianrui Li, Xiaojie Chen, ZhiGang Cai, and Tao Su. "High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays." Electronics 12, no. 4 (2023): 822. http://dx.doi.org/10.3390/electronics12040822.

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The systolic array is frequently used in accelerators for neural networks, including Transformer models that have recently achieved remarkable progress in natural language processing (NLP) and machine translation. Due to the constraints of FPGA EDA (Field Programmable Gate Array Electronic Design Automation) tools and the limitations of design methodology, existing systolic array accelerators for FPGA deployment often cannot achieve high frequency. In this work, we propose a well-designed high-frequency systolic array for an FPGA-based Transformer accelerator, which is capable of performing th
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Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

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A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acqu
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Jamro, Ernest, Maciej Wielgosz, Sławomir Bieniasz, and Witold Cioch. "FPGA – ARM Heterogeneous System for High Speed Signal Analysis." Solid State Phenomena 180 (November 2011): 207–13. http://dx.doi.org/10.4028/www.scientific.net/ssp.180.207.

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This paper presents a version 2 of hardware solution denoted as Programmable Unit for Diagnostic (PUD-2) based on Filed Programmable Gate Arrays (FPGAs) and ARM-based OMAP3530 microprocessor adapted for diagnostic systems. The sampling frequency of the input analog signals and digital signals processing speed of the PUD is high beyond comparable DSP based systems. Employing ARM microprocessor allows for much quicker and easer design than only FPGA-based solution.
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Bhuvaneswari, Thangavel, Nor Hidayati Abdul Aziz, Jakir Hossen, and Chinthakunta Venkataseshaiah. "Field Programmable Gate Array (FPGA) Based Microwave Oven." Applied Mechanics and Materials 892 (June 2019): 120–26. http://dx.doi.org/10.4028/www.scientific.net/amm.892.120.

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In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms
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Govil, Anchal, Anmol Karnwal, Govinda Sindhu, Ayush Singh, and Dr Shubham Shukla. "Design and Implementation of UART Using FPGA Board." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (2022): 1187–90. http://dx.doi.org/10.22214/ijraset.2022.41478.

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Abstract: This paper introduces the implementation of the Universal Asynchronous Receiver- Transmitter Controller (UART) based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our UART design is fully functional and built-in. Coded using the Verilog design from top to bottom and visible in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. Use results show that the design can work Spartan-3E FPGA maximum clock frequency of 218.248 MHz. The maximum frequent use of the UART controller is 192.773 MHz. of bits and hence this is why with a small amount of storage. Keywords: Receive
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Dissertations / Theses on the topic "Filed Programmable Gate Array (FPGA)"

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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configur
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Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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Simmler, Harald C. "Preemptive multitasking auf FPGA-Prozessoren : ein Betriebssystem für FPGA-Prozessoren /." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9460961.

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Kornmesser, Klaus. "Das FPGA-Entwicklungssystem CHDL eine vollständige, C++-basierte Entwicklungsumgebung für FPGA-Koprozessoren /." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11612006.

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Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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HAWK, CHRISTOPHER J. "DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.

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Books on the topic "Filed Programmable Gate Array (FPGA)"

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David E. Van den Bout. FPGA workout: Beginning exercises with the Intel FLEXlogic FPGA. X Engineering Software Systems Corp., 1994.

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ACM, International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey Calif ). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM Press, 1999.

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ACM International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey, Calif.). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Association for Computing Machinery, 1999.

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ACM International Symposium on Field-Programmable Gate Arrays (9th 2001 Monterey, Calif.). FPGA '01: ACM/SIGDA International Symposium on Field Programmable Gate Arrays : Monterey, California, USA. Association for Computing Machinery, 2001.

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ACM International Symposium on Field-Programmable Gate Arrays (6th 1998 Monterey, Calif.). FPGA '98: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Association for Computing Machinery, 1998.

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ACM International Symposium on Field-Programmable Gate Arrays (10th 2002 Monterey, Calif.). FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA : February 24-26, 2002. ACM Press, 2002.

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ACM, International Symposium on Field-Programmable Gate Arrays (3rd 1995 Monterey Calif ). FPGA '95: 1995 ACM Third International Sympsosium on Field-Programmable Gate Arrays : February 12-14, 1995, Monterey Marriott, Monterey, California, USA. ACM Press, 1995.

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ACM, International Symposium on Field-Programmable Gate Arrays (17th 2009 Monterey Calif ). FPGA'09: Proceedings of the Seventeenth ACM SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2009. Association for Computing Machinery, 2009.

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ACM Special Interest Group on Design Automation, ed. FPGA '13: Proceedings of the 2013 ACM SIGDA International Symposium on Field Programmable Gate Arrays : February 11-13, 2013, Monterey, California, USA. Association for Computing Machinery, 2013.

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ACM International Symposium on Field-Programmable Gate Arrays (17th 2009 Monterey, Calif.). FPGA'09: Proceedings of the Seventeenth ACM SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2009. Association for Computing Machinery, 2009.

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Book chapters on the topic "Filed Programmable Gate Array (FPGA)"

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Bindal, Ahmet, and Sotoudeh Hamedi-Hagh. "Field-Programmable-Gate-Array (FPGA)." In Silicon Nanowire Transistors. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-27177-4_7.

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Pandey, Bishwajeet, and Keshav Kumar. "Field programmable gate arrays (FPGA)." In Green Communication with Field-programmable Gate Array for Sustainable Development. CRC Press, 2023. http://dx.doi.org/10.1201/9781003302872-2.

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Sanchez, Eduardo. "Field programmable gate array (FPGA) circuits." In Towards Evolvable Hardware. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61093-6_1.

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Bazil Raj, A. Arockia. "Digital Signal Processing with Field-Programmable Gate Array." In FPGA-Based Embedded System Developer's Guide. CRC Press, 2018. http://dx.doi.org/10.1201/9781315156200-11.

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Negi, Anvit, Sumit Raj, Surendrabikram Thapa, and S. Indu. "Field Programmable Gate Array (FPGA) Based IoT for Smart City Applications." In Data-Driven Mining, Learning and Analytics for Secured Smart Cities. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-72139-8_7.

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Raja Sudharsan, R., and J. Deny. "Field Programmable Gate Array (FPGA)-Based Fast and Low-Pass Finite Impulse Response (FIR) Filter." In Intelligent Computing and Innovation on Data Science. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-3284-9_23.

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Garzetti, Fabio. "Ultra-High Performance Digital Electronic Architectures for Events Management in Real Time Environments." In Special Topics in Information Technology. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-15374-7_5.

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AbstractThe research spans several application areas, including biotechnology, medical imaging, and environmental monitoring. Precise and specialized processing techniques are often required for measurements of signal parameters with high efficiency, for example, in terms of resolution and count rate, such as time of occurrence of events. Digital solutions have thus received the most significant attention since they are the most effective at enabling flexible, application-oriented elaboration systems. The research is finalized to develop high-resolution time measurement systems in Field Progra
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Kumar, Aditya, Prashant Kumar, Sompurna Modi, and Vijay Nath. "Study and Implementation of Ladder Logic Conversion to VHDL for Field Programmable Gate Array (FPGA)-Based Programmable Logic Controllers (PLC)." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5546-6_3.

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Trimberger, Steve. "SRAM Programmable FPGAs." In Field-Programmable Gate Array Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2742-8_2.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Flexibility of FPGA Routing Architectures." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_6.

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Conference papers on the topic "Filed Programmable Gate Array (FPGA)"

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Chow, P., P. G. Gulak, and P. Chow. "A Field-Programmable Mixed-Analog-Digital Array." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242048.

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Bratt, A., and I. Macbeth. "Design and Implementation of a Field Programmable Analogue Array." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242434.

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Yao-Wen Chang, D. F. Wong, and C. K. Wong. "Universal Switch-Module Design for Symmetric-Array-Based FPGAs." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242433.

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Briggs, Fred. "Field Programmable Gate Array (FPGA) Design Strategies and Applications." In AIAA Infotech@Aerospace 2007 Conference and Exhibit. American Institute of Aeronautics and Astronautics, 2007. http://dx.doi.org/10.2514/6.2007-2958.

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Tan, Beng-Liong, Wai-Kong Lee, Kai-Ming Mok, and Hock-Guan Goh. "Clock Gating Implementation on commercial Field Programmable Gate Array (FPGA)." In 2018 4th International Conference on Electrical, Electronics and System Engineering (ICEESE). IEEE, 2018. http://dx.doi.org/10.1109/iceese.2018.8703530.

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Farhanaaz and V. Sanju. "Field Programmable Gate Array(FPGA): An Innovation In Hardware Technology." In 2023 2nd International Conference for Innovation in Technology (INOCON). IEEE, 2023. http://dx.doi.org/10.1109/inocon57975.2023.10101210.

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Carroll, Robert, Carlos Gutierrez, Leila Choobineh, and Robert Geer. "Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA)." In ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/ipack2019-6514.

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Abstract Field Programmable Gate Arrays (FPGA) are integrated circuits (ICs) which can implement virtually any digital function and can be configured by a designer after manufacturing. This is beneficial when dedicated application-specific runs are not time or cost-effective; however, this flexibility comes at the cost of a substantially higher interconnect overhead. Three-dimensional (3D) integration can offer significant improvements in the FPGA architecture by stacking multiple device layers and interconnecting them in the third or vertical dimension, through a substrate, where path lengths
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WANG, JINGHUI, and YUANCHAO ZHAO. "LOW-COST FIELD PROGRAMMABLE GATE ARRAY ACCELERATES DEEP Q-LEARNING." In 2021 INTERNATIONAL CONFERENCE ON ADVANCED EDUCATION AND INFORMATION MANAGEMENT (AEIM 2021). Destech Publications, Inc., 2021. http://dx.doi.org/10.12783/dtssehs/aeim2021/35981.

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Abstract. Due to recent advances in digital technologies, deep reinforcement learning has emerged, and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolution neural networks (CNNs) have been demonstrated their effectiveness in reinforcement learning. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve desired performance levels. In this paper, we used some low-cost field programming gates array (FPGA) designed a parallel Deep Qlearning accelerator to solve this pr
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Moore, Christopher H., Ulas Sunar, and Wei Lin. "A Real-Time FPGA-Based DCS System for Blood Flow Monitoring." In Optical Tomography and Spectroscopy. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/ots.2024.om5d.5.

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A field-programmable gate array (FPGA) design was created to perform all diffuse correlation spectroscopy (DCS) computations necessary to derive a blood flow index on a single chip. A good match was observed between cuff ischemia results from our FPGA system and a reference standard DCS system.
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Bai, Yu, and Mingjie Lin. "Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only)." In FPGA'16: The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2016. http://dx.doi.org/10.1145/2847263.2847317.

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Reports on the topic "Filed Programmable Gate Array (FPGA)"

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Manohar, Rajit. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA). Defense Technical Information Center, 2015. http://dx.doi.org/10.21236/ada614130.

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Wawrzynek, J., and K. Asanovic. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture. Defense Technical Information Center, 2009. http://dx.doi.org/10.21236/ada519578.

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Wirthlin, Michael, Brent Nelson, Brad Hutchings, Peter Athanas, and Shawn Bohner. Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada492273.

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Don, Michael, and Mitchell Grabner. A Field-Programmable Gate Array (FPGA)-Based Instrumentation System for an Embedded Flight Controller. DEVCOM Army Research Laboratory, 2022. http://dx.doi.org/10.21236/ad1156875.

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Lin, Chun-Shin. High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA). Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada514601.

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Chang, Chen, and Kevin Camera. Exploring Field-Programmable Gate Array (FPGA)-Based Emulation Technologies for Accelerating Computer Architecture Development and Evaluation. Defense Technical Information Center, 2009. http://dx.doi.org/10.21236/ada511786.

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El-Ghazawi, Tarek, Alan D. George, Ivan Gonzalez, et al. Exploration of a Research Roadmap for Application Development and Execution on Field-Programmable Gate Array (FPGA)-Based Systems. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada494473.

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Tayeb, Shahab. Intelligent Blind Crossings for Suburban and Rural Intersections. Mineta Transportation Institute, 2025. https://doi.org/10.31979/mti.2024.2351.

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Blind intersections in suburban and rural areas pose significant safety challenges due to limited visibility and inadequate infrastructure. This project proposes an innovative solution leveraging the Internet of Vehicles (IoV) paradigm, utilizing connected and autonomous vehicles (CAVs) for seamless communication to enhance safety at these intersections. The research focuses on developing a specialized Road-Side Unit (RSU) system equipped with a Virtual Traffic Light Algorithm implemented on a Field-Programmable Gate Array (FPGA). Key stakeholders, including transportation authorities, vehicle
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Mumbru, Jose, George Panotopoulos, and Demetri Psaltis. Optically Programmable Field Programmable Gate Arrays (FPGA) Systems. Defense Technical Information Center, 2004. http://dx.doi.org/10.21236/ada421336.

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