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Journal articles on the topic 'Filed Programmable Gate Array (FPGA)'

Author: Grafiati

Published: 7 June 2025

Last updated: 2 August 2025

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1

krishna, Mr P. V. Murali, and Kantumajji Navyasri. "ACCELERATING HIGH-PERFORMANCE VOLTAGE SOURCE INVERTER PROTOTYPING WITH FPGA IMPLEMENTATION." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (2023): 1–10. http://dx.doi.org/10.55041/ijsrem27818.

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This paper highlights the advantages of FPGA-based rapid prototyping as a powerful tool for accelerating the development cycle of high-performance Voltage Source Inverters. By providing a flexible and efficient platform for algorithm testing, hardware evaluation, and performance optimization, it contributes to advancements in power electronics and facilitates the deployment of robust VSIs in diverse application domains. Through extensive experimentation, we demonstrate the effectiveness of the FPGA-based rapid prototyping platform in achieving high- performance VSI control. The FPGA's real-tim

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Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, and Rahul Khanna. "Field Programmable Gate Array Applications—A Scientometric Review." Computation 7, no. 4 (2019): 63. http://dx.doi.org/10.3390/computation7040063.

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram

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Xu, Heyang. "FPGA: The super chip in the age of artificial intelligence." Journal of Physics: Conference Series 2649, no. 1 (2023): 012018. http://dx.doi.org/10.1088/1742-6596/2649/1/012018.

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Abstract In modern society, artificial intelligence (AI) is developing more rapidly. And the Field Programmable Gate Array (FPGA) has always been the focus of research as a driving platform. This paper studies in detail the theoretical basis, applications, defects, and future development directions of FPGAs. It is concluded that FPGA has three characteristics: gate array, programmable, and scene, and the detailed positioning of FPGA, the structure, principle, tools, process, and description language of FPGA design. And the unique advantages of FPGA in the field of artificial intelligence: flex

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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier inje

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., Karthik S. "REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB." International Journal of Research in Engineering and Technology 03, no. 04 (2014): 842–45. http://dx.doi.org/10.15623/ijret.2014.0304149.

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Chen, Yonghao, Tianrui Li, Xiaojie Chen, ZhiGang Cai, and Tao Su. "High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays." Electronics 12, no. 4 (2023): 822. http://dx.doi.org/10.3390/electronics12040822.

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The systolic array is frequently used in accelerators for neural networks, including Transformer models that have recently achieved remarkable progress in natural language processing (NLP) and machine translation. Due to the constraints of FPGA EDA (Field Programmable Gate Array Electronic Design Automation) tools and the limitations of design methodology, existing systolic array accelerators for FPGA deployment often cannot achieve high frequency. In this work, we propose a well-designed high-frequency systolic array for an FPGA-based Transformer accelerator, which is capable of performing th

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Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

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A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acqu

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Jamro, Ernest, Maciej Wielgosz, Sławomir Bieniasz, and Witold Cioch. "FPGA – ARM Heterogeneous System for High Speed Signal Analysis." Solid State Phenomena 180 (November 2011): 207–13. http://dx.doi.org/10.4028/www.scientific.net/ssp.180.207.

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This paper presents a version 2 of hardware solution denoted as Programmable Unit for Diagnostic (PUD-2) based on Filed Programmable Gate Arrays (FPGAs) and ARM-based OMAP3530 microprocessor adapted for diagnostic systems. The sampling frequency of the input analog signals and digital signals processing speed of the PUD is high beyond comparable DSP based systems. Employing ARM microprocessor allows for much quicker and easer design than only FPGA-based solution.

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Bhuvaneswari, Thangavel, Nor Hidayati Abdul Aziz, Jakir Hossen, and Chinthakunta Venkataseshaiah. "Field Programmable Gate Array (FPGA) Based Microwave Oven." Applied Mechanics and Materials 892 (June 2019): 120–26. http://dx.doi.org/10.4028/www.scientific.net/amm.892.120.

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In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms

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Govil, Anchal, Anmol Karnwal, Govinda Sindhu, Ayush Singh, and Dr Shubham Shukla. "Design and Implementation of UART Using FPGA Board." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (2022): 1187–90. http://dx.doi.org/10.22214/ijraset.2022.41478.

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Abstract: This paper introduces the implementation of the Universal Asynchronous Receiver- Transmitter Controller (UART) based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our UART design is fully functional and built-in. Coded using the Verilog design from top to bottom and visible in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. Use results show that the design can work Spartan-3E FPGA maximum clock frequency of 218.248 MHz. The maximum frequent use of the UART controller is 192.773 MHz. of bits and hence this is why with a small amount of storage. Keywords: Receive

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Keller, Damián, Aman Jagwani, and Victor Lazzarini. "The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design." Computers 14, no. 4 (2025): 155. https://doi.org/10.3390/computers14040155.

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The emergent field of embedded computing presents a challenging scenario for ubiquitous music (ubimus) design. Available tools demand specific technical knowledge—as exemplified in the techniques involved in programming integrated circuits of configurable logic units, known as field-programmable gate arrays (FPGAs). Low-level hardware description languages used for handling FPGAs involve a steep learning curve. Hence, FPGA programming offers a unique challenge to probe the boundaries of ubimus frameworks as enablers of fast and versatile prototyping. State-of-the-art hardware-oriented approach

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Hyodo, Kazuhito, Hirokazu Noborisaka, Keijiro Yamamoto, and Takashi Yada. "Development of a Portable Multipurpose Controller for Mechatronics Education." Journal of Robotics and Mechatronics 19, no. 2 (2007): 223–31. http://dx.doi.org/10.20965/jrm.2007.p0223.

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The control module we developed for mechatronics education, consists of a Field-programmable gate array (FPGA), a Programmable System-On-Chip (PSoC) and Game Boy Advance (GBA). The FPGA and PSoC provide a reconfigurable peripheral module and the GBA provides computational power and an interactive user interface. The interactive user interface is very useful for developing educational materials, and the control module enables educators to develop a variety of educational materials.

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Kou, Zhengchang, and Michael L. Oelze. "Ultrafast ultrasound beamformer for plane wave imaging with field programmable gate array." Journal of the Acoustical Society of America 153, no. 3_supplement (2023): A353. http://dx.doi.org/10.1121/10.0019131.

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In this work, we propose a novel method of implementing an ultrafast ultrasound beamformer for plane wave imaging (PWI) on a field programmable gate array (FPGA). First, a modified delay calculation method was proposed to (1) separate the transmit and receive delay, (2) reduce the size of delay profile, and (3) enable parallel beamforming by delay reuse and data vectorization. Second, a parallelized implementation of beamformer on single FPGA was proposed by (1) loading pre-calculated delay profile from external memory instead of calculating delay on run-time, (2) vectorizing channel data fetc

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Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam, and Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays." International Journal of Handheld Computing Research 7, no. 4 (2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation

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LI, XIAOYING, and ENHUA WU. "RELIEF TEXTURE MAPPING ON FIELD PROGRAMMABLE GATE ARRAY." International Journal of Image and Graphics 06, no. 04 (2006): 641–55. http://dx.doi.org/10.1142/s021946780600246x.

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Relief texture mapping is an image-based rendering technique which can successfully support the representation of 3D surface details and view motion parallax. It has the potential to significantly increase visual realism of rendered geometry while keeping system load constant. In this paper, FPGA (Field Programmable Gate Array) chip technology is applied to this three-dimensional image warping method. A relief texture mapping system has been implemented on a reprogrammable and reconfigurable FPGA board. The algorithm is optimized for the specific architecture and the framework is customized fo

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Kurniawan, Yusuf, and Muhammad Adli Rizqulloh. "Block cipher four implementation on field programmable gate array." Communications in Science and Technology 5, no. 2 (2020): 53–64. http://dx.doi.org/10.21924/cst.5.2.2020.184.

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Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios

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Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging." Advanced Materials Research 588-589 (November 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.

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While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presen

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Binh, Dang, Bui Minh, Trinh Vu Dang Nguyen, and Tran Linh. "Parameterized SDRAM-based content-addressable memory on field programmable gate array." Parameterized SDRAM-based content-addressable memory on field programmable gate array 31, no. 2 (2023): 669–80. https://doi.org/10.11591/ijeecs.v31.i2.pp669-680.

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Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)- based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Bes

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Liu, Liang, Zhao Yao Zhou, Ke Jing He, Wen Jiong Cao, and Xue Feng Qin. "Reconfigurable Design and Implementation of Gravure Engraving Motion Controller Based on FPGA." Advanced Materials Research 317-319 (August 2011): 1518–24. http://dx.doi.org/10.4028/www.scientific.net/amr.317-319.1518.

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Reconfigurable logic has gained relevance in high-speed computer numerical control (CNC) digital controller. In this paper, a design of three-axis high speed gravure engraving machine motion controller based on programmable logical device is proposed. In the design of the hardware, the prevalent technology of Filed Programmable Gate Array is applied, which enhances the flexibility of the hardware. All the circuits and algorithms are developed using hardware description language. A novel solution for acceleration and deceleration control of servo motors is implemented in FPGA. This system is al

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C. P., Mallikarjuna Gowda, and Raju Hajare. "Space-time trellis codes: Field programmable gate array approach." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 3 (2020): 213. http://dx.doi.org/10.11591/ijres.v9.i3.pp213-223.

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This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and

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Guerrieri, Andrea, Andres Upegui, and Laurent Gantel. "Applications Enabled by FPGA-Based Technology." Electronics 12, no. 15 (2023): 3302. http://dx.doi.org/10.3390/electronics12153302.

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Ramezani, Hadise, Majid Mohammadi, and Amir Sabbagh Molahosseini. "An efficient look up table based approximate adder for field programmable gate array." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (2022): 144. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp144-151.

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The approximate computing is an alternative computing approach which can lead to high-performance implementation of audio and image processing as well as deep learning applications. However, most of the available approximate adders have been designed using application specific integrated circuits (ASICs), and they would not result in an efficient implementation on field programmable gate arrays (FPGAs). In this paper, we have designed a new approximate adder customized for efficient implementation on FPGAs, and then it has been used to build the Gaussian filter. The experimental results of the

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Ramezani, Hadise, Majid Mohammadi, and Amir Sabbagh Molahosseini. "An efficient look up table based approximate adder for field programmable gate array." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (2022): 144–51. https://doi.org/10.11591/ijeecs.v25.i1.pp144-151.

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The approximate computing is an alternative computing approach which can lead to high-performance implementation of audio and image processing as well as deep learning applications. However, most of the available approximate adders have been designed using application specific integrated circuits (ASICs), and they would not result in an efficient implementation on field programmable gate arrays (FPGAs). In this paper, we have designed a new approximate adder customized for efficient implementation on FPGAs, and then it has been used to build the Gaussian filter. The experimental results of the

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Maerani, Restu, Tulis Jojok Suryono, Sigit Santoso, and Muhammad Subekti. "Kajian Implementasi Field Programmable Gate Array untuk Rencana Modernisasi Sistem Proteksi Reaktor." Jurnal Pengembangan Energi Nuklir 22, no. 2 (2020): 119. http://dx.doi.org/10.17146/jpen.2020.22.2.6095.

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Penggunaan Field Programmable Gate Array (FPGA) pada reaktor nuklir sudah dilakukan sejak 2016, terutama diaplikasikan pada perangkat Sistem Instrumentasi dan Kendali (SIK). FPGA sebelumnya sudah diujikan pada rancangan Sistem Proteksi Reaktor (SPR) dan Engineered Safety Feature – Component Control System (ESF-CCS) reaktor daya tipe APR1400. Dengan adanya rencana peremajaan SIK reaktor serbaguna G.A. Siwabessy (RSG-GAS) pada bagian SPR, diharapkan sistem berbasis FPGA juga dapat diimplementasikan pada reaktor riset. Dengan pertimbangan nilai ekonomi, keamanan dan juga keandalannya, FPGA yang b

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Tran, Hoang T., Dong LT Tran, Quang N. Pham, et al. "Field programmable gate array based moving object tracking system for robot navigation." Bulletin of Electrical Engineering and Informatics 12, no. 2 (2023): 771–81. http://dx.doi.org/10.11591/eei.v12i2.4538.

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This paper proposes a method in which an object tracking robot system is implemented on field programmable gate arrays (FPGAs). The OV7670 camera provides real-time object pictures to the system. To improve picture quality, images are put via the median filter phase. The item is distinguished from the backdrop based on color (red), after which it is subjected to a mathematical morphological approach of filtering to eliminate noise. To send the robot control signals, the object's (new) coordinates are found. In this method, the median filter, color separation, hardware IP cores, and morphologic

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Hoang, T. Tran, LT. Tran Dong, N. Pham Quang, et al. "Field programmable gate array based moving object tracking system for robot navigation." Bulletin of Electrical Engineering and Informatics 12, no. 2 (2023): 771~781. https://doi.org/10.11591/eei.v12i2.4538.

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This paper proposes a method in which an object tracking robot system is implemented on field programmable gate arrays (FPGAs). The OV7670 camera provides real-time object pictures to the system. To improve picture quality, images are put via the median filter phase. The item is distinguished from the backdrop based on color (red), after which it is subjected to a mathematical morphological approach of filtering to eliminate noise. To send the robot control signals, the object's (new) coordinates are found. In this method, the median filter, color separation, hardware IP cores, and morphol

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Augoestien, Nia Gella, Abdul Ro uf, Bambang Nurcahyo Prastowo, and Jazi Eko Istiyanto. "Review of Obfuscation Techniques in FPGA (Field Programmable Gate Array) Security." International Journal for Research in Applied Science and Engineering Technology 13, no. 1 (2025): 1163–66. https://doi.org/10.22214/ijraset.2025.66519.

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Abstract: Hardware security is crucial for FPGA-based systems in addition to the functional realization of the system according to the expected specifications and optimal performance. FPGA has a longer supply-chain model that involves many entities. This results in greater opportunities for security threats and trust issues. Hardware Obfuscation is one method that can be used as a mechanism for a security effort from the threats of IP Piracy, Overbuilding, Trojan Hardware, Reverse Engineering, and Bitstream Modification. Obfuscation technique variations for FPGA-based system security cannot be

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Liu, Meng, Yunfei Wang, and Shuai Li. "A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration." Electronics 13, no. 1 (2023): 37. http://dx.doi.org/10.3390/electronics13010037.

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Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introd

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Dhekekar, Ram Shankarrao, and N. V. Srikanth. "Digital Control of Static Var Compensator with Field Programmable Gate Array." International Journal of Reconfigurable and Embedded Systems (IJRES) 1, no. 3 (2012): 87. http://dx.doi.org/10.11591/ijres.v1.i3.pp87-94.

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This paper is about real time simulation and implementation of FPGA Digital Control of Static VAR compensator for 750km lab model of artificial transmission line. In this paper, a new method of controlling SVC using Field Programmable Gate Array (FPGA) is suggested. FPGA controller is used to generate the firing pulses required to for Static Var Compensator. Pulses are synchronized with AC input; the delay of pulses determines the firing angle to driver circuit. The proposed control scheme has been realized using XILINX FPGA SPARTAN 2 XC2S200 and tested actual testing proves that these devices

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Балбаев, Г. К. "ТЕХНОЛОГИЯ FPGA (FIELD PROGRAMMABLE GATE ARRAY) ДЛЯ КОСМИЧЕСКОЙ СВЯЗИ". Вестник Академии гражданской авиации, № 1 (2022): 34–38. http://dx.doi.org/10.53364/24138614_2022_24_1_34.

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Lingyan Sun, Hongwei Song, Z. Keirn, and B. V. K. V. Kumar. "Field programmable gate array (FPGA) for iterative code evaluation." IEEE Transactions on Magnetics 42, no. 2 (2006): 226–31. http://dx.doi.org/10.1109/tmag.2005.861744.

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Dang, Binh, Minh Bui, Nguyen Trinh Vu Dang, and Linh Tran. "Parameterized SDRAM-based content-addressable memory on field programmable gate array." Indonesian Journal of Electrical Engineering and Computer Science 31, no. 2 (2023): 669. http://dx.doi.org/10.11591/ijeecs.v31.i2.pp669-680.

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Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)-based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Besi

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Cao, Da, Shun Xiang Wu, and Long Jiang Su. "I²C-Bus Design Based on FPGA." Advanced Materials Research 179-180 (January 2011): 528–33. http://dx.doi.org/10.4028/www.scientific.net/amr.179-180.528.

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Introduced field programmable gate array FPGA with I2C bus interface device interface design. Programming with VHDL, using general FPGA I/O port to generate I2C bus interface signal timing, achieved FPGA with I2C-bus devices data communication, went through the simulation test, given the application example of FPGA with I2C-bus EEPROOM chip AT24C02 connected hardware design.

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Muzakkir, Mas’ud Adamu*, Ahmend Danzomo*** Bashir, Agadi Danladi** Tonga, Ahmed** Abubakar, and Hassan* Zakariyya. "FIELD PROGRAMMABLE GATE ARRAY BASED PULSE WIDTH MODULATION CONTROLLER." International Journal of Engineering Sciences & Research Technology 5, no. 2 (2016): 789–98. https://doi.org/10.5281/zenodo.46521.

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A pulse width modulation (PWM) signal controller is implemented in a digital circuit to control the speed of a DC motor. The PWM controller modules are designed by adopting the very high-speed integrated circuit hardware description language (VHDL) and the Xilinx Spartan-3E starter board, field programmable gate array (FPGA). The use of PWM control for DC motors is widely used due to reliable performance. The starting torque, for example, in a DC motor can be higher several orders in magnitude than that for a comparable size AC motor. PWM control for DC motors enables a higher efficient, wide

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Tounsi, Mohamed, Ali Jafer Mahdi, Mahmood Anees Ahmed, et al. "Hardware Implementation of a Deep Learning-based Autonomous System for Smart Homes using Field Programmable Gate Array Technology." Engineering, Technology & Applied Science Research 14, no. 5 (2024): 17203–8. http://dx.doi.org/10.48084/etasr.8372.

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The current study uses Field-Programmable Gate Array (FPGA) hardware to advance smart home technology through a self-learning system. The proposed intelligent three-hidden layer system outperformed prior systems with 99.21% accuracy using real-world data from the MavPad dataset. The research shows that FPGA solutions can do difficult computations in seconds. The study also examines the difficulties of maximizing performance with limited resources when incorporating deep learning technologies into FPGAs. Despite these challenges, the research shows that FPGA-based solutions improve home technol

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Muhammed, Ihsan Husni, Kareem Hussein Mohammed, Shamian Bin Zainal Mohd, Anuar Bin Hamzah Shipun, Bin Md Nor Danial, and Bin Mhd Poad Hazwaj. "Soil Moisture Monitoring Using Field Programmable Gate Array." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 169–74. https://doi.org/10.11591/ijeecs.v11.i1.pp169-174.

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This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity. Hardware descriptive language has been used for the implementation of proposed topology on Field Programmable Gate Arrays. The hardware used for this purpose is an Altera board. The simulated results take into consideration the environmental factors such as the humidity, soil moisture content and the temperature. The proposed system continuously monitors the environmental changes for any updates. The system also controls a water motor that is turn

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VELAYAUDHAN, SINDHU THAZHATHETHIL, and KALPANA DEVI. "BUFIT: FINE-GRAINED DYNAMIC BURST FAULT INJECTION TOOL FOR EMBEDDED field programmable gate array TESTING." REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE 69, no. 3 (2024): 303–8. http://dx.doi.org/10.59277/rrst-ee.2024.69.3.8.

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Fault injection (FI) is a well-known method to attack embedded systems, particularly advanced FPGAs and microcontrollers physically. The FPGA-based embedded system constitutes SRAM for configuration data storage. Multiple-bit upset is a main threat for FPGAs due to technology scaling and complex application bit files. Space environments additionally incur radiation threats to these devices. This paper proposes burst error modeling and a burst fault injection tool (BUFIT) to address these issues. BUFIT has been proposed with fine-grained and coarse-grained circuits. Built-in instrumented FPGA-b

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Qi, Xing Guang, Yan Min Zhang, Qing Hua Li, and Ning Wang. "Photon Correlator Implemented by Field Programmable Gate Array." Applied Mechanics and Materials 513-517 (February 2014): 4171–74. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4171.

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Photon correlation technique is an effective method for measuring the particle size of sub-micron particles and nanoparticles. This technology has a good prospect and commercial value. Photon correlator is used in photon correlation spectroscopy experiment to gain the photon correlation function. In order to obtain the accurate values of the photon correlation, efficient and accurate photon correlator must be designed. This paper presents one kind of photon correlator implemented by FPGA. The programming language used is Verilog HDL. The software design and system simulation are completed in t

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Joler, Miroslav. "How FPGAs Can Help Create Self-Recoverable Antenna Arrays." International Journal of Antennas and Propagation 2012 (2012): 1–10. http://dx.doi.org/10.1155/2012/196925.

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An approach to utilize Field Programmable Gate Array (FPGA) technology to control antenna arrays is presented based on the scenario of sensing a failure of any array element, analyzing degradation of the radiation pattern due to that failure, and finding a new set of excitations to the array elements in order to recover the radiation pattern as close to the original state as possible, thus creating aself-recoverable antenna array(SRA). The challenges of the SRA concept and embodiment of the recovery algorithm(s) are discussed. The results of the radiation recovery are presented on a few array

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Palepu, Mohan Radha Devi, Kumar Chenchela Vijay, Vijayasanthi Palepu, and Kapileswar Nellore. "DESIGN OF HIGH SPEED FIR FILTER ON FPGA BY USING MULTIPLEXER ARRAY OPTIMIZATION IN DA-OBC ALGORITHM." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 4 (2016): 715–22. https://doi.org/10.5281/zenodo.50382.

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The main objective of the project is to implement FIR filter on FPGA using Distributed Arithmetic-Offset Binary Coding (DA-OBC) reduction technique. Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application- specific integrated circuits (ASICs) for higher rates.  This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs). Implementing hardware design in Field Programmable Gate Arra

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LEE, HANHO, and GERALD E. SOBELMAN. "VLSI DESIGN OF DIGIT-SERIAL FPGA ARCHITECTURE." Journal of Circuits, Systems and Computers 13, no. 01 (2004): 17–52. http://dx.doi.org/10.1142/s021812660400126x.

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This paper presents a novel application-specific field-programmable gate array (FPGA) architecture that satisfies efficient implementation of digit-serial DSP architectures on a digit wide basis. Digit-serial DSP designs have been an effective implementation method for FPGAs. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layo

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Li, Xu, Xing Guang Qi, Qing Hua Li, Ning Wang, and Li Peng Wang. "Photon Counter Implemented by Field Programmable Gate Array." Advanced Materials Research 591-593 (November 2012): 1396–99. http://dx.doi.org/10.4028/www.scientific.net/amr.591-593.1396.

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Photon correlation technique is an effective method for measuring the particle size of sub-micron particles and nanoparticles. This tenchnology has a good prospect and commerical value. Photon counter is used in photon correlation spectroscopy experiment to gain the intensity of photon. In order to obtain the accurate values of the photon correlation, efficient and accurate photon counter must be designed. This paper presents two kinds of photon counters implemented by FPGA. The programming language used is Verilog HDL. The software design and system simulation are completed in the integration

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Yang, Liu, Yuqi Wang, Zhiru Wu, and Xiaoyuan Wang. "FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design." Micromachines 12, no. 11 (2021): 1344. http://dx.doi.org/10.3390/mi12111344.

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In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has distinct advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

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Hajduk, Zbigniew. "Field-Programmable Gate Array-Based True Random Number Generator Using Capacitive Oscillators." Electronics 13, no. 23 (2024): 4819. https://doi.org/10.3390/electronics13234819.

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In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A specific connection between these buffers allows cyclical charging and discharging of a parasitic capacitance associated with an external FPGA pin. If a few pins of an FPGA chip are not connected to any external components, they can be targeted to build the TRNG. The proposed TRNG requires only three external

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Šušteršič, Tijana, and Aleksandar Peulić. "Implementation of Face Recognition Algorithm on Field Programmable Gate Array (FPGA)." Journal of Circuits, Systems and Computers 28, no. 08 (2019): 1950129. http://dx.doi.org/10.1142/s0218126619501299.

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The aim of this study is to implement an algorithm for face recognition, based on fast fourier transform (FFT), on the field programmable gate array (FPGA) chip. Implemented program included the initialization process of two single-IP-core ROM blocks, each with an image of a human face, which are sent to the real components of two-channel IP CoreFFT block. The result of classification could be displayed in the form of either a word “yes” or “no” on the seven-segment display or the information about the reference to the folder with the found match face. Due to the lack of memory on the chip, th

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Sum, Rithea, Watcharapan Suwansantisuk, and Pinit Kumhom. "Remote field-programmable gate array laboratory for signal acquisition and design verification." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 2 (2024): 2344. http://dx.doi.org/10.11591/ijece.v14i2.pp2344-2360.

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A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embedded-system design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabi

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Sum, Rithea, Watcharapan Suwansantisuk, and Pinit Kumhom. "Remote field-programmable gate array laboratory for signal acquisition and design verification." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 2 (2024): 2344–60. https://doi.org/10.11591/ijece.v14i2.pp2344-2360.

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A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embeddedsystem design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging c

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Duong, Huu Ai, Dat Vuong Cong, Ty Luong Khanh, and Truong Le Viet. "Field programmable gate array implementation of edge detection system based on an improved sobel edge detector." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 3 (2023): 1378–83. https://doi.org/10.11591/ijeecs.v32.i3.pp1378-1383.

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Field programmable gate array (FPGA) is an integrated circuit consisting of internal hardware blocks with programmable link connections for users to customize operations for a particular application. Link connections can be easily reprogrammed, allowing the FPGA to adapt to changes to the design or even support a new application throughout the department's uptime. One of the important tasks in image processing is image edge detection image, with computer aided, image recognition is concerned with the recognition and classification of objects in an image, so edge detection is an important tool.

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Mroczkowski, Piotr. "Implementation of the block cipher Rijndael using Altera FPGA." Journal of Telecommunications and Information Technology, no. 1 (March 30, 2001): 80–86. http://dx.doi.org/10.26636/jtit.2001.1.35.

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A short description of the block cipher Rijndael is presented. Hardware implementation by means of the FPGA (field programmable gate array) technology is evaluated. Im- plementation results compared with other hardware imple- mentations are summarized.

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Wang, Nuocheng. "HDL Synthesis, Inference and Technology Mapping Algorithms for FPGA Configuration." International Journal of Engineering and Technology 16, no. 1 (2024): 32–38. http://dx.doi.org/10.7763/ijet.2024.v16.1251.

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This paper introduces the logic control flow of Field-Programmable Gate Array (FPGA). The process from analyzing a digital circuit description to component mapping on FPGA is described thoroughly. This transforming process is partitioned into three major stages: combinational logic synthesis, sequential logic inference, and technology mapping. Specific algorithms are discussed for each stage.

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