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Journal articles on the topic 'Fine pitch technology'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

SAKAMOTO, Yasuhiro, Masato SUMIKAWA, Hiroshi MATSUBARA, Keiji YAMAMURA, and Takashi NUKII. "Fine Pitch TAB/OLB Technology." Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 13, no. 1 (1998): 30–36. http://dx.doi.org/10.5104/jiep1995.13.30.

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2

NOGAMI, Sachiko, Fumihiko ANDO, Fumihiko TANIGUCHI, Akira TAKASHIMA, Kanako MURAKAMI, and Nobutaka ITO. "Surface Mount Technology Fine Pitch BGA." Journal of Japan Institute of Electronics Packaging 4, no. 1 (2001): 63–67. http://dx.doi.org/10.5104/jiep.4.63.

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3

SUGATA, Takashi, Yosikazu KUMAGAYA, Tadashi UNO, et al. "Technology of Ultra-Thin Fine Pitch LGA." Journal of Japan Institute of Electronics Packaging 5, no. 3 (2002): 278–82. http://dx.doi.org/10.5104/jiep.5.278.

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4

XUE, Songbai. "Diode Laser Soldering Technology of Fine Pitch QFP Devices." Chinese Journal of Mechanical Engineering 24, no. 05 (2011): 917. http://dx.doi.org/10.3901/cjme.2011.05.917.

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5

Son, Jihye, Yong-Sung Eom, Kwang-Seong Choi, Haksun Lee, Hyun-Cheol Bae, and Jin-Ho Lee. "HV-SoP Technology for Maskless Fine-Pitch Bumping Process." ETRI Journal 37, no. 3 (2015): 523–32. http://dx.doi.org/10.4218/etrij.15.0114.0578.

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6

Khan, Sadia A., Abhishek Choudhury, Nitesh Kumbhat, et al. "Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections." IEEE Transactions on Components, Packaging and Manufacturing Technology 3, no. 2 (2013): 197–204. http://dx.doi.org/10.1109/tcpmt.2012.2235528.

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7

Wright, Steven L., and Yang Liu. "Transferable-Tip Technology for Fine-Pitch Probes and Interconnections." IEEE Transactions on Components, Packaging and Manufacturing Technology 9, no. 8 (2019): 1451–58. http://dx.doi.org/10.1109/tcpmt.2019.2925589.

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8

Qin, Ivy, Hui Xu, Cuong Huynh, et al. "Fine Pitch Cu Wire Bonding Capability – Process Optimization and Reliability Study." International Symposium on Microelectronics 2014, no. 1 (2014): 000283–88. http://dx.doi.org/10.4071/isom-tp43.

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Wire bonding has been around for over 70 years and it is still growing. The most recent advances in wire bonding are the wide proliferation of fine pitch Cu wire bonded applications and the development of fine pitch Cu capability extending to the newest technology nodes. Around 2008, fine pitch Cu wire bonding started to take off driven by the skyrocketing Au price. Since then, Cu wire bonding capability has improved dramatically so that today's advanced technology devices such as 28nm and 20nm nodes are being bonded with Cu wire including Pd coated and AuPd coated Cu wire. It turns out that not only is Cu wire cheaper, but it is more suitable for high I/O counts, and fine pitch advanced node applications due to its better electrical and mechanical properties. This paper examines the most advanced Cu wire bonding capability using a Cu optimized process called ProCuTM process. 40um pitch and 35um pitch capability are demonstrated using this new ProCu process. Process responses such as process bonding windows, intermetallic coverage (IMC), and free air ball size control are studied in detail. The ProCu process achieved fine pitch capability for 40um as a robust production process and it also shows that 35um pitch with 13um (0.5mil) wire is a possibility using the latest technology. The JEDEC Reliability test has been a challenge for Cu wire bonding especially for fine pitch applications. As part of this paper, we also examined reliability aspects of fine pitch Cu wire bonding. TEM analysis was used to understand the major factors that affect Cu wire bonding reliability.

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9

Aoki, Toyohiro, Kazushige Toriyama, Hiroyuki Mori, et al. "IMS (Injection Molded Solder) Technology with Liquid Photoresist for Ultra Fine Pitch Bumping." International Symposium on Microelectronics 2014, no. 1 (2014): 000713–17. http://dx.doi.org/10.4071/isom-wp42.

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IMS (injection molded solder) is an advanced solder bumping technology with solder alloy flexibility even at very fine pitch and small size. One of key materials for successful fine pitch bumping by IMS is a photoresist material. The photoresist material must be stable at high temperature during the IMS process and be perfectly stripped after the IMS process without any residue on the surface of the substrate. In this study, negative tone liquid photoresist materials were prepared to investigate effects of thermal cure of photoresist on IMS process and stripping performance. With appropriate cure conditions, successful bumping without any film damages at IMS process and any residue at stripping was achieved. Fine pitch bumping down to 40 μm pitch with 20 μm diameter was demonstrated with a Sn-3.0Ag-0.5Cu solder. Also physical and electrical connections for the solder joints of IMS bumps to Ni/Au pads were confirmed using a 80 μm pitch test vehicle.

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10

Xie, Hua Kun, Ying Fu, and Gang Feng. "Differential Roll-Scanning Technology for Accuracy Measurement of Fine-Pitch Gears." Advanced Materials Research 472-475 (February 2012): 3083–88. http://dx.doi.org/10.4028/www.scientific.net/amr.472-475.3083.

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The accuracy measurement of fine-pitch gears within module 0.02-0.2mm in batch production is one of the puzzle problems in industry because of its small amout of dimension and rigidity. Based on the gear integrated error measurement technology developed by CTRI in China and Frenco in Germany, a kind of differential roll-scanning measuring technology and a differential fine-pitch gear integrated error measuring machine first developed by the authors are introduced briefly in the paper, including the working principle and calculation formulas of ‘two synchronized rotate-driving systems, one differential-compensation closed-loop measurement’ , the stucture of ‘spindle on spindle’ and ‘differential composite driving spindle system’ of the master gear, and the unique master gear with ‘every other tooth thinned’ followed the principle of overlap coefficient not bigger than 1 for a few certain gear pairs，and also the special made hob for making the thinned master gear. The measuring results of four items of deviations, including pitch, profile, tangential composite and integrated deviations of product fine-pitch gears show the feasibility and prospect of the new developed measuring technology and machine in future industry application.

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11

Tacken, Roland, Daniel Mitcan, and Jasper Nab. "Combining Fine Line Photoimageable with Multi-Step Thick Film for Improved Circuit Density." Journal of Microelectronics and Electronic Packaging 14, no. 3 (2017): 94–99. http://dx.doi.org/10.4071/imaps.459344.

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Abstract There is a strong market need for further miniaturization of microelectronic ceramic-based products; electronic components require an increasingly finer pitch interconnect. Screen-printing resolution is a limiting factor in further miniaturization of classical thick film. Photo imageable thick film technology (PITF) was proposed decades ago as a successor technology to thick film, to achieve finer pitch patterns. However, where classical multilayer thick film provides good routing and interconnect capabilities, but insufficient fine line resolution, PITF does the reverse: no multilayer routing but advanced fine line performance. A combination of PITF for fine pitch mounting with advanced MLTF for efficient routing has been developed, targeting a linewidth of 50 μm line/spaces and below. Test and demo panels were made, using combinations of PITF pastes and conventional screen-print materials. Results, process performance, and limiting factors are discussed.

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12

Eom, Yong-Sung. "Optimization of Material and Process for Fine Pitch LVSoP Technology." ETRI Journal 35, no. 4 (2013): 625–31. http://dx.doi.org/10.4218/etrij.13.1912.0007.

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13

Lau, J., L. M. Powers-Maloney, J. R. Baker, D. Rice, and B. Shaw. "Solder joint reliability of fine pitch surface mount technology assemblies." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 13, no. 3 (1990): 534–44. http://dx.doi.org/10.1109/33.58856.

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14

Griffiths, G. W. "Fine pitch surface mount technology —quality, design and manufacturing techniques." Microelectronics Journal 24, no. 5 (1993): 585. http://dx.doi.org/10.1016/0026-2692(93)90128-2.

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15

Katkar, Rajesh, Rey Co, and Wael Zohni. "Manufacturing Readiness of BVA™ Technology for Fine-Pitch Package-on-Package." International Symposium on Microelectronics 2014, no. 1 (2014): 000024–30. http://dx.doi.org/10.4071/isom-ta15.

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Ever increasing performance demands in a rapidly evolving smart phone market have led to a need for higher density interconnections linking memory components with logic devices in a standard package on package (PoP) configuration. While existing solutions present a technological roadblock at 350–400μm PoP pitch, new Bond Via Array (BVA™) technology provides a cost effective and scalable alternative that can achieve 240μm and below pitch values while utilizing conventional wirebond package assembly processes and tools. BVA is a high density, ultra-fine pitch package-on-package (PoP) interconnect solution that enables more than 1000 high aspect ratio connections between memory and processor components in a standard outline PoP. This increase significantly improves PoP capability and correspondingly provides increased bandwidth for the next generation of mobile devices. Here we discuss the 1020 IO BVA demonstration test vehicle, associated manufacturing process details, reliability performance and bi-level socket hardware developed to test these wire bond based novel interconnects. Furthermore the overall high volume manufacturing (HVM) readiness state of this technology for PoP applications will be described. The 1020 IO BVA prototype features 5 rows of vertical interconnects at 0.24mm pitch within an industry standard 14 x14mm package footprint. Although BVA interconnects were primarily developed for PoP packages, they offer many benefits over traditional vertical interconnects and can be implemented in a variety of other applications.

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16

Takahashi, Shintaro, Christian Schmidt, Leander Dittmann, et al. "TGV Microfabrication Technology for 3D Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 000811–31. http://dx.doi.org/10.4071/2012dpc-tp13.

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Glass is expected to be applied to a core material for panel size interposer for 3D package system nowadays. The most important challenge for glass as an interposer is the development of through hole formation with cost-effective and high-throughput. Several through hole drilling technologies such as wet etching, deep reactive-ion etching, sandblasting, laser ablation and the use of photosensitive glass have been studied and reported so far. However, the glass microfabrication technology combining both high-throughput and large area processability have not been reported yet. This study explored the new glass fabrication method by means of electrical discharge to realize high throughput and fine pitch hole drilling. An alkali-free glass substrate was used. Focused and controlled electrical discharge induced dielectric breakdown of glass material and also created Joule heat induced ablation and ejection of glass. Approximately 50 – 60 micron in diameter through hole was made. The result shows, even serial process can have a potential for high high-throughput solution, because this phenomenon can complete as an ultrashort process time of 1msec or less. In terms of fine pitch processability, 100um pitch hole drilling was confirmed. In this study, several glass fabrication technologies were compared by SEM and optical microscope observation for hole shape characteristic. Additionally a potential of industrialization and fine pitch hole drilling were considered. This study pointed out necessary development subjects towards an application, glass core material for 3D interposer substrate.

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17

Nah, Jae-Woong, Peter A. Gruber, Paul A. Lauro, and Claudius Feger. "Mask and mask-less injection molded solder (IMS) technology for fine pitch substrate bumping." International Symposium on Microelectronics 2010, no. 1 (2010): 000348–54. http://dx.doi.org/10.4071/isom-2010-tp5-paper5.

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We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for fine pitch organic substrates. Pure molten solder is injected through a reusable film mask (mask IMS) or directly injected without a mask (mask-less IMS) on the pads of an organic substrate to overcome the limitation of current pre-solder bumping technologies such as solder paste stencil printing and micro-ball mounting. In the case of mask IMS, targeted solder height over the solder resist (SR) is designed into the mask which has desirable thickness and hole sizes. Three different solder bump heights such as 30, 50, and 70 microns over SR were demonstrated for commercial organic substrates which have a pitch of 150 μm for 5,000 area array pads. To show the extendibility of the mask IMS bumping method to very fine pitch applications, 100 μm pitch bumping of 10,000 pads and 80 μm pitch bumping of 15,000 pads were demonstrated. In mask-less IMS, the pure molten solder is directly filled into the opening volume of the SR. After the injection of molten solder, solidification of the solder under low oxygen leads to solder protrusions above the SR surface because 100 % pure solder is filled into the whole SR opening volume. For a 150 μm pitch commercial substrate, we demonstrated minimum bump heights of 15 μm over the 20 μm thick SR. Since there is no need to align mask and substrate, the maskless IMS method lowers process costs and makes the process more reliable. By manipulating the opening in the SR, it is possible to enable variations in the height of the solder bumps. Flux or formic acid is not needed during solder injection of both described processes, but a low oxygen environment must be maintained. In this paper, we will discuss laboratory scale processes and bump inspection data, along with the discussion of manufacturing strategies for IMS solder bumping technology for fine pitch organic substrates.

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18

Whitmore, Mark, and Clive Ashmore. "Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly." International Symposium on Microelectronics 2011, no. 1 (2011): 000502–8. http://dx.doi.org/10.4071/isom-2011-wa2-paper2.

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As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.

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19

Zohni, Wael, Rajesh Katkar, Rey Co, and Rizza Cizek. "Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (2014): 000930–59. http://dx.doi.org/10.4071/2014dpc-tp26.

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Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (&gt;100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

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20

Ruifen, Zhang, Sarangapani Murali, Vinobaji Sureshkumar, Teo Lingling, Loke Chee Keong, and Chan Li-San. "Fine Pitch Paste for System-in-Package Applications." International Symposium on Microelectronics 2018, no. 1 (2018): 000528–33. http://dx.doi.org/10.4071/2380-4505-2018.1.000528.

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Abstract Water soluble solder paste developed using T7 powder particles revealed good solderability when printed on copper, tin, gold flash nickel plated surfaces and on reflow as well. Its cross-section showed absence of voids, good wetting and soldering to the plated surfaces with angle of contact from 42° to 84° on reflow. All the solder interface are integral with pad/substrate surfaces and revealed formation of tin based intermetallics. T7 solder powder processed using Welco technology showed spherical, clean, smooth, un-agglomerated powder particles with the size range of 2 to 12μm. The developed solder paste is used for fine pitch applications.

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21

MITSUKURA, Kazuyuki, Tomonori MINEGISHI, Keiichi HATAKEYAMA, et al. "Assembly Technology for Fine Pitch Bumps Using Photodefinable Wafer-Level Underfill." Journal of Smart Processing 6, no. 4 (2017): 149–55. http://dx.doi.org/10.7791/jspmee.6.149.

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22

Chroneos, R. J., D. Mallik, and S. D. Prough. "Packaging alternatives for high lead count, fine pitch, surface mount technology." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 16, no. 4 (1993): 396–401. http://dx.doi.org/10.1109/33.237936.

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23

Mashiko, Yasuaki. "Technology aspects of TAB tape with fine pitch and high pin count." Journal of the Japan Welding Society 65, no. 4 (1996): 339–42. http://dx.doi.org/10.2207/qjjws1943.65.4_339.

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24

Sano, Yasushi. "Fine-Pitch Printing Technology by Minimum Pressure Printing Process and The Screens." Journal of SHM 9, no. 5 (1993): 15–21. http://dx.doi.org/10.5104/jiep1993.9.5_15.

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25

SHOHJI, Ikuo, Takeshi YAMADA, Hideo KIMURA, Shinichi FUJIUCHI, and Yasumitsu ORII. "Flip Chip Attach Technology for Fine Pitch Connection by In Alloy Solder." Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 12, no. 1 (1997): 25–28. http://dx.doi.org/10.5104/jiep1995.12.25.

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26

Govaerts, J., E. Bosman, W. Christiaens, and J. Vanfleteren. "Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology." IEEE Transactions on Advanced Packaging 33, no. 1 (2010): 72–78. http://dx.doi.org/10.1109/tadvp.2009.2018134.

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27

Booth, Richard. "Materials jetting technology — MPM breakthrough in solder deposition for ultra-fine pitch." Microelectronics Journal 28, no. 5 (1997): xiv—xviii. http://dx.doi.org/10.1016/s0026-2692(97)90117-8.

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28

GOWARD, JOHN M., DAVID J. WILLIAMS, and DAVID C. WHALLEY. "Properties of anisotropic conductive adhesive pastes for fine-pitch surface mount technology." Journal of Electronics Manufacturing 03, no. 04 (1993): 179–90. http://dx.doi.org/10.1142/s096031319300019x.

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29

Takahashi, Shintaro, Kentaro Tatsukoshi, Motoshi Ono, Masaki Mikayama, and Nobuhiko Imajo. "Development of TGV Interposer for 3D IC." International Symposium on Microelectronics 2013, no. 1 (2013): 000631–34. http://dx.doi.org/10.4071/isom-2013-wp14.

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This study explores Through Glass Via (TGV) formation technology and metallization technology for glass interposer. 3D packaging has presently attracted lots of attention. The interposer is recognized as one of key materials, and its development of new fine pitch, high dense, and low cost interposer are accelerated. Glass is expected as one of candidates as material of future interposer substrate because of its good electrical properties and scalability of substrate size leading to higher loading efficiency. This study demonstrates TGV formation showed capabilities of fine pitch and high dense, and TGV formation for standard thick glass aiming varied applications for packaging such as MEMS, Optical device, and RF devise. This study also demonstrates metallization for above fine pitch TGV substrate. Necessary future development and subjects are pointed out.

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30

OGAWA, Hideki. "Micro-Interconnection Technology. The Development of Surface Mount Technology for Fine Pitch Tape Carrier Package." Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 10, no. 6 (1995): 382–84. http://dx.doi.org/10.5104/jiep1995.10.382.

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31

Burgess, Guy, Anthony Curtis, Tom Nilsson, Gene Stout, and Theodore G. Tessier. "Cu Pillar Bumping Technology with Solder Alloy Versatility." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 002360–76. http://dx.doi.org/10.4071/2011dpc-tha31.

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There is considerable interest in the semiconductor industry regarding Cu pillar bumping for finer pitch flip chip and 3D packaging applications. A common Cu Pillar method of production incorporates a combined Cu plated post topped with a plated solder pillar cap, usually of a Sn or SnAg alloy. Compared with this, a unique method of Cu pillar bump production developed at FlipChip International, LLC (FCI) creates the solder cap by applying and reflowing a solder paste on top of the plated Cu post. This method of production offers several benefits; the most important include a broader solder alloy selection, better alloy control, and improved overall pillar height uniformity. FCI has qualified a wide range of Cu pillar bump sizes, heights and shapes including Cu pillar bumps for fine pitch applications as low as 35um pitch (NANOPillarTM). FCI's Cu pillar bump structures in overmolded SiP have passed JEDEC 22-A104C board level thermal cycle testing, JEDEC J-STD-20A MLS 3@260C, as well as other board level corrosion and shock testing. FCI has demonstrated capping Cu pillar bumps with a broad range of solder alloys tailored to specific application requirements.

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32

Rodriguez, G., and D. F. Baldwin. "Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes." Journal of Electronic Packaging 121, no. 3 (1999): 169–78. http://dx.doi.org/10.1115/1.2792680.

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Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the main process variables affecting final print quality. An in-situ measurement system using a high speed imaging system monitored the solder paste release process. Based on experimental observations, different modes of solder paste release and their corresponding mechanisms were identified. A model was developed to predict print quality for fine pitch applications. The proposed model was experimentally verified showing good agreement with measured values for fine pitch and very fine pitch printing. It was found that the cohesive and adhesive forces acting on the paste tend to govern the release process rather than the viscous and inertial forces.

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33

Katkar, Rajesh, Zhijun Zhao, Ron Zhang, Rey Co, and Laura Mirkarimi. "Ultra-fine pitch Package on Package solution for high bandwidth mobile applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 001870–93. http://dx.doi.org/10.4071/2013dpc-tha14.

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Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

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34

Choubey, Anupam, E. Anzures, A. Dhoble, et al. "Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 001432–51. http://dx.doi.org/10.4071/2012dpc-wa14.

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Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

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35

Yoo, Se-Hoon, and Chang-Woo Lee. "Through Silicon Via Filling and Fine Pitch Joining Technology for 3D Electronic Package." Journal of the Korean Welding and Joining Society 27, no. 3 (2009): 17–22. http://dx.doi.org/10.5781/kwjs.2009.27.3.017.

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36

Manessis, Dionysios, Rainer Patzelt, Andreas Ostmann, Rolf Aschenbrenner, and Herbert Reichl. "Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping." Microelectronics Reliability 44, no. 5 (2004): 797–803. http://dx.doi.org/10.1016/s0026-2714(03)00361-5.

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37

Artaki, I., A. M. Jackson, and P. T. Vianco. "Fine Pitch Surface Mount Technology Assembly with Lead‐free, Low Residue Solder Paste." Soldering & Surface Mount Technology 7, no. 2 (1995): 27–32. http://dx.doi.org/10.1108/eb037896.

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38

Takeda, S., H. Ezawa, A. Kuromaru, K. Kawade, Y. Takagi, and Y. Suzuki. "Fine pitch TAB technology with straight side wall bump structure for LCD panel." IEEE Transactions on Consumer Electronics 35, no. 3 (1989): 343–51. http://dx.doi.org/10.1109/30.44290.

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39

Abdrakhmanov, Y. S., P. O. Bykov, and A. V. Bogomolov. "Thermal Capacity of Enriched Fuel Briquets Produced from the Fine of Ekibastuz Coal." Solid State Phenomena 284 (October 2018): 731–36. http://dx.doi.org/10.4028/www.scientific.net/ssp.284.731.

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The object of the research work was coal fines and processes of enrichment of Ekibastuz coal to produce fuel briquettes with increased calorific value and less ash content. Research, scientific substantiation of technology for obtaining high-calorific coal briquettes from fines of Ekibastuz coal, using various binders and the possibility of further coking, designing and manufacturing equipment for the implementation of technology, was made. The standard methods of theoretical and experimental research widely used in metallurgy, machine building, computer systems, etc. were used in the work. The characteristics of briquettes on bio-binding and on petroleum pitch with enrichers in the form of rubber-technical soot and anode dust of electrolysis cell for aluminum production have been established. It is revealed that the calorific value of briquettes is higher than that of Ekibastuz coal (Pavlodar region) by 20-40%, and the heating value is the highest for briquettes with an enrichment agent in the form of anode dust and a binder in the form of petroleum pitch (-NH combustion = 6840.8 kcal / kg). Briquettes on petroleum pitch with an enrichment agent in the form of anodic dust of aluminum electrolysis can be used as industrial briquettes for further use in metallurgy.

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40

Yoo, Do-Jae, Ki-Chan Kim, Young-Hoon Kwak, et al. "Molded Underfill (MUF) Technology Development for SiP Module with Fine Flip Chip." International Symposium on Microelectronics 2010, no. 1 (2010): 000204–11. http://dx.doi.org/10.4071/isom-2010-tp2-paper2.

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In this study, we developed the Molded Underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on the void free methodology to minimize void between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding Compound (EMC) selection approach, air vent design of cavity vacuum molding, and void formation mechanism by mold flow simulation and DOE(Design of Experiment) of several SIP module layouts. The test vehicle used for this study of MUF by vacuum transfer molding shown as SiP module (8.2×7.7×1.13mm) which was sawn from 52.70×68.70×0.75mm mold area of 118.5*75.5*0.38 substrate. One segment mold inside (52.70× 68.70×0.75mm) had 35ea SiP modules (7X5 unit array). In addition, one SiP module included one Flip chip RF/BB IC(6.51×5.81×0.41mm) which had 339ea bumps and 95um Bump height, one Flip chip RF switch (0.705×0.705× 0.33mm) which had 4 bumps and 85um bump height, 1.6×0.8×0.6mm size of LC filter, and total 25ea passives. In the end, SAT result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.

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41

Mohammed, Ilyas. "Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)." International Symposium on Microelectronics 2012, no. 1 (2012): 001137–42. http://dx.doi.org/10.4071/isom-2012-thp43.

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For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVA™) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The three main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.

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MISHINA, Haruo. "Special Articles: The Micro Soldering Technology of Super High Density Packaging. Soldering Technology of Fine Pitch Packages." Circuit Technology 9, no. 7 (1994): 479–84. http://dx.doi.org/10.5104/jiep1986.9.479.

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43

Lecarpentier, Gilbert, and Joeri De Vos. "Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 002251–84. http://dx.doi.org/10.4071/2012dpc-tha15.

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Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

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Kilian, Arnd, Gustavo Ramos, Rick Nichols, et al. "Advances in Fine Pitch Off-Chip Interconnections Through the Use of a Novel Surface Finish." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 001531–63. http://dx.doi.org/10.4071/2015dpc-wp25.

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One constant in electronic system integration is the continuous trend towards smaller devices with increased functionality, driven by emerging mobile and high-performance applications. This brings the need for higher bandwidth at lower power, translating into increased I/O density, to enable highly-integrated systems with form factor reduction. These requirements result in the necessity of interconnection pitch-scaling, below 30 μm in the near future, and substrates with high wiring densities, leading to routing with sub 5 μm L/S where standard surface finishes (ENIG, ENEPIG) are no longer applicable. Copper pillar with solder caps technology is currently the prevalent solution for off-chip interconnections at fine pitch, dominating the high performance and mobile market with pitches as low as 40 μm in production. However, this technology faces many fundamental limitations in pitch scaling below 30 μm, due to solder bridging, IMC-solder interfacial stress management, and poor power handling capability of solders. All-copper interconnections without solder are very sought after by the semiconductor industry and have been applied to 3D-IC stacking, however no cost effective, manufacturable and scalable solution has been proposed to date for HVM and application to non CTE matched package structures. The low temperature Cu-Cu interconnection technology without solder recently patented by Georgia Tech PRC is one of the most promising solutions to this problem. The main bottleneck of copper oxidation is dealt with by application of ENIG on the Cu bumps and pads, enabling formation of a reliable metallurgical bond by thermocompression bonding (TCB) at temperatures below 200°C, in air, with cycle-times compatible with HVM targets. However, to ensure a bump collapse of 3 μm to overcome non-coplanarities and warpage, a pressure of 300MPa is used in the Process-of-Record (PoR) conditions, limiting the scalability of this technology. This paper introduces a novel Electroless Palladium / Autocatalytic Gold (EPAG) surface finish process, to enable the next generation of high density substrates and interconnections. With circa 100nm-thin Pd and Au layers, the EPAG finish can be applied to fine L/S wiring, with no risk of bridging adjacent Cu traces, even with spacing below 5 μm. Further, the EPAG finish is compatible with current interconnection processes; such as wire bonding, and the Cu pillar and solder cap technology for fine-pitch applications. For further pitch reduction, the EPAG surface finish was coupled to GT PRC's low-temperature Cu-interconnections, in an effort to reduce the bonding load for enhanced manufacturability without degrading the metallurgical bond or reliability. This paper is the first demonstration of such interconnections. The effect of the surface finish thickness and composition on the bonding load, assembly yield, quality of the metallurgical bond was extensively evaluated based on analysis of the metal interface microstructures and the chemical composition of the joints. The current PoR using Electroless Nickel / Immersion Gold (ENIG) coated Cu pillars and pads was used as reference. A novel surface finish is introduced, which allows formation of Cu-Cu interconnections without solder at lower pressure, between a silicon die and glass, organic or silicon substrate at fine pitch, allowing the performance improvements demanded by the IC Packaging Industry.

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45

Choi, Kwang-Seong, Ho-Eun Bae, Haksun Lee, Hyun-Cheol Bae, and Yong-Sung Eom. "Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers." International Symposium on Microelectronics 2013, no. 1 (2013): 000420–23. http://dx.doi.org/10.4071/isom-2013-tp66.

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A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

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46

Vallabhajosyula, Phani. "Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–18. http://dx.doi.org/10.4071/2017dpc-poster_vallabhajosyula.

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Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.

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47

Kloeser, J., K. Heinricht, K. Kutzner, E. Jung, A. Ostmann, and H. Reichl. "Fine pitch stencil printing of Sn/Pb and lead free solders for flip chip technology." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C 21, no. 1 (1998): 41–50. http://dx.doi.org/10.1109/3476.670027.

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48

Huang, Baigang, Jianjun Jiang, and Zaojian Zou. "Online Prediction of Ship Coupled Heave-Pitch Motions in Irregular Waves Based on a Coarse-and-Fine Tuning Fixed-Grid Wavelet Network." Journal of Marine Science and Engineering 9, no. 9 (2021): 989. http://dx.doi.org/10.3390/jmse9090989.

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A method based on a coarse- and fine-tuning fixed-grid wavelet networks is presented for online prediction of the coupled heave-pitch motions of a ship in irregular waves. The online modeling method contains two processes, i.e., coarse tuning and fine tuning. The coarse tuning is used to select the important wavelet terms, while the fine tuning is only used to compute the related coefficients of the selected wavelet terms. The Givens transformation algorithm is applied to realize the fine-tuning process. Due to the continuous fine-tuning process, the computational efficiency is improved significantly. Both simulation data and experimental data are used to verify the modeling method. The prediction results illustrate that the method has the ability to online predict the coupled heave-pitch motions of a ship in irregular waves.

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49

Leal, Jeff S., Suzette K. Pangrle, Charles Whyte, et al. "Fine Pitch 3D Dispensable Electrical Interconnects for System In Package Solutions." International Symposium on Microelectronics 2010, no. 1 (2010): 000559–65. http://dx.doi.org/10.4071/isom-2010-wp1-paper5.

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The use of dispensable conductive materials to create fine pitch 3D electrical interconnects has been proven by Vertical Circuits Inc. as a low cost, high reliability alternative to create System in Package (SIP) solutions. This paper discusses the benefits of dispensing the 3D electrical interconnects instead of using traditional wire bond or high cost TSV processes to create a System in Package. Pad pitches achieved are typically less than 65um. A conformal coating of a dielectric material with the subsequent selective laser ablation of the dielectric over the die pads allows all interconnect lines to be dispensed in a single application adjacent to each other. Compared to traditional wire bond applications, the overall interconnect inductance is lower with comparable capacitive and resistance values enabling higher frequencies to be achieved. Using this process, complex multi-step stacking and bonding applications that jeopardize known good die (KGD) and increase the XY footprint of the System in Package are eliminated. Furthermore, the entire die stacking process can be executed as a single step before the application of the electrical interconnect material. This method minimizes the overall material handling and repetitive die stack processes that increase the probability of defects leading to expensive yield losses. Methods for matching the Coefficient of Thermal Expansion (CTE) for the stacked components within a System in Package will be demonstrated as well as surface treatments to enable fine pitch dispense that result in increased product reliability. JEDEC L3 reliability data will be presented to demonstrate SIP robustness using this technology.

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Bhopte, Siddharth, Jesse Galloway, Kyung-Rok Park, et al. "Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 000441–54. http://dx.doi.org/10.4071/2013dpc-ta22.

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Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (&lt;60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

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