Journal articles on the topic 'FinFET vs. Nanosheet Transistors'

Nanosheet gate-all-around devices have demonstrated several advantages in device performance and area scaling over finFET devices with higher device density and improved electrostatic control. Robust inner spacer (IS) and channel formation is critical for high performance, reduced variability and good yield. An isotropic dry etch of the sacrificial SiGe layer with extremely high selectivity to gate spacer, IS and Si channels is necessary for high-quality channel formation over a wide range of sheet widths. Furthermore, the nFET Si:P and pFET SiGe:B source-drain (S/D) epitaxy must be isolated using inner spacers or buffers to prevent damage during Channel Release (CR). The damage can be further mitigated with optimized CR etch chemistry, enabling IS scaling. We highlight S/D damage mechanisms during CR, then demonstrate reduced S/D damage by co-optimization of the IS, CR chemistry and S/D epitaxy.

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2]. The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage amplifier, where the first stage is a differential amplifier with active load and the second one is a common source amplifier, as can be seen in figure 2. This analog block is biased through the current source and the bias current is mirrored for each stage. In addition, negative feedback is used between the first and second stages with a compensation capacitor (miller capacitor) in order to stabilize the amplifier response. In this work, an OTA circuit is designed with SOI omega-gate nanowire experimental transistors. In order to find the best device to be used in the project, some measurements were carried out of several nanowire devices with different channel lengths (ranging from 20 nm to 200 nm). The schematic structure of the measured devices is presented in figure 3 [2]. Basic device parameters such as: transconductance (gm), output conductance (gd), Early voltage (VEA), threshold voltage (VT), transistor efficiency (gm/ID) and subthreshold slope (SS) were analyzed. The model of the experimental omega-gate transistors was performed using the Look Up Table (LUT) method. The capacitance measurements of the nanowire transistor were also considered, to simulate the frequency responses more faithfully. The simulator used to design the OTA circuit was Cadence using the Verilog-A language. It was obtained the main figure of merit of this block like voltage gain (Av), gain-bandwidth product (GBW), phase margin and power. A transistor efficiency (gm/ID) near 8 V-1 was chosen in order to compare the performance of OTA designed with omega-gate nanowire devices (NW-OTA) of this work with anothers OTAs designed with triple gate FinFETs (FinFET-OTA) and with nanosheets (NS-OTA) from the literature (Table 1) [3,4]. Table 1 shows that the phase margin is close to 60o in all cases, ensuring the stability of the circuit. The NW-OTA presents higher voltage gain compared to FinFET-OTA due to the better gate to channel coupling. The NS-OTA presents the highest voltage gain of all cases, but it is the more expensive technology [4]. When GBW is analyzed for all 3 designs, the NW-OTA shows better results than the NS-OTA, using the same load capacitance of 200fF, thanks to the lower miller capacitance (Cc) required to keep the frequency behavior. The FinFET-OTA shows the best result in relation to GBW, but the FinFET-OTA project doesn’t consider a load capacitance, making the comparison unfair [3]. Figure 4 shows the gain and phase of the OTA using a SOI omega-gate nanowire transistors. In summary, the OTA designed with SOI omega-gate nanowire technology presents a better performance than FinFET one, can be implemented in a smaller area on the chip (smaller Cc capacitor and smaller number of fins in parallel) and it is a cheaper option compared to nanosheet one. Figure 1

Improvement of semiconductor device performances have been brought about by innovations in device structures such as SOI, FinFET and gate-all around FET. The FinFET devices saw a remarkable success owing to their high hole mobility. FinFET devices attain this preferable feature by having the (110)-surface channel. Recently, considerable progress has been made in the nanosheet transistor technology. Owing to the gate-all-around structure and the added dimension, the nanosheet transistor technology has an enormous potential for realization of the electronic devices with a significantly high performance. An issue for the nanosheet transistor is the degradation of the hole mobility. This problem stems from the following factors. First, currently developed nanosheet transistors are characterized as (100)-channel devices which have inferior character regarding the hole mobility. Secondly, for fabrication of nanosheet transistors, crystal growth of multiply stacked Si/SiGe layers is an essential process, which involves deterioration of the crystalline quality. The degradation of the crystalline quality is severer in the case of crystal growths on the (110)-surface than those on the (100)-surface. Therefore, the use of the (110)-wafer is challenging and methods to grow Si/SiGe multilayers on (110)-wafers with high quality is to be developed. The authors have been involved in the crystal growth and characterizations of Si/SiGe heterostructures on Si(110) wafers [1-4]. In these studies, a significant enhancement of the hole mobility in the strained Si layer was demonstrated. The results indicate the effect of the lattice strain on the energy band structure can overcome the adverse effects of the crystalline defects. In addition, characteristic features of the crystalline defects generated in the (110)-oriented heterostructures have been revealed. Along with the knowledge on the defect generation and the formation process of the surface morphology, the effect of strain is also a focus of this talk. We discuss first the effect of strain on the valence band structure of Si. It is shown that the effect of strain in reducing the hole cyclotron effective mass is more significant when the surface is (110) compared to the case where the surface is (100). Interestingly, the strain dependences of the hole cyclotron effective mass differ in these two cases. The computational investigation indicates that the lattice strain combined with the (110)-oriented surface is an effective method to increase the hole mobility. Next, a formation mechanism of the crystalline defects in SiGe grown on the (110) wafer is discussed. The TEM observations clearly show that the dominant crystalline defect induced by strain is a twin structure having the {111} twin boundary. The reason for the twin generation is understood in the framework of a dislocation theory. The shear stress acting on a (111) plane drives the atomic layer to form a stacking fault and/or a twin structure. The strength of the shear stress is higher in the case of the (110)-oriented SiGe film compared to the case of the (100) counterpart, which explains the small critical layer thickness of the SiGe on a Si(110) wafer. Finally, the formation process of the surface morphology during the growths of SiGe on Si(110) wafers is discussed. Even at the initial stages of the SiGe, difficulty in obtaining a flat surface is recognized [4]. Based on currently obtained experimental results, we discuss the effect of a surface inclination on the surface morphology. [1] K. Arimoto et al., Jpn. J. Appl. Phys. 59, SGGK06 (2020). [2] D. Namiuchi et al., Materials Science in Semiconductor Processing 113, 105052 (2020). [3] K. Arimoto et al., ECS Transactions 98 (5), 277 (2020). [4] S. Saito et al., Materials Science in Semiconductor Processing 113, 105042 (2020).

Abstract Self-heating effect (SHE) is a severe issue in advanced nano-scaled devices such as stacked nanosheet field-effect transistors (NS-FET), which raises the device temperature (T D), that ultimately affects the key electrical characteristics, i.e. threshold voltage (V T), DIBL, subthreshold slope (SS), I OFF, I ON, etc. SHE puts design constraints in the advanced CMOS logic devices and circuits. In this paper, we thoroughly investigated the impact of ambient temperature and interface thermal contact resistance induced-self heating effect in the NS-FET using extensive numerical simulations. The weak electron–phonon coupling, phonon scattering, and the ambient temperature-induced joule energy directly coupled with thermal contact resistance cause the SHE-induced thermal degradation, which increases the device temperature (T D) and affects the device reliability. The baseline NS-FET is well-calibrated with the experimental data and 3D quantum corrected drift-diffusion coupled hydrodynamic and thermodynamic transport models is used in our TCAD framework to estimate the impact of ambient temperature and interface thermal contact resistance on the device performance. Moreover, we also evaluate the SHE-induced performance comparison of NS-FET with conventional FinFET and found that thermal degradation in NS-FET potentially worsen the electrical characteristics. Thus, a detailed TCAD analysis shows that the ambient temperature and interface thermal contact resistances deteriorate the effective thermal resistance (R eff) and device performance metrics.

As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. Exploring performance improvement techniques, such as channel strain engineering, is important for next generation CMOS technologies. It is difficult, however, to effectively induce strain into the channel region using source/drain stressors in scaled GAA NS structures due to reduction of the stressor (embedded SiGe in source/drain region) volume as transistor dimension shrinks. In addition, strain relaxation of source/drain stressors caused by introduction of crystalline defects decreases effectiveness to induce strain into the channel region. This is more pronounced by the fact that achieving superior epitaxial growth is more difficult on the GAA NS device structure due to the presence of inner spacer dielectric. Therefore, we proposed a stacked GAA NS pFET device with compressively strained SiGe channel. The SiGe channel NS devices were fabricated using Si NS channel trimming by selective isotropic dry etch and selective SiGe epitaxial growth techniques after the Si NS channel release (Fig. 1). This is the preferable scheme in terms of strain retention in the SiGe channel NS region since there are no patterning processes that cause strain relaxation during downstream processing. To investigate the device characteristics of SiGe NS devices, we fabricated strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET and investigated the crystallinity and strain in the channel region. Fig. 2 contains cross-sectional TEM images across the gate after Si0.7Ge0.3 channel formation. We observed no visible crystalline defects in the 4 nm-thick Si0.7Ge0.3 layer grown on the 2 nm-thick trimmed Si NS, indicating superior crystallinity of Si0.7Ge0.3 layer. To investigate strain in the nanoscale strained SiGe NS channel structures, Precession Electron Diffraction (PED) characterization was performed to evaluate lattice deformation of the stacked SiGe NS channel with 4 nm-thick Si0.7Ge0.3 epitaxial growth. Lattice deformation values are defined as the difference between in-plane lattice constants and the Si lattice constant, normalized by the Si lattice constant. Fig. 3 shows in-plane lattice deformation contour maps in the region of the stacked SiGe NS channel obtained from both X-cut (across the gate) and Y-cut (along the gate) for the SiGe NS structure with sheet width of 20 nm. The in-plane lattice deformation values were extracted from the middle of the SiGe NS channel as shown in Fig. 4. Preservation of half the amount of strain along the channel direction ([110]) was confirmed whereas strain along the NS width direction ([1-10]) was found to be almost fully relaxed due to elastic relaxation. This results in the Si0.7Ge0.3 channel being uniaxially stressed. The compressive stress along the channel direction estimated from the [110] lattice deformation is ~1 GPa. Normalized hole mobility in the representative Si1-xGex channel NS pFET as a function of inversion carrier density (Ninv) is shown in Fig. 5. The hole mobility of Si1-xGex channel (x = 0.35) with Si cap is almost 100% higher than that of Si NS channel. The mobility benefit of Si1-xGex channel is attributed to reduced effective hole mass along the transport direction caused by a high compressive strain in the Si1-xGex channel. The technique demonstrated in this study for forming compressively strained SiGe channel NS has great potential to improve pFET device performance for next generation of CMOS logic in GAA Nanosheet technology. Figure 1

Nanosheet (NS) gate-all-around (GAA) devices have demonstrated advantages in device performance and area scaling over finFET devices [1-11]. Enablement and future scaling of GAA devices require robust etch processes for Inner Spacer (IS) and Channel Release (CR) for well-controlled device performance and yield (Fig. 1). CR requires an isotropic, complete etch of the sacrificial SiGe layer with extremely high selectivity to the spacer (Sp0), IS, and Si channels. Furthermore, during CR, the Si channels must be released simultaneously for all sheet widths (WNS) [1], which range from 20nm to 100nm, necessitating significant over-etch (OE) on the narrowest sheets. We demonstrated excellent device performance across all WNS with more than 150 % OE on the widest sheets [1]. However, this extreme OE makes the pFET source/drain (S/D) SiGe:B especially vulnerable to damage. In this paper, we explore several mechanisms that result in SiGe:B S/D damage and demonstrate how to prevent the damage with IS, CR, and S/D epitaxial optimization. The S/D Si:B and Si:P used in our high-performance test devices are not susceptible to damage during CR due to high etch selectivity [2]. Thus, SiGe:B S/D is required to evaluate the mechanisms causing S/D damage. To enable these studies, we developed high-quality S/D SiGe:B, which shows substantial device performance improvement over our baseline S/D Si:B, with 150% increase in peak mobility, 50% reduction in Vt, and 45% reduction in Ron (Fig. 2). The ability to target IS thickness allows tuning of device performance through Cov and Ron and is critical for future device scaling. In addition, the IS plays a critical role as a physical barrier to prevent S/D damage during CR [1,2]; reducing IS thickness below a critical value can result in S/D damage. The optimal IS thickness is determined by balancing maximum device performance for all WNS while maintaining S/D integrity during CR. This process window can be maximized by optimizing the CR etch process, and can be further increased by integrating an Si:B buffer in the S/D epitaxy. We have developed four CR processes with different chemistries and evaluated their process windows. We evaluated S/D damage for two CR processes versus IS thickness. We observed no S/D damage with Process A until 4nm IS thickness at 50% OE (Fig. 3a). Process C showed no damage at 4nm IS thickness, even up to 100% OE. The plan-view TEM in Fig. 3a shows that S/D damage occurs at the corners of the S/D region as well as at the center, indicating several mechanisms for S/D damage (see Fig. 4): CR etch gas permeation through the IS, exposed S/D through pinholes in the IS or at the IS edges due to rounded IS shape, and exposed S/D at the intersection of the Si/SiGe fins and gate. To isolate and characterize permeation of the CR etch gas through the IS, we deposited various thicknesses of IS on SiGe/Si multilayers (Fig. 5a), then exposed the structures to CR Process A. The SiGe layers showed no damage until the IS layer was thinned to <1nm. The difference in critical thickness for etch gas permeation on fully integrated structures compared to these test structures (4nm compared to <1nm) could be attributed to the other mechanisms. S/D damage due to IS permeation can be prevented by a better quality IS; by optimizing the CR chemistry to tune the selectivity between the sacrificial SiGe and the S/D SiGe:B (Fig. 5b); or by integrating a Si:B buffer prior to S/D SiGe:B deposition (Fig. 6). The process window then can be maximized by selecting the best CR process since selectivity to Si:B and permeation through the IS varies with the chemistry. Fig. 7 shows the improvement in the process window with a 2nm Si:B buffer on wafers with no IS for Processes A, B and C. The other S/D damage mechanisms highlighted in Fig. 4 are characterized in Fig. 3b. The S/D damage starts at the corners of the active region and the extent of damage increases with CR OE. These failure modes require changes in integration to improve the Sp0 at the fin-gate corner, reducing the IS rounding, or creating a straighter etch front across the sheet [2]. S/D damage during CR is a significant issue in NS architecture. This can be mitigated by optimizing the CR etch process, incorporating an Si:B buffer layer, improving the IS quality or shape, and improved integration. Understanding these mechanisms is critical to ensure robust S/D quality with scaling for future technology nodes. Figure 1

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related μFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole μFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

The field of electronic devices and materials has seen major changes over the last ~20 years. The SiGe, Ge, & Related Compounds: Material Processing, and Devices symposium has documented much of this change. In 2004 the meeting grew out of a desire for the ECS to have a special ongoing symposium on SiGe & Ge as a materials system with increasing importance in silicon semiconductor technology. In 2008 the symposium was expanded to include Ge and Related compounds including SiC and III-Vs on Silicon to recognize the important work in these areas. In 2010 the symposium was expanded to include work in nano-wires, nano-membranes, and light emitting structures with SiGe and/or Ge. In 2012 the symposium explored finfet devices and expanded to include the area of GeSn. In 2014 the symposium explored the use SiGe and related compounds in more complex and advanced structures. In 2016 the conference had a theme around SOI and the FDSOI technology in particular. In 2018 the themes were the ever expanding device structures and role epitaxy has played in it. Each year the plenary talks were selected to give a view of the industry and the conference. These talks give us insight into the symposium and how the field has changed over time. In 2004 the first symposium “SiGe 1: Materials, Processing, and Devices” focused on the SiGe HBT transistor performance and SiGe epitaxial technology. But CMOS scaling was also presented. These trends were reflected in the plenary talks were given by John Cressler on “Using SiGe HBTs for Mixed-Signal Circuits and Systems: Opportunities and Challenges” and Judy Hoyt on “Enhanced Mobility CMOS.” This was the first symposium and we set the conference organization with multiple topical committees and published the first proceedings. In 2006 the “SiGe and Ge 2” symposium continued the themes of SiGe and Ge Epitaxy, SiGe HBT, CMOS scalling, and added silicon photonics. The Plenary talks were given by Dimitris Antoniadis on “Channel Material Innovations for Continuing the Historical MOSFET Performance Increase with Scaling” and Cary Gunn on “CMOS Photonics for High Speed Interconnects.” In 2008 the “SiGe, Ge, & Related Compounds 3” symposium changed in composition bringing IIIV and other compounds into the symposium. The Plenary papers were by Krishna Saraswat on “Germanium for High-Performance MOSFETS and Optical Interconnects,” and Wiebe B. de Boer on “Si and SiGe Epitaxy in Perspective.” Krishna focused on the role of Ge in modern devices and Wiebe focused on the history of SiGe epitaxy at ASM. In 2010 the “SiGe, Ge, & Related Compounds 4” greatly expanded topics while maintaining the core of SiGe HBT and CMOS scaling. The plenary papers were given by K. Kuhn on “Past, Present, and Future: SiGe and CMOS Transistor Scaling” and L. Kimmerling on “Scaling Energy and Form Factor with Germanium Microphotonics.” The conference emphasis continued on SiGe epitaxy, CMOS scaling, and HBT performance with a new optoelectronics focus area. In 2012 the “SiGe, Ge, & Related Compounds 5” focused on the finfet and GeSn. The plenary papers were given by E. Nowak “Advanced CMOS scaling and FinFET Technology” and C. Hu on “FinFET and UTB – How to make very short channel MOSFETs.” There were 4 sessions containing papers with GeSn. In 2014 the “SiGe, Ge, & Related Compounds 6” returned to CMOS scaling and the SiGe HBT. The plenary papers were given by K. Uchida and T. Takahashi on “Extending the FETs: Challenges and Opportunities for New Materials and Structures” and L. Zimmermann (IHP) on “High-Performance Photonic BiCMOS – Next Generation More-than-Moore Technology for the Large Bandwidth Era.” In 2016 the “SiGe, Ge, & Related Compounds 7” focused on FDSOI. The plenary papers were given by Bruce Doris “FDSOI Past, Present and Future” and Carlos Mazure and S. Cristoloveanu “ FD-SOI: The History from Early Transistors to Today.” In 2018 the “SiGe, Ge, & Related Compounds 8” focused on CMOS scaling and SiGe as an enabling material. The plenary papers were given by Maszara, Witold on “Contemporary and Future Logic Devices” and by Tsu-Jae Liu on “ Silicon-Germanium: Enabler of Moore's Law.” In 2020 the “SiGe, Ge, & Related Compounds 9” symposium focused on III-Vs and Silicon Photonic Sensors. The plenary papers were given by N. Collaert on “The revival of compound semiconductors and how they will change the world in the 5G/6G era,” and Ben Miller on “Creating the Interface Universe between the Universe and Data with Integrated Photonic Sensors." Highlights from these plenary talks and symposium topics will be presented.

The dimensionality of semiconductors has a crucial role in determining their properties. Recently, metal halide perovskites have been demonstrated with many exciting applications, attracting wide attention to further their development for advanced optoelectronics, such as photovoltaics, photodetectors, light-emitting diodes, and lasers. At length scales down to nanoscale regimes, surface features as well as quantum confinement effects become dominant in regulating the material properties of perovskite materials. In past years, our group focus on the synthesis and characterization of metal halide perovskites with different configurations, ranging from bulk films, microplates, nanosheets, to nanowires. The corresponding physical properties and device applications were also systematically studied based on their widely tunable dimensionality, morphologies, and compositions. Specifically, for perovskite bulk films, surface defects and bulk structural order significantly affect their device performance. Through optimizing processing techniques, self-assembled quasi-2D perovskite films with graded phase distribution were successfully prepared. Gradient type-II band alignments along the out-of-plane direction of perovskites with spontaneous separation of photo-generated electrons and holes are obtained, which is later employed to construct self-powered vertical-structure photodetectors for the first time. Without any driving voltage, the device exhibited impressive performance with the responsivity up to 444 mA/W and ultrashort response time down to 52 µs. In addition, to assess the intrinsic material properties of crystalline perovskites, freestanding MAPbI3 nanosheets and lead-free Cs3Sb2I9 microplates were fabricated by two-step chemical vapor deposition method, in which excellent optoelectronic performance (e.g., responsively of MAPbI3 nanosheet is measured to be 40 A/W) together with ultra-fast response speed (down to 58 µs) and superior thermal stability were obtained. For nanostructured perovskites, understanding the dimensional features and their impact on the materials and devices is becoming increasingly important. Lately, we reported the direct vapor-liquid-solid growth of single-crystalline all-inorganic lead halide perovskite (i.e., CsPbX3; X = Cl, Br, or I) NWs. These NWs exhibited high-performance photodetection with the responsivity exceeding 4489 A/W and detectivity over 7.9 × 1012 Jones toward the visible light regime. Field-effect transistors based on individual CsPbX3 NWs were also fabricated to show the impressive carrier mobility of 3.05 cm2/Vs, being higher than other all-inorganic perovskite devices. Besides, the realization of high-mobility CsPbBr3 NW devices is reported via a simple surface charge transfer doping strategy. After MoO3 decoration and device fabrication, the hole mobility of CsPbBr3/MoO3 core-shell NW device is significantly enhanced to 23.3 cm2/Vs. All these results provide important guidelines for the further improvement of these perovskite nanostructures for practical utilization.

The success of lead halide perovskites as active materials in optoelectronic technologies is often associated with the unique properties of their optical excitations. Specifically, the photo-generated excitons in perovskites are responsible for the large absorption coefficients close to their band gap, reaching as high as 105 cm-1. Due to the advent of nanotechnology, perovskite materials can be readily fabricated into nanoscale configurations with different dimensionalities, and more importantly, the corresponding excitonic effects could be further enhanced. On the other hand, at length scales down to the nanoscale regime, surface features as well as quantum confinement effects, become dominant in regulating the advanced material properties of perovskite materials. [1, 2] In recent years, our group focused on the synthesis and characterization of metal halide perovskites with different forms, ranging from bulk film, microplate, and nanosheet, to nanowire. The corresponding physical properties and device applications were also systematically studied based on their widely tunable dimensionality, morphologies, and compositions. For perovskite bulk films, surface defects and bulk structural order significantly affect device performance. Through optimizing processing techniques, self-assemble quasi-2D perovskite films with graded phase distribution were successfully prepared by our group. [3] Gradient type-II band alignments along the out-of-plane direction of perovskites with spontaneous separation of photo-generated electrons and holes are obtained, which is further employed to construct self-powered vertical-structure photodetectors for the first time. Without any driving voltage, the device exhibited impressive performance with responsivity up to 444 mA/W and ultrashort response time down to 52 µs. In addition, to probe the intrinsic material properties of crystalline perovskites, freestanding MAPbI3 nanosheets, and lead-free Cs3Sb2I9 microplates were fabricated by two-step chemical vapor deposition method, in which excellent optoelectronic performance (e.g., responsively of MAPbI3 nanosheet is measured to be 40 A/W) together with ultra-fast response speed (down to 58 µs) and superior thermal stability were obtained. [4, 5] For nanostructured perovskites, understanding the dimensional features and their impact on the materials and devices is becoming increasingly important. For the first time, we reported the direct vapor-liquid-solid growth of single-crystalline all-inorganic lead halide perovskite (i.e., CsPbX3; X = Cl, Br, or I) NWs using Sn as catalyst seeds. [6] These NWs exhibited high-performance photodetection with the responsivity exceeding 4489 A/W and detectivity over 7.9 × 1012 Jones toward the visible light regime. Field-effect transistors based on individual CsPbX3 NWs were also fabricated to show the impressive carrier mobility of 3.05 cm2/Vs, being higher than other all-inorganic perovskite devices. After that, the Au catalyst seeds were used to avoid the Sn-related impurity doping, by which lower dark current and higher detectivity were achieved in Au-seeded CsPbI3 NWs. Besides, the realization of high-mobility CsPbBr3 NW devices is reported via a simple surface charge transfer doping strategy. [7] After MoO3 decoration and device fabrication, the hole mobility of CsPbBr3/MoO3 core-shell NW device is significantly enhanced to 23.3 cm2/Vs. All these results provide important guidelines for the further improvement of these perovskite nanostructures for practical utilization. References [1] Meng Y.†, Li F.†, Lan C., Bu X., Kang X., Wei R., Yip S., Li D., Wang F., Takahashi T., Hosomi T., Nagashima K., Yanagida T., Ho J.C.*, Science Advances, 6, eabc6389, 2020. [2] Li D., Lan C., Manikandan A., Yip S.P., Zhou Z., Liang X., Shu L., Chueh Y.L., Han N.,* Ho J.C.*, Nature Communications, 10, 1664, 2019. [3] Lai Z., Meng Y., Zhu Q., Wang F., Bu X., Li F., Wang W., Liu C., Wang F., Ho J.C.*, Small, 17, 2100442, 2021. [4] Lan C., Dong R., Zhou Z., Shu L., Li D., Yip S.P., Ho J.C.*, Advanced Materials, 29, 1702759, 2017. [5] Shil S.K.†, Wang F.†,*, Lai Z., Meng Y., Wang Y., Zhao D., Hossain M.K., Egdo K.O., Wang Y., Yu K.M.*, Ho J.C.*, Nano Research, 14, 4116-4124, 2021. [6] Meng Y., Lan C., Li F., Yip S.P., Wei R., Kang X., Bu X., Dong R., Zhang H., Ho J.C.*, ACS Nano, 13, 6060-6070, 2019. [7] Meng Y., Lai Z., Li F., Wang W., Yip S.P., Quan Q., Bu X., Wang F., Bao Y., Hosomi T., Takahashi T., Nagashima K., Yanagida T., Lu J., Ho J.C.*, ACS Nano, 14, 12749-12760, 2020.

The aim of this work is to perform an in-depth analysis in order to identify the key contributors to the total flicker noise in advanced MOSFET technologies, e.g. UTBOX, FinFET or Gate-all-around (GAA) nanowire or nanosheet FET devices. In this abstract, as an example, we will focus on p-type gate all around silicon vertical nanowire devices fabricated at imec. The transistors have a fixed gate length (LG) of 50 nm and 1200 nanowires in parallel (N), each nanowire (NW) having a diameter (WNW) of 20 nm. The total width (W) of the device is calculated as . The gate stack corresponds to an equivalent oxide thickness (EOT) of 0.9 nm. A full description of the process flow of the devices is presented in [1]. Comparison between the Y-function strategy of [2] and McLarty methodology [3] permits to estimate with accuracy the DC parameters necessary for low frequency noise modelling, which are summarized in Table 1. Typical low frequency noise spectra are shown in Figure 1. The methodology for the estimation of the low frequency noise parameters is described in [4], but it is obvious that the noise spectra are dominated by 1/f noise and only few Lorentzian contributions appear for some gate voltage polarization. As the corresponding flicker noise levels (K f ), plotted in Figure 2 present a plateau and rise with the increase of the applied gate voltage, the responsible 1/f noise mechanism should be related to the carrier number or correlated carrier number fluctuations mechanism, with a possible contribution of the access resistance 1/f noise. Firstly, the model described in [5-9] expressed as in equation (1) is employed. A linear dependence of the square root of the 1/f noise levels on the measured Id/gm is observed in Figure 3, permitting to estimate from the intercept and slope the flat-band noise level (Svfb) and the W coefficient, respectively. Using the methodology of [9] the estimated W parameter is corrected by the access resistance influence. Good agreement with experimental data in strong inversion may be observed in both cases (Figure 4). Secondly, the model which considers the small signal model of the MOSFET is used, assuming that the channel resistance noise and access resistances noise are uncorrelated noise sources [2,10,11]. The model may be expressed by equation (2) ((13) of [11]), in order to make no assumption concerning the gm/gch ratio. Beyond the threshold voltage, the impact of the cannot be neglected, as observed from Figure 5. It may be observed from Figure 6 that the correlated number fluctuation and mobility noise mechanism cannot explain the flicker noise behavior in very strong inversion, and an additional contribution of the access resistances noise may be considered in order to agree with the experimental data. The noise parameters estimated to agree with the experimental data for both models are summarized in Table 2. It is interesting to note that the experimental data may be explained by both models, but the key contributors are not the same: only correlated number fluctuations and mobility noise mechanism for the first model, and correlated number fluctuations and mobility and access resistance noise mechanisms contribution for the second one. Moreover, the estimated flat-band noise levels are not the same, a much lower Svfb is obtained when the first model is employed. Considering the access resistance impact may correct the W coefficient, but leads to even lower flat-band noise levels, as already reported in [9]. These results lead to some questioning about which of these two models is most accurate and give good indications on the key contributors and estimated parameters of the total flicker noise. References: [1] E. Simoen et al., Solid-State Electron, 2023, 200, DOI: 10.1016/j.sse.2022.108576. [2] B. Cretu et al., IEEE Trans. Electron Dev., 2023, 70(1), 254-260, DOI: 10.1109/TED.2022.3225248. [3] P.K. McLarty et al., Solid-State Electron, 1995, 6, 1175-1177, DOI: 10.1016/0038-1101(94)00248-E [4] D. Boudier et al., Solid-State Electronics, 2019, 168, DOI : 10.1016/j.sse.2019.107732. [5] E. G. Ioannidis et al., Solid-State Electron., 2012, 76, 54–59, DOI: : 10.1016/j.sse.2012.05.035. [6] C. G. Theodorou et al., IEEE Trans. Electron Dev., 2014, 61(2), 1161-1167, DOI: 10.1109/TED.2014.2307201. [7] E. G. Ioannidis et al., IEEE Trans. Electron Dev., 2015, 62(5), 1574-1579, DOI: 10.1109/TED.2015.2411678. [8] A. Tataridou et al., in Proc. IEEE 33rd Int. Conf. Microelectron. Test Struct. (ICMTS), 2020, DOI: 10.1109/ICMTS48187.2020.9107908. [9] A. Tataridou et al., IEEE Trans. Electron Dev., 2020, 67(11), 4568-4572, DOI: 10.1109/TED.2020.3026612. [10] D. Boudier et al., Solid-State Electron, 2017, 128, 102-108, DOI: 10.1016/j.sse.2016.10.012. [11] B. Cretu et al., Solid-State Electron, 2023, 201, DOI: 10.1016/j.sse.2023.108591 Figure 1

Self-heating in surround gate (e.g., nanosheet, nanowire, and FinFET) transistors degrades their on-current performance and reduces their lifetime. If a transistor heats/cools with time constants much shorter than the inverse of the operating frequency, predictable, frequency-independent performance is expected; if not, the operating frequency must be optimized for the highest performance. Typically, time constants are measured by expensive, ultra-fast instruments with high temporal resolution. Instead, here, we demonstrate an alternate, inexpensive, cyclostationary measurement technique to characterize self-heating (and cooling) with sub-microsecond resolution. The results are independently confirmed by direct imaging of the transient heating/cooling of the channel temperature by the thermoreflectance method. Routine use of the proposed technique will help improve the design of the surrounding gate transistors and shorten their design cycle.

Abstract As demand for advanced integrated circuits (ICs) continues to grow, fin field-effect transistors (FinFETs) have remained highly influential in the IC market because of their mature fabrication process and powerful driving capabilities. However, the ion bombardment that occurs during the reactive ion etching (RIE) process used to form the fin structure increases the fin's surface roughness and results in a high interfacial state density (Dit), which hinders further improvement in the subthreshold swing (SS) of FinFETs. To overcome this issue, this study proposes two oxidative trimming methods for use on the fin structures to improve their interface quality. It is found that conventional thermal oxidation and low-temperature oxidation processes reduced the channel Dit by 73.31% vs. 71.17%, respectively. Furthermore, the corresponding SS values of the device improved to 72.76 and 71.72 mV/dec, respectively. The technical solutions proposed in this paper represent a promising approach for performance optimization of FinFETs and other advanced devices.

Abstract An innovative breakthrough that addresses the shortcomings of FinFET is the use of tree-shaped Nanosheet FET. This study examines the temperature dependence of the performance of 12 nm Tree-shaped NSFET on DC and analog/RF properties using a gate stack of high-k HfO2 and SiO2. From 200 K to 350 K, a detailed DC performance analysis was performed, including the transfer characteristics (ID vs VGS), output characteristics (ID vs VDS), subthreshold swing (SS), and ION/IOFF ratio. Additionally, we examined how temperature influence power consumption, dynamic power, and the ON-OFF performance metric (Q). Having the off current lesser than nA at all the temperatures, the proposed device shows good ION/IOFF switching performance. At an LG of 12 nm, the cutoff frequency (fT) is found to be in the Tera Hz region, and the Q varies from 0.9 to 5.1 μS-dec/mV at temperatures between 200 K and 350 K. Additionally, the impact of IB height (HIB) is investigated at 15–25 nm with the step of 5nm and the impact of IB width (WIB) is investigated at 3 - 5 nm on Tree-shaped NSFET and the impact of variation in the work function is also done in this paper. The effect of scaling with different gate lengths from 20 nm down to 10 nm and its DC characteristics are examined in this paper. The power consumption of the Tree-shaped NSFET increases with temperature. From all these results, the proposed Tree-shaped NSFET shows great potential as a high-frequency competitor at the nanoscale.

AbstractToday's display industry faces transistor‐level challenges similar to those of complementary metal‐oxide semiconductor (CMOS) metal‐oxide semiconductor field‐effect transistors (MOSFETs) in the mid‐1990s. Learnings from MOSFETs inform the display industry's response to the limitations of silicon‐based thin‐film transistors (TFTs). Improvements sustaining Moore's Law drove the need to rethink MOSFET materials and structures. The display industry needs fundamental innovation at the device level. New thin‐film devices enable an inflection point in the use of displays, just as fin field‐effect transistor (FinFET) defined the inflection point in CMOS in the 2000s. This paper outlines two innovations in thin‐film device technology that offers improvement in image quality and power consumption of flat panel displays: amorphous metal gate TFTs (AMeTFTs) and amorphous metal nonlinear resistors (AMNRs). Linked through a single core material set based on mass‐producible, thin‐film amorphous metals, these two innovations create near‐ and long‐term roadmaps simplifying the production of high‐image quality, low‐power consumption displays on glass (now) and plastic (future). In particular, the field‐effect mobility of indium gallium zinc oxide (IGZO) AMeTFTs (55–72 cm2/Vs) exceeds that of IGZO TFTs developed by existing display manufacturers without the need for atomic layer deposition or vertical stacking of heterostructure semiconductor films, making AMeTFTs a natural choice for the new G8.5–G8.7 fabs targeting IGZO backplanes.