Log in

Relevant bibliographies by topics / FinFET vs. Nanosheet Transistors / Journal articles

To see the other types of publications on this topic, follow the link: FinFET vs. Nanosheet Transistors.

Journal articles on the topic 'FinFET vs. Nanosheet Transistors'

Author: Grafiati

Published: 5 June 2025

Last updated: 16 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 23 journal articles for your research on the topic 'FinFET vs. Nanosheet Transistors.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Rajat, Suvra Das. "A Systematic Literature Review on Advanced FinFET Technology and Beyond: Exploring Novel Transistor Architectures and Assessing their Potential for Future Semiconductor Applications." European Journal of Advances in Engineering and Technology 9, no. 12 (2022): 122–30. https://doi.org/10.5281/zenodo.10901221.

Full text

Abstract:

<strong>ABSTRACT</strong> In the ever-progressing field of semiconductor technology, the pursuit of heightened performance, energy efficiency, and scalability has prompted a shift beyond the conventional FinFETs. This study explores advanced FinFET technology and extends its focus to emerging transistor architectures, namely nanosheet transistors and Tunnel FETs, evaluating their potential impact on semiconductor applications. The analysis commences with an in-depth examination of FinFETs, acknowledging their pivotal role in the past decade but recognizing their limitations as semiconductor te

APA, Harvard, Vancouver, ISO, and other styles

2

Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

Full text

Abstract:

Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this r

APA, Harvard, Vancouver, ISO, and other styles

3

Wong, Hei, and Kuniyuki Kakushima. "On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node." Nanomaterials 12, no. 10 (2022): 1739. http://dx.doi.org/10.3390/nano12101739.

Full text

Abstract:

This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 5

APA, Harvard, Vancouver, ISO, and other styles

4

Rosseel, Erik, Clement Porret, Thomas Dursap, et al. "Source/Drain Epitaxy for Nanosheet-Based CFET Devices." ECS Transactions 114, no. 2 (2024): 29–36. http://dx.doi.org/10.1149/11402.0029ecst.

Full text

Abstract:

This work reports the progress in source/drain (S/D) epitaxy development for nanosheet-based monolithic complementary field effect transistors (mCFET). S/D processes which were set-up for bulk finFET devices can be easily transferred to mCFET devices. Owing to the complicated integration and small dimensions of the highly scaled structures however, more attention is required for the pre-epi cleaning of the exposed channel interfaces and for the additional defectivity that arises from the merging of individual epitaxial growth fronts. Low-temperature epi processes can be structurally integrated

APA, Harvard, Vancouver, ISO, and other styles

5

Chiang, Te-Kuang. "A Unified Semiconductor-Device-Physics-Based Ballistic Model for the Threshold Voltage of Modern Multiple-Gate Metal-Oxide-Semiconductor Field-Effect-Transistors." Electronic Materials 5, no. 4 (2024): 321–30. https://doi.org/10.3390/electronicmat5040020.

Full text

Abstract:

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi–Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, Ω-gate MOSFET, and nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate ballistic effects and resist threshold voltage degradation. In ad

APA, Harvard, Vancouver, ISO, and other styles

6

Chen, Zhuo, Huilong Zhu, Guilei Wang, et al. "High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale." Nanomaterials 13, no. 12 (2023): 1867. http://dx.doi.org/10.3390/nano13121867.

Full text

Abstract:

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules

APA, Harvard, Vancouver, ISO, and other styles

7

Durfee, Curtis, Ivo Otto IV, Subhadeep Kal, et al. "Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors." ECS Transactions 112, no. 1 (2023): 45–52. http://dx.doi.org/10.1149/11201.0045ecst.

Full text

Abstract:

Nanosheet gate-all-around devices have demonstrated several advantages in device performance and area scaling over finFET devices with higher device density and improved electrostatic control. Robust inner spacer (IS) and channel formation is critical for high performance, reduced variability and good yield. An isotropic dry etch of the sacrificial SiGe layer with extremely high selectivity to gate spacer, IS and Si channels is necessary for high-quality channel formation over a wide range of sheet widths. Furthermore, the nFET Si:P and pFET SiGe:B source-drain (S/D) epitaxy must be isolated u

APA, Harvard, Vancouver, ISO, and other styles

8

Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

Full text

Abstract:

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) n

APA, Harvard, Vancouver, ISO, and other styles

9

de Araujo, Gustavo Vinicius, Joao Martino, and Paula Agopian. "Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1861. http://dx.doi.org/10.1149/ma2023-01331861mtgabs.

Full text

Abstract:

The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2]. The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage

APA, Harvard, Vancouver, ISO, and other styles

10

Arimoto, Keisuke. "(110)-Surface Strained-Channel MOSFETs." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2372. https://doi.org/10.1149/ma2024-02322372mtgabs.

Full text

Abstract:

Improvement of semiconductor device performances have been brought about by innovations in device structures such as SOI, FinFET and gate-all around FET. The FinFET devices saw a remarkable success owing to their high hole mobility. FinFET devices attain this preferable feature by having the (110)-surface channel. Recently, considerable progress has been made in the nanosheet transistor technology. Owing to the gate-all-around structure and the added dimension, the nanosheet transistor technology has an enormous potential for realization of the electronic devices with a significantly high perf

APA, Harvard, Vancouver, ISO, and other styles

11

Rathore, Sunil, Rajeewa Kumar Jaisawal, Preeti Suryavanshi, and Pravin N. Kondekar. "Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET." Semiconductor Science and Technology 37, no. 5 (2022): 055019. http://dx.doi.org/10.1088/1361-6641/ac62fb.

Full text

Abstract:

Abstract Self-heating effect (SHE) is a severe issue in advanced nano-scaled devices such as stacked nanosheet field-effect transistors (NS-FET), which raises the device temperature (T D), that ultimately affects the key electrical characteristics, i.e. threshold voltage (V T), DIBL, subthreshold slope (SS), I OFF, I ON, etc. SHE puts design constraints in the advanced CMOS logic devices and circuits. In this paper, we thoroughly investigated the impact of ambient temperature and interface thermal contact resistance induced-self heating effect in the NS-FET using extensive numerical simulation

APA, Harvard, Vancouver, ISO, and other styles

12

Mochizuki, Shogo, Juntao Li, Erin Stuckert, Huimei Zhou, and Nicolas Loubet. "Compressive Strained Si_1-XGe_x Channel for High Performance Gate-All-Around Nanosheet Transistors." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1192. http://dx.doi.org/10.1149/ma2022-02321192mtgabs.

Full text

Abstract:

As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. E

APA, Harvard, Vancouver, ISO, and other styles

13

Durfee, Curtis, Ivo Otto IV, Subhadeep Kal, et al. "Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1517. http://dx.doi.org/10.1149/ma2023-02301517mtgabs.

Full text

Abstract:

Nanosheet (NS) gate-all-around (GAA) devices have demonstrated advantages in device performance and area scaling over finFET devices [1-11]. Enablement and future scaling of GAA devices require robust etch processes for Inner Spacer (IS) and Channel Release (CR) for well-controlled device performance and yield (Fig. 1). CR requires an isotropic, complete etch of the sacrificial SiGe layer with extremely high selectivity to the spacer (Sp0), IS, and Si channels. Furthermore, during CR, the Si channels must be released simultaneously for all sheet widths (WNS) [1], which range from 20nm to 100nm

APA, Harvard, Vancouver, ISO, and other styles

14

Mo, Fabrizio, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, and Marco Vacca. "NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance." Electronics 12, no. 6 (2023): 1487. http://dx.doi.org/10.3390/electronics12061487.

Full text

Abstract:

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compa

APA, Harvard, Vancouver, ISO, and other styles

15

Yen, Te Jui, Albert Chin, and Vladimir Gritsenko. "Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer." Nanomaterials 11, no. 1 (2021): 92. http://dx.doi.org/10.3390/nano11010092.

Full text

Abstract:

Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526

APA, Harvard, Vancouver, ISO, and other styles

16

Harame, David L. "Perspectives on How the "Sige, Ge, & Related Compounds: Materials, Processing, and Devices" Field Has Changed over the Last 20 Years." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1181. http://dx.doi.org/10.1149/ma2022-02321181mtgabs.

Full text

Abstract:

The field of electronic devices and materials has seen major changes over the last ~20 years. The SiGe, Ge, & Related Compounds: Material Processing, and Devices symposium has documented much of this change. In 2004 the meeting grew out of a desire for the ECS to have a special ongoing symposium on SiGe & Ge as a materials system with increasing importance in silicon semiconductor technology. In 2008 the symposium was expanded to include Ge and Related compounds including SiC and III-Vs on Silicon to recognize the important work in these areas. In 2010 the symposium was expanded to inc

APA, Harvard, Vancouver, ISO, and other styles

17

Ho, Johnny C. "(Invited) From Bulk to Nanostructured Perovskites." ECS Meeting Abstracts MA2022-02, no. 36 (2022): 1307. http://dx.doi.org/10.1149/ma2022-02361307mtgabs.

Full text

Abstract:

The dimensionality of semiconductors has a crucial role in determining their properties. Recently, metal halide perovskites have been demonstrated with many exciting applications, attracting wide attention to further their development for advanced optoelectronics, such as photovoltaics, photodetectors, light-emitting diodes, and lasers. At length scales down to nanoscale regimes, surface features as well as quantum confinement effects become dominant in regulating the material properties of perovskite materials. In past years, our group focus on the synthesis and characterization of metal hali

APA, Harvard, Vancouver, ISO, and other styles

18

Ho, Johnny C. "(Invited) Design of Perovskites for High-Performance Electronics and Optoelectronics." ECS Meeting Abstracts MA2023-01, no. 14 (2023): 1335. http://dx.doi.org/10.1149/ma2023-01141335mtgabs.

Full text

Abstract:

The success of lead halide perovskites as active materials in optoelectronic technologies is often associated with the unique properties of their optical excitations. Specifically, the photo-generated excitons in perovskites are responsible for the large absorption coefficients close to their band gap, reaching as high as 105 cm-1. Due to the advent of nanotechnology, perovskite materials can be readily fabricated into nanoscale configurations with different dimensionalities, and more importantly, the corresponding excitonic effects could be further enhanced. On the other hand, at length scale

APA, Harvard, Vancouver, ISO, and other styles

19

Cretu, Bogdan, Abderrahim Tahiat, Anabela Veloso, and Eddy Simoen. "(Invited) In-Depth Understanding of the Key Contributors to the Total Flicker Noise in Advanced Logic Devices." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1521. http://dx.doi.org/10.1149/ma2023-02301521mtgabs.

Full text

Abstract:

The aim of this work is to perform an in-depth analysis in order to identify the key contributors to the total flicker noise in advanced MOSFET technologies, e.g. UTBOX, FinFET or Gate-all-around (GAA) nanowire or nanosheet FET devices. In this abstract, as an example, we will focus on p-type gate all around silicon vertical nanowire devices fabricated at imec. The transistors have a fixed gate length (LG) of 50 nm and 1200 nanowires in parallel (N), each nanowire (NW) having a diameter (WNW) of 20 nm. The total width (W) of the device is calculated as . The gate stack corresponds to an equiva

APA, Harvard, Vancouver, ISO, and other styles

20

Shin, SangHoon, Muhammad Masuduzzaman, and Muhammad Ashraful Alam. "Characterizing self-heating dynamics using cyclostationary measurements." Applied Physics Letters 126, no. 8 (2025). https://doi.org/10.1063/5.0222652.

Full text

Abstract:

Self-heating in surround gate (e.g., nanosheet, nanowire, and FinFET) transistors degrades their on-current performance and reduces their lifetime. If a transistor heats/cools with time constants much shorter than the inverse of the operating frequency, predictable, frequency-independent performance is expected; if not, the operating frequency must be optimized for the highest performance. Typically, time constants are measured by expensive, ultra-fast instruments with high temporal resolution. Instead, here, we demonstrate an alternate, inexpensive, cyclostationary measurement technique to ch

APA, Harvard, Vancouver, ISO, and other styles

21

Peng, Wang, Guanqiao Sang, kun Yang, et al. "Improved Subthreshold Characteristics of Epi-Silicon FinFET via Fin Surface Passivation Technologies." ECS Journal of Solid State Science and Technology, September 30, 2024. http://dx.doi.org/10.1149/2162-8777/ad8187.

Full text

Abstract:

Abstract As demand for advanced integrated circuits (ICs) continues to grow, fin field-effect transistors (FinFETs) have remained highly influential in the IC market because of their mature fabrication process and powerful driving capabilities. However, the ion bombardment that occurs during the reactive ion etching (RIE) process used to form the fin structure increases the fin's surface roughness and results in a high interfacial state density (Dit), which hinders further improvement in the subthreshold swing (SS) of FinFETs. To overcome this issue, this study proposes two oxidative trimming

APA, Harvard, Vancouver, ISO, and other styles

22

U, Gowthami, Durga Prakash Matta, Supraja Patta, and Vakkalakula Bharath Sreenivasulu. "Design and Temperature Analysis of Tree-shaped Nanosheet FET for Analog and RF Applications." Physica Scripta, December 10, 2024. https://doi.org/10.1088/1402-4896/ad9cf8.

Full text

Abstract:

Abstract An innovative breakthrough that addresses the shortcomings of FinFET is the use of tree-shaped Nanosheet FET. This study examines the temperature dependence of the performance of 12 nm Tree-shaped NSFET on DC and analog/RF properties using a gate stack of high-k HfO2 and SiO2. From 200 K to 350 K, a detailed DC performance analysis was performed, including the transfer characteristics (ID vs VGS), output characteristics (ID vs VDS), subthreshold swing (SS), and ION/IOFF ratio. Additionally, we examined how temperature influence power consumption, dynamic power, and the ON-OFF performa

APA, Harvard, Vancouver, ISO, and other styles

23

Zeumault, Andre, Jose E. Mendez, and John Brewer. "Innovations in thin‐film electronics for the new generation of displays." Journal of the Society for Information Display, March 25, 2024. http://dx.doi.org/10.1002/jsid.1274.

Full text

Abstract:

AbstractToday's display industry faces transistor‐level challenges similar to those of complementary metal‐oxide semiconductor (CMOS) metal‐oxide semiconductor field‐effect transistors (MOSFETs) in the mid‐1990s. Learnings from MOSFETs inform the display industry's response to the limitations of silicon‐based thin‐film transistors (TFTs). Improvements sustaining Moore's Law drove the need to rethink MOSFET materials and structures. The display industry needs fundamental innovation at the device level. New thin‐film devices enable an inflection point in the use of displays, just as fin field‐ef

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!