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Journal articles on the topic 'FIR digital filters'
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Pushpalatha, P., and K. Babulu. "Design and implementation of systolic architecture based FIR filter." i-manager's Journal on Digital Signal Processing 10, no. 1 (2022): 17. http://dx.doi.org/10.26634/jdp.10.1.18852.
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In signal processing, a filter is a device or process that removes some unwanted components or features from a signal. Digital filters are mainly divided into Infinite Impulse Response (IIR) filters and Finite Impulse Response (FIR) filters. FIR filters are mostly used in applications like image processing, communications, Digital Signal Processing (DSP) etc. One of the most used filters for designing of VLSI circuits is FIR filter. Systolic architecture is a Processing Element (PE) network that generates and passes data rhythmically through the system. The concept of systolic architecture can map high-level computing into hardware structures. FIR filter with systolic architectures provide better examples for efficient VLSI and FPGA implementations of many digital signal processing applications because of their modularity and regularity features.
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Mewada, Hiren K., and Jitendra Chaudhari. "Low computation digital down converter using polyphase IIR filter." Circuit World 45, no. 3 (2019): 169–78. http://dx.doi.org/10.1108/cw-02-2019-0015.
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Purpose The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter. Design/methodology/approach Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC. Findings The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption. Originality/value The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.
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Stamenkovic, Negovan. "Digital FIR filter architecture based on the residue number system." Facta universitatis - series: Electronics and Energetics 22, no. 1 (2009): 125–40. http://dx.doi.org/10.2298/fuee0901125s.
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In this paper, architecture of residue number system used in FIR filters, is presented. For many years residue number coding has been recognized as a system which provides capability for implementation of a high speed addition and multiplication. These advantages of residue number system coding for the high speed FIR filters design results from the fact that an digital FIR filter requires only addition and multiplication. The proposed FIR filter architecture is performed as series of modulo multiplication and accumulation across each modulo. A numerical example illustrates the principles of FIR filtering of an 32 order low pass filter. This architecture is compared with FIR filters direct synthesis. .
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Gurpadam, Singh, and R. Prakash Neelam. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1874–81. https://doi.org/10.11591/ijece.v7i4.pp1874-1881.
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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.
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Heena, K. P. "A Review of High Throughput FIR Filter Design." International Journal for Research in Applied Science and Engineering Technology 12, no. 7 (2024): 1180–90. http://dx.doi.org/10.22214/ijraset.2024.63734.
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Abstract: Advancements in Finite Impulse Response (FIR) filter design have significantly propelled the field of Digital Signal Processing (DSP), addressing the increasing need for high-performance and efficient digital filters. FIR filters are renowned for their stability, linear phase response, and computational efficiency, making them indispensable in applications such as image filtering and frequency modulation. Their inherent advantages, including the ability to leverage Fast Fourier Transformation (FFT) techniques and minimal finite precision arithmetic errors, often make them preferable over Infinite Impulse Response (IIR) filters. Recent research efforts have focused on algorithmic and hardware modifications to optimize FIR filter architectures, employing techniques such as retiming, pipelining, and parallel processing. This paper explores various design techniques and architectures aimed at optimizing FIR filter performance. Additionally, the role of high-speed adder structures, like carry-lookahead adders, is examined for their impact on enhancing digital filter efficiency and the critical role of continuous exploration and optimization in FIR filter design to advance DSP. By addressing the demands of modern technology, these innovations foster the development of high-performance, efficient digital filters, essential for diverse applications and the ongoing progression of digital signal processing.
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Singh, Gurpadam, and Neelam R. Prakash. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1874. http://dx.doi.org/10.11591/ijece.v7i4.pp1874-1881.
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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.
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Saber, Mohamed, Mohamed E. Ghoneim, and Sunil Kumar. "Survey on Design of Digital FIR Filters using Optimization Models." Journal of Artificial Intelligence and Metaheuristics 2, no. 1 (2022): 16–26. http://dx.doi.org/10.54216/jaim.020102.
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As the discipline of Digital Signal Processing develops, digital filters play an increasingly vital role in modern technology (DSP). The FIR filter, which stands for finite impulse response, is the most common type of filter. As a result of its versatility, FIR filters find widespread application in many fields, including image filtering, frequency modulation, precision arithmetic, and many more. For this reason, digital FIR filters are designed using various optimization techniques. Using various optimization strategies yields the best results when optimizing for different filter coefficients (concerning control parameters, dependence, premature convergence, etc.). They're advantageous due to several factors, including their straightforward implementation, low error function, high-quality searching ability, and rapid convergence. In this paper, we have covered the topic of designing efficient digital filters for signal, image, and video processing using various optimization techniques.
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Shaik, Samdhani, and P. Balanagu. "Functional Verification Architecture Implementation for Power Optimized FIR Filter." International Journal of Engineering & Technology 7, no. 2.20 (2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.
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Digital-filters are having universal for audio applications. So that, great digital-filter execution ought to be taken as an imperative for outline of audio system Applications. The utilization of accuracy with limited in Digital filters for speaking to signals which likewise contrast from that of simple filters as computerized filters utilizing a limited exactness number juggling for registering the filter reaction. Here, FIR-filter has been actualized in Xilinx ISE utilizing VERILOG dialect. VERILOG coding for FIR-filter has been actualized here too waveforms are additionally seen in the reproduction.Viper comprises of less weight as contrasted and multipliers as far as silicon territory and this plays a profitable in FIR structure. This paper has picked multipliers as stall and Wallace and the taken the adders as convey spare and convey skip. In this paper it needs to build up a RTL in the purpose of structures and check the usefulness of structures contrasted and playing out the union utilizing Xilinx synthesizer. The outcomes were thought about regarding region (LUT'S), power, deferral and memory for different fir structures.
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Parameshappa, G., and D. Jayadevapp. "Efficient uniform digital filter bank with linear phase and FRM technique for hearing aids." International Journal of Engineering & Technology 7, no. 1.9 (2018): 69. http://dx.doi.org/10.14419/ijet.v7i1.9.9738.
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This paper attempts to present an uniform digital filter bank based on linear phase FIR and IIR filters applied for Frequency Response Masking (FRM) technique in hearing aid applications.In the proposed filter bank, nine uniformly spaced sub-bands are formed with the help of half band filters and masking filters. These nine channel FIR filter bank is realized using an interpolated half band linear phase FIR filter and an appropriate number of masking FIR filters. The nine channel IIR filter bank is realized using an interpolated half band approximately linear phase IIR filter and an appropriate number of masking filters. The proposed approximately linear phase IIR half band filter bank is compared with filter bank based on linear phase FIR half band filters in terms of area, power, memory and number of gates needed for implementation. The experiment was carried on various hearing loss cases and the results obtained from these tests proves that, the proposed filter bank achieved the required matching between audiograms and magnitude response of the filter bank at very reasonable range with less computational complexity.
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Neelam, Kumari *1 Priyanka Jaglan 2. "DESIGN OF FIR FILTER USING PSO: A REVIEW." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 9 (2017): 283–86. https://doi.org/10.5281/zenodo.891698.
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Digital filters are devices which allow some frequencies to pass without being altered while completely blocking others. Mainly two types of digital filters are available: FIR (finite impulse response) and IIR (infinite impulse response). FIR filters are used in wide variety of applications due to their linear phase response and stability. Filter designing involves use of traditional non-optimization techniques that provides suboptimal results. In order to further enhance the efficiency of designed filter, a number of optimization techniques have been proposed. Particle Swarm Optimization (PSO) is one of such optimization algorithm. This paper presents a review of FIR filter designing using PSO.
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Wang, Zixuan. "Different Methods of Linear Phase IIR Filer Realization." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 167–71. http://dx.doi.org/10.54097/hset.v27i.3739.
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Signal processing has become one of the most popular research topics. Researchers have designed a variety of digital filters to exclude unwanted random noises during the transmission or extract part of the signal in the desired range. There is a prevalent trend for digital filters to replace analog ones since they do not require hardwires. All the performances are operated on a single processor and are free from the effect of external factors. Finite impulse response (FIR) and infinite impulse response (IIR) filters in digital filters respectively provide infinite and finite impulse responses. In the application, it is preferred to have a linear phase digital filter, and FIR filters are naturally linear. However, FIR filters have higher orders and group delay than IIR filters, so researchers found various ways to implement linear phase IIR filters for improvement. This paper introduces and compares Powell and Chau Linear Phase IIR Filter, Kwan Linear Phase IIR Filter, and Xiao, Oliver, and Agathoklis Linear Phase IIR Filter.
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Wang, Wei. "Implemention of FIR Filter Based on DSP." Applied Mechanics and Materials 214 (November 2012): 717–20. http://dx.doi.org/10.4028/www.scientific.net/amm.214.717.
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DSP chip is especially fit for digital signal processing. Its main application is realizing all kinds of digital signal processing arithmetic such as clove hitch correlation, all kinds of transforms etc. Realizing digital filters with DSP is an important application. The paper discusses the filter’s software realization based on TMS320C5410 and finished the hardware systems of noise-restraining.The main works accomplished are as following: realization of FIR filter with window function, and realization on TMS320C5410 chip, the result of experiment to make clear.
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K S, Bindu, Chidananda Murthy M V, M. N. Eshwarappa, and Gaurav Dutta Saxena. "Designing FIR Filter using Distributed Arithmetic." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (2023): 983–87. http://dx.doi.org/10.22214/ijraset.2023.54782.
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Abstract: Distributed arithmetic technique is employed in this paper to develop the FIR filter. To eliminate undesired signal and noise, FIR filters are frequently employed as digital filters in digital signal processing. This method also calls for shift registers and an accumulator and stores the FIR filter coefficients in a look-up table (LUT).By using this method, shift and accumulate can take the place of the multipliers in the FIR filter. The size of the LUT can be reduced for larger filter coefficients by dividing it into any number of LUTs, which are made up of taps that are FIR filter coefficients. FIR filter is created in MATLAB using the DA technique, and manual computation yields the same result
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NERURKAR, SHAILESH B., and KHALID H. ABED. "LOW POWER DIGITAL DECIMATION FILTER FOR RF WIRELESS COMMUNICATIONS." Journal of Circuits, Systems and Computers 17, no. 02 (2008): 239–51. http://dx.doi.org/10.1142/s0218126608004241.
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In this paper, we present a unique low power decimation filter architecture for RF wireless applications. To implement the low power decimation filter, we considered low power design techniques such as multi-rate, multi-stage signal processing, proper selection of decimation factor, one multiplier realization of 1/3-band filters, and poly-phase 1/2-band filters. We have designed three conventional decimation filter architectures using a single-stage FIR filter, a three-stage FIR filter, and a three-stage half-band FIR filter. Compared to the 55-tap comb-FIR filter architecture, the proposed decimation filter has only 13 taps, and requires 76% less hardware and consumes 64% less power.
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Bukke, Balaji Naik, Kamsali Manjunathachari, and Srinivas Sabbavarapu. "Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans." Engineering, Technology & Applied Science Research 13, no. 6 (2023): 12151–57. http://dx.doi.org/10.48084/etasr.6133.
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In the modern era of signal processing, digital filters play an important role in real-time applications such as communication, consumer electronics, digital signal processing, audio, etc. In digital filter design, Finite Impulse Response (FIR) filters are highly preferable due to their linear phase and inherent stability. These filters benefit from being time-invariant and simple to implement with minimal computational requirements. Therefore, the hardware security of FIR filters is essential for good performance and reliable results. On the other hand, there is the possibility of hardware threats, such as tampering, reverse engineering, hardware Trojans, etc., as the design of an FIR filter involves many stages. Such hardware attacks on FIR filters can cause several problems, including performance degradation, leakage of confidential information, lack of stability, etc. This study presents the design and implementation of a Trojan-aware FIR filter using Physical Unclonable Functions (PUFs). The key feature of PUFs is that they generate a unique and unpredictable response for each given challenge. In the proposed design, PUFs were used to generate the FIR filter coefficients that are unique and unpredictable by attackers/trojans to improve security. The security of FIR with PUF was tested using ML-based challenges, and the results showed approximately 30% more reliability and consistency compared to the FIR without PUFs.
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Krishna, Dr B. Vamsy, Siva Ganeshraju Sarikonda, and Jonnakuti Sharath Chandra. "Design and Implementation Low Pass FIR Digital Filter Using Windowing Techniques." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem43943.
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A filter can need to have a certain frequency response, or a particular reaction to an impulse, step, or ramp, or mimic an analogue system. Digital filters can be categorised into Finite Impulse Response (FIR) filters & Infinite Impulse Response (IIR) filters depending on the system response. The thesis addresses FPGA low pass FIR filter design. Theoretical and experimental findings conducted FIR low pass filter point to the window design approach as very straightforward and user-friendly due to the presence of well-defined equation. Comparison indicated that the Direct-Form structure technique is simpler and performs better than other typical filter structures whereas Kaiser window gives the minimal main-lobe width and a sharp cut-off indicating smaller transition width. Experimental research of coefficient quantisation reveals a link between the frequency response, number of coefficients, and bit count. Key words: Digital Signal Processing (DSP),Finite Impulse Response (FIR) Filter, Low- Pass Filter, Verilog HDL, Windowing Techniques, Hamming Window, Hanning Window.
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Litwin, L. "FIR and IIR digital filters." IEEE Potentials 19, no. 4 (2000): 28–31. http://dx.doi.org/10.1109/45.877863.
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Mismar, M. J., and I. H. Zabalawi. "Complex coefficient fir digital filters." Circuits, Systems, and Signal Processing 13, no. 5 (1994): 591–600. http://dx.doi.org/10.1007/bf02523185.
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Kaplun, Dmitry, Denis Butusov, Valerii Ostrovskii, Alexander Veligosha, and Vyacheslav Gulvanskii. "Optimization of the FIR Filter Structure in Finite Residue Field Algebra." Electronics 7, no. 12 (2018): 372. http://dx.doi.org/10.3390/electronics7120372.
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This paper introduces a method for optimizing non-recursive filtering algorithms. A mathematical model of a non-recursive digital filter is proposed and a performance estimation is given. A method for optimizing the structural implementation of the modular digital filter is described. The essence of the optimization is that by using the property of the residue ring and the properties of the symmetric impulse response of the filter, it is possible to obtain a filter having almost a half the length of the impulse response compared to the traditional modular filter. A difference equation is given by calculating the output sample of modules p1 … pn in the modified modular digital filter. The performance of the modular filters was compared with the performance of positional non-recursive filters implemented on a digital signal processor. An example of the estimation of the hardware costs is shown to be required for implementing a modular digital filter with a modified structure. This paper substantiates the expediency of applying the natural redundancy of finite field algebra codes on the example of the possibility to reduce hardware costs by a factor of two. It is demonstrated that the accuracy of data processing in the modular digital filter is higher than the accuracy achieved with the implementation of filters on digital processors. The accuracy advantage of the proposed approach is shown experimentally by the construction of the frequency response of the non-recursive low-pass filters.
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Chen, Jing, Chang Yin Liu, and Xue Ping Li. "The Design and FPGA Implementation of a Polyphase SRRC FIR Filter in DTMB." Advanced Materials Research 791-793 (September 2013): 2122–26. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.2122.
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Polyphase FIR filters are applied in many practical Digital Signal Processing applications where the sampling rate needs to be changed. This paper focuses on the implementation of polyphase square root raised cosine (SRRC) FIR filter based on Field Programmable Gate Array (FPGA). The filter employs methods like filter's multiphase structure, symmetrical coefficients, I/Q channel multiplexing, pipeline addition and so on to design the SRRC filter. Compared with the traditional method, the designed FIR filter exhibits the advantages of high response speed and low hardware resource s consumption.
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Kadhim, Ola N., Kifah T. Khudhair, Fallah H. Najjar, and Hassan M. Al-Jawahry. "Digital filters windowing for data transmission enhancement in communication channel." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (2021): 1454–68. https://doi.org/10.11591/ijeecs.v24.i3.pp1454-1468.
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In this search, an important methodology has been presented for communicated information rectification utilizing advanced channel windowing approach. The modern data communication technologies are ensured with numerous challenges because of their unpredictability and arrangement. Various digital transmission topologies in 4G can't fulfill the requirements in future arrangements, therefore, alternative multicarrier modulation (MCM) becoming the nominated approaches among all other data transmission techniques. Wherein prototype filter configuration is a fundamental system based on which the synthesis and analysis filters are derived. This paper presents a complete review on the ongoing advances of finite impulse response (FIR) filter plan procedures in MCM based correspondence frameworks. Initially, the essential issues are tried, taking into consideration the presentation of available data signal applicants and the FIR filter design concept. At that point the techniques for FIR filter configuration are summed up in subtleties and are center around the accompanying three group’s recurrence testing strategies, windowing based strategies and advancement-based techniques. At last, the exhibitions of different FIR structure strategies are assessed and measured by power spectral density (PSD) and bit error rate (BER), and variable MCM plots as well as their potential prototype filters are examined.
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Ananta Patnaikuni Mythri, Pondreti Pushpalatha,. "VLSI Implementation of 3-Parallel FIR Filters through Coefficient Symmetry Property and Fast FIR Algorithm." Tuijin Jishu/Journal of Propulsion Technology 44, no. 4 (2023): 966–77. http://dx.doi.org/10.52783/tjjpt.v44.i4.952.
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In multirate digital signal processing systems, polyphase filters are frequently used. The challenges in multirate digital signal processing systems primarily relate to efficiently processing signals at different rates while maintaining high-quality output. These challenges include computational complexity, power consumption, and signal delay. The coefficient symmetry property plays a key role in systematically arranging of filter taps in symmetric manner to improve operating efficiency. With a major focus on using the coefficient symmetry characteristic, this paper addresses the VLSI implementation of traditional Type-1 polyphase FIR filters. Furthermore, this paper incorporated 3-parallel FIR filters especially for sequences with odd lengths in order to take full advantage of the coefficient symmetry characteristic. The Fast FIR Algorithm (FFA) method is used to increase overall efficiency. Furthermore, in order to achieve better performance, a modified FFA technique is introduced to enhance overall performance. The paper thoroughly investigates important VLSI factors, such as power consumption, utilization, and delay, and shows how, by utilizing coefficient symmetry and applying this modified FFA technique, filters that are optimized for both power consumption and area utilization are able to be implemented. The results illustrate a significant reduction in both area and power consumption, particularly for longer filters, attributed to the reduced number of multiplication operations inherent in the fast FIR algorithm approach. Additionally, image processing application using 3x3 FIR filter is executed.
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Li, Jiajie. "Design and hardware implementation of FIR digital filter." Applied and Computational Engineering 72, no. 1 (2024): 288–93. http://dx.doi.org/10.54254/2755-2721/72/20241040.
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This article is about the hardware application of one of the basic filters (FIR filter) often used in digital signal processing. First, it introduces the development process of FIR digital filter and the development of FIR digital filter today, and then introduces FIR digital filter. The part combined with hardware, including the research on the hardware implementation technology of the programmable digital filter based on the emictor, the combination with the memistor and the combination with the programmable logic device FPGA is the second most typical research on the combination of digital signal processing technology and hardware in recent years, which respectively describes its main realisation. The combination of FIR digital filter and different hardware methods also has different advantages, but in general, compared with its separate development, the combination of hardware and it has more advantages.
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Zhang, Weiqiang, and Zihan Wang. "FPGA-Based FIR Filter Design and Simulation." Highlights in Science, Engineering and Technology 131 (March 25, 2025): 50–57. https://doi.org/10.54097/dybxk207.
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This paper proposes an optimized design approach for a Finite Impulse Response (FIR) digital filter, leveraging parallel and pipelined architectures to enhance performance, with simulation results validated in ModelSim. FIR filters are crucial components in digital signal processing (DSP), commonly applied in communication systems, audio processing, and other real-time signal applications. As real-time systems demand high computational speed, the challenge of implementing FIR filters efficiently in hardware, particularly in resource-limited environments, becomes increasingly critical. This study addresses these challenges by incorporating parallel processing to enable simultaneous computation across multiple filter stages, significantly boosting processing speed. Additionally, a pipelined architecture is employed to decompose the filter’s operations into multiple stages, reducing latency and further improving throughput. The proposed design is implemented using Verilog Hardware Description Language (HDL), ensuring flexibility and scalability for various hardware platforms. The performance and functionality of the design are thoroughly verified through simulations in ModelSim, demonstrating that the parallel and pipelined FIR filter achieves an optimal trade-off between processing speed and resource consumption. The results show that the design is not only effective for high-frequency applications but also well-suited for embedded and real-time systems, where both speed and resource efficiency are essential. Future work will focus on exploring additional optimizations for filter architectures to further enhance system performance and expand the design's applicability in dynamic and resource-constrained environments.
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Wen, Hui, and Shu Ming Li. "DSP-Based FIR Filter Design and Circular Buffer Implementation." Advanced Materials Research 403-408 (November 2011): 1755–58. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1755.
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The digital filter technology includes two aspects, which are the filter design process and filter realization. The article expounded the basic structure of FIR filter, with examples on the use Matlab to determine the FIR filter coefficient, analysis of the cycle of the buffer zone algorithm Principle, based on the algorithm, combination of filters designed to achieve the input of mixed-signal FIR digital filter. In the end, the filter is given before and after the input and output signal waveform simulation.
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Rao, Dr B. Rama. "Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (2022): 1506–11. http://dx.doi.org/10.22214/ijraset.2022.44081.
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Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.
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Jain, Ekta H., and Chandu N. Bhoyar. "Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result." Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395) 2, no. 4 (2015): 10–17. http://dx.doi.org/10.53555/nneee.v2i4.204.
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Recent years there has been a increasing trend to implement digital signal processing functions in Field ProgrammableGate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functionssuch as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present amethod for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) andDistributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements areused. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter dueto its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performanceof the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.
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DINIZ, PAULO S. R., and SERGIO L. NETTO. "ON WLS-CHEBYSHEV FIR DIGITAL FILTERS." Journal of Circuits, Systems and Computers 09, no. 03n04 (1999): 155–68. http://dx.doi.org/10.1142/s0218126699000141.
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A new numerical approach for designing FIR digital filters is proposed. The method is able to compromise maximum stopband attenuation and minimum stopband energy requirements. The approach is based on the weighted-least-squares (WLS) method using, at each iteration, a different weight function, which is made constant within a given frequency interval. In that manner, digital filters with partially equiripple and partially WLS-like stopbands are efficiently obtained. Generality of the method makes it suitable for the design of linear- and arbitrary-phase FIR filters.
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Kocoń, Sławomir, and Jacek Piskorowski. "Digital Finite Impulse Response Notch Filter with Non-Zero Initial Conditions, Based on an Infinite Impulse Response Prototype Filter." Metrology and Measurement Systems 19, no. 4 (2012): 767–76. http://dx.doi.org/10.2478/v10178-012-0068-x.
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Abstract In this paper a concept of finite impulse response (FIR) narrow band-stop (notch) filter with non-zero initial conditions, based on infinite impulse response (IIR) prototype filter, is proposed. The filter described in this paper is used to suppress power line noise from ECG signals. In order to reduce the transient response of the proposed FIR notch filter, optimal initial conditions for the filter have been determined. The algorithm for finding the length of the initial conditions vector is presented. The proposed values of the length of initial conditions vector, for several ECG signals and interfering frequencies, are calculated. The proposed filters are tested using various ECG signals. Computer simulations demonstrate that the proposed FIR filters outperform traditional FIR filters with initial conditions set to zero.
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Jameil, Ahmed K., Yassir A. Ahmed, and Saad Albawi. "Efficient FIR Filter Architecture using FPGA." Recent Advances in Computer Science and Communications 13, no. 1 (2020): 91–98. http://dx.doi.org/10.2174/2213275912666190603115506.
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Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.
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Dutta Roy, S. C. "Design of digital FIR notch filters." IEE Proceedings - Vision, Image, and Signal Processing 141, no. 5 (1994): 334. http://dx.doi.org/10.1049/ip-vis:19941057.
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Jain, Ekta H., and Chandu N. Bhoyar. "Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result." Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395) 2, no. 2 (2015): 10–17. http://dx.doi.org/10.53555/nneee.v2i2.231.
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Recent years there has been a increasing trend to implement digital signal processing functions in Field Programmable Gate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functions such as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present a method for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) and Distributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements are used. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.
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LIAN, YONG. "A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (2003): 643–54. http://dx.doi.org/10.1142/s0218126603001069.
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This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.
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Hao, Zhenyu, Chenyang Liu, and Shaowei Ouyang. "Study on the optimization process and application of FIR digital filter." Applied and Computational Engineering 72, no. 1 (2024): 107–13. http://dx.doi.org/10.54254/2755-2721/72/20241033.
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As one of the components of digital signal processing technology, the FIR digital filter has been widely used in real life and played an increasingly important role due to its advantages of system stability and ease of linear phase. This paper will summarize and analyze the research results of some past scientific research teams on FIR digital filters, and show the optimization process of this technology and the application examples in real life. This paper focuses on the optimization process of noise reduction performance, delay and size, and energy consumption optimization of FIR digital filters. This study summarizes three examples of its applications in medical, audio processing, and radar. In the medical field, the processing of electrocardiogram (ECG) signals, the audio processing fields are the frequency shaping, noise removal, and signal enhancement of audio signals, and the precise filtering and processing of received signals in the radar field. At the end of this paper, the FIR digital filter has an irreplaceable role in all fields in the world and gradually develops in the direction of miniaturization and low power consumption in the future.
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Balaji, M., and N. Padmaja. "High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (December 31, 2022): 549–56. http://dx.doi.org/10.37394/23203.2022.17.60.
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Digital FIR Filters plays a major role in many signal processing applications. Generally, these filters are designed with multipliers and adders to find the filter output. This paper acquaints how to reduce the complexity of higher order FIR filter by using performance optimization techniques like retiming and pipelining. The filter’s throughput, energy efficiency, and latency, as well as the complexity of its technology, all need to be improved. By adopting pipelining technique, the arithmetic processes of addition and multiplication are separated. The break addition procedure is retimed. The architecture of Pipelining and Retiming with m-tap filters and n-bit word lengths were designed. The smallest delay achieved by the proposed distributed arithmetic-based FIR Filter with pipelining was 2.564ns for a 4tap implementation receiving an 8bit input, while the largest delay achieved was 56.04ns for a 64-tap implementation receiving a 32-bit word length. Delays as low as 0.68ns for a 4-tap implementation receiving an 8-bit input and as high as 4.53ns for a 64tap implementation receiving a 32bit word length have been achieved by using the suggested distributed arithmetic-based FIR Filter with retiming approach. Delay has been reduced by 73.2% for 4tap with 8bit input and by 91.9% for 64tap with 32bit word length compared to the pipelining approach.
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Daraghma, Raed S. M. "M-ary phase-shift keying using finite impulse response filter based on window function method." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 451. http://dx.doi.org/10.11591/ijece.v11i1.pp451-457.
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Digital filters are vastly utilized in the area of communication. A perfect digital filter efficiency is significant and hence to design a digital finite impulse response filter (FIR) favorable all the wanted situations is necessary. In this paper, a new proposed FIR digital filter designed, the fineness of the submitted filter is tested in terms of BER and then matched with another window, namely Hamming, Hanning, and Blackman. The design procedure done in the MATLAB software. It is concluded that the Blackman window is the best window to design the FIR digital filter, because it is bit error rate is better than another window.
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Raed, S. M. Daraghma. "M-ary phase-shift keying using finite impulse response filter based on window function method." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 451–57. https://doi.org/10.11591/ijece.v11i1.pp451-457.
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Digital filters are vastly utilized in the area of communication. A perfect digital filter efficiency is significant and hence to design a digital finite impulse response filter (FIR) favorable all the wanted situations is necessary. In this paper, a new proposed FIR digital filter designed, the fineness of the submitted filter is tested in terms of BER and then matched with another window, namely Hamming, Hanning, and Blackman. The design procedure done in the MATLAB software. It is concluded that the Blackman window is the best window to design the FIR digital filter, because it is bit error rate is better than another window.
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RAMÍREZ, JAVIER, UWE MEYER-BÄSE, and ANTONIO GARCÍA. "EFFICIENT RNS-BASED DESIGN OF PROGRAMMABLE FIR FILTERS TARGETING FPL TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 01 (2005): 165–77. http://dx.doi.org/10.1142/s0218126605002131.
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FIR filters are routinely used in the implementation of modern digital signal processing systems. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the residue number system (RNS) implementation of reduced-complexity and high-performance FIR filters, using modern Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields and the Quadratic Residue Number System (QRNS), along with a selection of a small wordwidth modulus set, are the keys for attaining low complexity and high throughput in real and complex FIR filters. RNS–FPL merged FIR filters demonstrated its superiority when compared to 2C (two's complement) filters, being about 65% faster and requiring fewer logic elements for most study cases. Special attention was paid to an efficient implementation of the multi-operand modulo adders. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage reduced area requirements by 10% for a 32-tap FIR filter. On the other hand, an index arithmetic QRNS-based complex FIR filter yielded up to 60% performance improvement over a three-multiplier-per-tap 2C filter, while requiring fewer LEs for filters having more than eight taps. Particularly, a 32-tap filter needed 24% LEs less than the classical design.
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Gupta, Subham, and Mukesh Kumar Ojha. "Real-Time Audio Enchancement: CIC Filter Design for Improved FIR Filter Performance in Digital Signal Processing." International Journal of Microsystems and IoT 2, no. 8 (2024): 1076–83. https://doi.org/10.5281/zenodo.13365586.
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The fusion of cascading integrator-comb (CIC) and finite impulse response (FIR) filters to improve audio signals in real time. The development and implementation of an operational audio enhancement system is the main goal. The CIC filter's intrinsic elegance and low computing complexity are utilized for effective decimation or interpolation. Achieving significant rate variations inside the pass band with a flat response to frequency is the key objective. After that, the FIR filter is carefully included to improve performance even more by offering increased frequency shaping and customization to satisfy particular needs for audio improvement. Choosing the right filter order, coefficients, and decimation and interpolated coefficients for the CIC filter, as well as smoothly combining it alongside the FIR filter in a current processing pipeline, are all part of the design stage. The suggested process entails establishing the needs for the system, creating and executing the two filters, and carrying out exhaustive testing and optimization. By providing a thorough method that strikes a balance between computing efficiency, latency, and<strong> </strong>performance, the work advances the area of immediate fashion sound processing and tackles the difficulties associated with audio improvement in digital systems. The proposed CIC-FIR method achieves a signal-to-noise ratio (SNR) of 12.41 dB, showcasing its performance in maintaining signal fidelity and noise levels. This SNR value serves as a key metric for evaluating the effectiveness of the proposed CIC-FIR approach.
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Kadhim, Ola N., Kifah T. Khudhair, Fallah H. Najjar, and Hassan M. Al-Jawahry. "Digital filters windowing for data transmission enhancement in communication channel." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (2021): 1454. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1454-1468.
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In this search, an important methodology has been presented for communicated information rectification utilizing advanced channel windowing approach. The modern data communication technologies are ensured with numerous challenges because of their unpredictability and arrangement. Various digital transmission topologies in 4G can't fulfill the requirements in future arrangements, therefore, alternative multicarrier modulation (MCM) becoming the nominated approaches among all other data transmission techniques. Wherein prototype filter configuration is a fundamental system based on which the synthesis and analysis filters are derived. This paper presents a complete review on the ongoing advances of finite impulse response (FIR) filter plan procedures in MCM based correspondence frameworks. Initially, the essential issues are tried, taking into consideration the presentation of available data signal applicants and the FIR filter design concept. At that point the techniques for FIR filter configuration are summed up in subtleties and are center around the accompanying three group’s recurrence testing strategies, windowing based strategies and advancement-based techniques. At last, the exhibitions of different FIR structure strategies are assessed and measured by power spectral density (PSD) and bit error rate (BER), and variable MCM plots as well as their potential prototype filters are examined.
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Petrosian, Ruslan, Vladyslav Chukhov, and Arsen Petrosian. "Development of a method for synthesis the FIR filters with a cascade structure based on genetic algorithm." Technology audit and production reserves 4, no. 2(60) (2021): 6–11. http://dx.doi.org/10.15587/2706-5448.2021.237271.
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The object of research is the process of digital signal processing. The subject of research is methods of synthesis of digital filters with a finite impulse response based on a genetic algorithm. Digital filtering is one of the tasks of digital signal processing. FIR filters are always stable and provide a constant group delay. There are various methods for synthesizing digital filters, but they are all aimed at synthesizing filters with a direct structure. One of the most problematic areas of a digital filter with a direct structure in digital processing is the high sensitivity of the filter characteristics to inaccuracies in setting the filter coefficients. Genetic algorithm-based filter synthesis methods use an ideal filter as the approximated filter. This approach has a number of disadvantages: it complicates the search for an optimal solution; computation time increases. The study used random search method, which is the basis of genetic algorithm (used for solving optimization problems); theory of digital filtering in filter analysis; numerical methods for modeling in a Python program. Prepared synthesis method FIR filter with the cascade structure, which is less sensitive to the effect of finite bit width. Computation time was reduced. This is due to the fact that the proposed method searches for the most suitable filter coefficients based on a genetic algorithm and has a number of features, in particular, it is proposed to use a piecewise-linear function as an approximated amplitude-frequency response. This makes it possible to reduce the number of populations of the genetic algorithm when searching for a solution. The synthesis of an FIR filter with a cascade structure based on a genetic algorithm showed that for a 24-order filter it took about 30–40 generations to get the filter parameters close to the optimal values. In comparison with classical methods of filter synthesis, the following advantages are provided: calculations of the coefficients of a filter with a cascade structure directly, the possibility of optimizing coefficients with limited bit depth.
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ALTINTAŞI, Çağrı. "Design of Digital Low Pass FIR Filter Using Hybrid Particle Swarm – Grey Wolf Optimization Algorithm." Erzincan Üniversitesi Fen Bilimleri Enstitüsü Dergisi 15, no. 3 (2022): 838–44. http://dx.doi.org/10.18185/erzifbed.1097138.
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In this study, digital low-pass FIR filter is designed using Hybrid Particle Swarm – Grey Wolf Optimization Algorithm (HPSGWO). The purpose of digital FIR filter design with HPSGWO is to optimized filter coefficients that are closest to the characteristics of the ideal filter. The obtained results are compared with PSO, and GWO which were previously used for FIR filters design in the literature. According to the obtained results, HPSGWO has better filter response and less stop band ripple than other methods.
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Zhang, Ying, Yubin Zhu, Kaining Han, Junchao Wang, and Jianhao Hu. "A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method." Electronics 10, no. 16 (2021): 1937. http://dx.doi.org/10.3390/electronics10161937.
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Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.
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Pondreti, Pushpalatha, and K. Babulu. "Design of Digital FIR Filter with Systolic Architecture using Reversible Logic Gates." Journal of Physics: Conference Series 2335, no. 1 (2022): 012038. http://dx.doi.org/10.1088/1742-6596/2335/1/012038.
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Abstract The design of Digital filters plays a prominent role in the present scenario. The delay and area are the two major components that need to be concentrated on. The delay tap present in FIR filters should be suppressed to inflate the speed of the system. In this paper, the FIR filter design using systolic architecture with associative technique is implemented. This system includes a number of identical elements that are interconnected one after another by programmed manner to get the specified output. Here the proposed systolic FIR is compared with TDA logic block using bisection technique. There will be a greater reduce of critical path using the systolic architecture. To intensify the speed and to truncate the system delay the processing elements such as adders, multipliers and delay elements are designed by reversible logic operations. The proposed filter is better in many aspects such as density of gates, power consumption and delay outputs compared with existing filter. Experimental results are performed using the Xilinx ISE tool.
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Saha, Suman Kumar, R. Kar, D. Mandal, and S. P. Ghoshal. "A Novel Firefly Algorithm for Optimal Linear Phase FIR Filter Design." International Journal of Swarm Intelligence Research 4, no. 2 (2013): 29–48. http://dx.doi.org/10.4018/jsir.2013040102.
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Optimal digital filter design in digital signal processing has thrown a growing influence on communication systems. FIR filter design involves multi-parameter optimization, on which the existing optimization algorithms do not work efficiently. For which different optimization techniques can be utilized to determine the impulse response coefficient of a filter and try to meet the ideal frequency response characteristics. In this paper, FIR low pass, high pass, band pass and band stop filters have been designed using a new meta-heuristic search method, called firefly algorithm. Firefly Algorithm is inspired by the flash pattern and characteristics of fireflies. The performance of the designed filters has been compared with that obtained by real coded genetic algorithm (RGA), standard PSO and differential evolution (DE) optimization techniques. Differential evolution (DE) is already one of the most powerful stochastic real-parameter optimization algorithms in current use. Here the firefly algorithm (FA) technique has proven a significant advantage. For the problem at hand, the simulation of designing FIR filters has been done and the simulation results demonstrate that Firefly algorithm is better than other relevant algorithms, not only in the convergence speed but also in the performance of the designed filter.
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Reddy, V. Vittal. "Implementation of Digital Filter Using Verilog HDL." International Journal for Research in Applied Science and Engineering Technology 12, no. 4 (2024): 3293–302. http://dx.doi.org/10.22214/ijraset.2024.60579.
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Abstract: In the context of Very Large Scale Integration technology, where addition is essential, digital filters are essential elements. The performance of the Finite Impulse Response Filter is highly dependent on the speed of its multiplier unit, making itstand out among the others. In order to improve the effectiveness of the FIR filter, we suggest using a Wallace tree multiplier. This novel method offers improvements over conventional multipliers, with a decrease in latency being one of the main advantages. Significant improvements in latency are obtained by using Xilinx tools and implementing this filter design in Verilog HDL. The Wallace tree multiplier is perfect for FIR filter construction in low-voltage and low-power VLSI applications since it has benefits like higher operating frequency and reduced power consumption. This development might improve the effectiveness and performance of digital filters, especially in settings with limited resources, opening the way for more robust VLSI systems
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Jasim, Ali, Jawad Mahmood, and Ramzy Ali. "Sound Signal Analysis Using FIR Filters for Musical Fountain Operation." Basrah journal for engineering science 16, no. 2 (2016): 21–28. http://dx.doi.org/10.33971/bjes.16.2.3.
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In digital signal processing (DSP), FIR digital filter isvery important device to deal with particular frequencies of acertain signal to be appropriate for some applications such ascommunications, sound equalizers, etc. In this paper, FIRfilters are adapted to decompose the original sound signal intofour signals. Each one is created by one FIR filter and eachfilter represents a narrow band of frequencies. The filteroutput is used to drive a certain variable speed drive (VSD) tocontrol the speed of a water pump and light intensity of acolored lamp. This filter output signal is applied to the analogcontrol voltage terminals of the VSD unit to control thefrequency and magnitude of the voltage supplied to the lampand pump. Thus, the heads of the water jets and the lightintensity is controlled according to the analog control signalswhich are created by the FIR filters (The VSD is used to mapthe filter output into light intensity and water head bycontrolling the supplied voltage of them). The goal of this studyis to design and simulate four sound harmonics bandsproduced by FIR filters to drive four VSDs which aresimulated using V/F ratio constant method for musicalfountain operation.
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Aparna, A., and T. Vigneswaran. "DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (2017): 66. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19564.
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This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications.
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Ruslan, Petrosian, Chukhov Vladyslav, and Petrosian Arsen. "Development of a method for synthesis the FIR filters with a cascade structure based on genetic algorithm." Technology audit and production reserves 4, no. 2(60) (2021): 6–11. https://doi.org/10.15587/2706-5448.2021.237271.
Full textAbstract:
<em>The object of research is the process of digital signal processing. The subject of research is methods of synthesis of digital filters with a finite impulse response based on a genetic algorithm. Digital filtering is one of the tasks of digital signal processing. FIR filters are always stable and provide a constant group delay. There are various methods for synthesizing digital filters, but they are all aimed at synthesizing filters with a direct structure.</em> <em>One of the most problematic areas of a digital filter with a direct structure in digital processing is the high sensitivity of the filter characteristics to inaccuracies in setting the filter coefficients. Genetic algorithm-based filter synthesis methods use an ideal filter as the approximated filter. This approach has a number of disadvantages: it complicates the search for an optimal solution; computation time increases.</em> <em>The study used random search method, which is the basis of genetic algorithm </em>(<em>used for solving optimization problems</em>)<em>; theory of digital filtering in filter analysis; numerical methods for modeling in a Python program.</em> <em>Prepared synthesis method FIR filter with the cascade structure, which is less sensitive to the effect of finite bit width. Computation time was reduced. This is due to the fact that the proposed method searches for the most suitable filter coefficients based on a genetic algorithm and has a number of features, in particular, it is proposed to use a piecewise-linear function as an approximated amplitude-frequency response.</em> <em>This makes it possible to reduce the number of populations of the genetic algorithm when searching for a solution. The synthesis of an FIR filter with a cascade structure based on a genetic algorithm showed that for a 24-order filter it took about 30–40 generations to get the filter parameters close to the optimal values. In comparison with classical methods of filter synthesis, the following advantages are provided: calculations of the coefficients of a filter with a cascade structure directly, the possibility of optimizing coefficients with limited bit depth.</em>
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Chit, N. N., and J. S. Mason. "Complex Chebyshev approximation for FIR digital filters." IEEE Transactions on Signal Processing 39, no. 1 (1991): 49–54. http://dx.doi.org/10.1109/78.80764.
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