Journal articles: 'FIR filter order'

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Singh, Gurpadam, and Neelam R. Prakash. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (August 1, 2017): 1874. http://dx.doi.org/10.11591/ijece.v7i4.pp1874-1881.

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.

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Konopacki, J., and K. Mościńska. "Estimation of filter order for prescribed, reduced group delay FIR filter design." Bulletin of the Polish Academy of Sciences Technical Sciences 63, no. 1 (March 1, 2015): 209–16. http://dx.doi.org/10.1515/bpasts-2015-0024.

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Abstract FIR filters are often applied, as they possess many advantages, including linear-phase response and well elaborated design methods. However, group delay introduced by FIR filters is usually large. The reduction of group delay can be obtained by restriction of the linear phase requirement only to the passband. One of the problems that appear while designing FIR filters with a prescribed value of group delay is the choice of the filter order. In the paper a formula for filter order calculation for the given filter parameters and dedicated for equiripple or quasi-equiripple approximation of the magnitude response has been derived based on experiments. Numerous examples that explain how to use the derived formula have been included.

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Santhanaraj, M., Rishikesh S. S, and Subramanian A. N. Vijai Sooriya Su. "Higher Order Low Pass FIR Filter Design using IPSO Algorithm." International Journal of Trend in Scientific Research and Development Volume-3, Issue-3 (April 30, 2019): 518–20. http://dx.doi.org/10.31142/ijtsrd22899.

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Zhao, He, Liwei Zhang, Jie Liu, Chao Zhang, Jiao Cai, and Lu Shen. "Design of a Low-Order FIR Filter for a High-Frequency Square-Wave Voltage Injection Method of the PMLSM Used in Maglev Train." Electronics 9, no. 5 (April 28, 2020): 729. http://dx.doi.org/10.3390/electronics9050729.

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In position sensorless control based on a high-frequency pulsating voltage injection method, filters are used to complete the extraction of high-frequency response signals for position observation. A finite impulse response (FIR) filter has the advantages of good stability and linear phase. However, the FIR filter designed by using traditional methods has a high order which will cause a large time delay. This paper proposes a low-order FIR filter design method for a high-frequency signal injection method in the permanent magnet linear synchronous motor. Based on the frequency characteristics of the current signal, the requirement that the FIR filter needs to meet were analyzed. According to the amplitude–frequency characteristic of the FIR filter, these requirements were converted into constraint equations. By solving these equations, the coefficient of the FIR filter could be obtained. The simulation and experiment results showed the effectiveness of this low-order FIR filter.

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Stamenkovic, Negovan. "Digital FIR filter architecture based on the residue number system." Facta universitatis - series: Electronics and Energetics 22, no. 1 (2009): 125–40. http://dx.doi.org/10.2298/fuee0901125s.

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In this paper, architecture of residue number system used in FIR filters, is presented. For many years residue number coding has been recognized as a system which provides capability for implementation of a high speed addition and multiplication. These advantages of residue number system coding for the high speed FIR filters design results from the fact that an digital FIR filter requires only addition and multiplication. The proposed FIR filter architecture is performed as series of modulo multiplication and accumulation across each modulo. A numerical example illustrates the principles of FIR filtering of an 32 order low pass filter. This architecture is compared with FIR filters direct synthesis. .

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Meher, Pramod Kumar, and Sang Yoon Park. "Reconfigurable FIR Filter for Dynamic Variation of Filter Order and Filter Coefficients." JSTS:Journal of Semiconductor Technology and Science 16, no. 3 (June 30, 2016): 261–73. http://dx.doi.org/10.5573/jsts.2016.16.3.261.

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Ahfir, Maamar, Izzet Kale, and Daoud Berkani. "An Alternative Approach to the Balanced Model Truncation Algorithm for Acoustic Minimum-Phase Inverse Filters Order Reduction." ISRN Signal Processing 2011 (April 13, 2011): 1–6. http://dx.doi.org/10.5402/2011/971051.

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We propose an alternative approach to the Balanced Model Truncation method (standard method). This approach reduces substantially the order of minimum-phase inverse filters for equalizing room acoustics. This method is based on a property of the filter z transform function, which modifies the corresponding FIR coefficients before the application of the standard technique to the modified FIR coefficients filter version. In the standard technique, the Hankel singular values plot is the chief guide for a user for the selection of a reduced filter order. Results for minimum-phase inverse filter corresponding to partial equalization of measured acoustic impulse response show the superiority of the proposed method over the standard technique, in terms of reduced filters order selection.

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Kocoń, Sławomir, and Jacek Piskorowski. "Digital Finite Impulse Response Notch Filter with Non-Zero Initial Conditions, Based on an Infinite Impulse Response Prototype Filter." Metrology and Measurement Systems 19, no. 4 (December 1, 2012): 767–76. http://dx.doi.org/10.2478/v10178-012-0068-x.

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Abstract In this paper a concept of finite impulse response (FIR) narrow band-stop (notch) filter with non-zero initial conditions, based on infinite impulse response (IIR) prototype filter, is proposed. The filter described in this paper is used to suppress power line noise from ECG signals. In order to reduce the transient response of the proposed FIR notch filter, optimal initial conditions for the filter have been determined. The algorithm for finding the length of the initial conditions vector is presented. The proposed values of the length of initial conditions vector, for several ECG signals and interfering frequencies, are calculated. The proposed filters are tested using various ECG signals. Computer simulations demonstrate that the proposed FIR filters outperform traditional FIR filters with initial conditions set to zero.

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Soibam*, Daimond Singh, and Manoj Kumar. "Design and Implementation of Third Order Low Pass Digital FIR Filter using Pipelining Retiming Technique." International Journal of Engineering and Advanced Technology 10, no. 4 (April 30, 2021): 178–84. http://dx.doi.org/10.35940/ijeat.d2446.0410421.

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: This paper presents design and implementation of 3rd order low pass digital FIR filter using pipelining retiming technique. Aim of this paper is to apply pipelining retiming technique on low pass digital FIR filter and compare with the existing second order retimed FIR filter and third order broadcast, non-broadcast low pass FIR filter. MATLAB FDA tool is used to calculate digital FIR filter coefficients. Hamming and Kaiser window methods are used to find out the coefficients of the FIR filter. Broadcast and non broadcast third order low pass FIR filter architectures are used for pipelining retiming .Cutset and feed forward pipelining retiming techniques are used to retime the third order low pass digital FIR filter. We design our algorithm in VHDL and implemented on Xilinx Vivado xc7a35tcpg261-1. Area (LUT), speed and power are calculated using Xilinx Vivado 2015.2 tool. Synthesis and simulation results are discussed in this paper. Speed and area (LUT) of proposed third order low pass FIR filter is improved in comparison with existing designs.

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Abu Khadra, F., and K. Dimyati†. "First-order PMD compensation using optical FIR filter." Journal of Modern Optics 55, no. 8 (May 10, 2008): 1243–50. http://dx.doi.org/10.1080/09500340701639565.

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Hu, Haijiang, Shaojing Song, and Fengdeng Zhang. "FIR to FIR Model Reduction with Linear Group Delay in Passband by SDP Optimization." Journal of Electrical and Computer Engineering 2020 (February 20, 2020): 1–7. http://dx.doi.org/10.1155/2020/4503706.

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Filter model reduction is an important optimization method in digital signal processing. A method of FIR to FIR model reduction using SDP optimization is proposed in this paper. At first, we use SDP to design an original FIR filter. Then we name a general K-order FIR digital filter H1z−1 with coefficient values equal to the first K + 1 filter coefficient values of H0z−1. Finally, we design a new general K-order FIR digital filter H2z−1 connected in parallel with H1z−1 using SDP optimization. The experiment results show this method has good performance on the magnitude error and the linear phase in passband. Therefore, this method can be used in the field of digital signal processing.

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SARAMÄKI, TAPIO, JUHA YLI-KAAKINEN, and HÅKAN JOHANSSON. "OPTIMIZATION OF FREQUENCY-RESPONSE MASKING BASED FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (October 2003): 563–91. http://dx.doi.org/10.1142/s0218126603001070.

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A very efficient technique to drastically reduce the number of multipliers and adders in implementing linear-phase finite-impulse response (FIR) digital filters in applications demanding a narrow transition band is to use the frequency-response masking (FRM) approach originally introduced by Lim. The arithmetic complexity can be even further reduced using a common filter part for constructing the masking filters originally proposed by Lim and Lian. A drawback in the above-mentioned original FRM synthesis techniques is that the subfilters in the overall implementations are separately designed. In order to further reduce the arithmetic complexity in these two FRM approaches, the following two-step optimization technique is proposed for simultaneously optimizing the subfilters. At the first step, a good suboptimal solution is found by using a simple iterative algorithm. At the second step, this solution is then used as a start-up solution for further optimization being carried out by using an efficient unconstrained nonlinear optimization algorithm. An example taken from the literature illustrates that both the number of multipliers and the number of adders for the resulting optimized filter are less than 80% compared with those of the FRM filter obtained using the original FRM design schemes in the case where the masking filters are separately implemented. If a common filter part is used for realizing the masking filters, then an additional reduction of more than 10% is achieved compared with the optimized design with separately implemented masking filters.

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Wavhal, Monika Dattatraya. "Systolic Architecture for High Speed FIR Filter Using VLSI Technology." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 14, no. 11 (August 1, 2015): 6211–18. http://dx.doi.org/10.24297/ijct.v14i11.1805.

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The tremendous growth of computer and Internet technology wants the data to be processed athigh speed. Low power consumption, high throughput and optimized hardware are the most important design criteriaâ€™s for VLSI implementation. This project gives an efficient design of high speed FIR filters using systolic architecture. In this paper we have implemented 7th,8th,11th order FIR filter with 8 bit normalized input. To obtain efficient results we have selected B1 design from all the designs of systolic arrays.GF (28) multiplier and XOR adder are used for multiplication and addition in filter. Hamming window technique is used to derive the filter coefficients. The coefficients of filter are found out using Matlab. The FIR filter architecture is effectively synthesized and simulated using Xilinx ISE 8.1i in VHDL and Modelsim simulator. Maximum frequency, timing simulation delay and number of slices were used as performance metrics. The results obtained are compared with the existing results achieved for FIR filter, thus our work proves that the objective of high speed has been achieved successfully with the use of minimum number of slices.

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Zhang, Ying, Yubin Zhu, Kaining Han, Junchao Wang, and Jianhao Hu. "A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method." Electronics 10, no. 16 (August 11, 2021): 1937. http://dx.doi.org/10.3390/electronics10161937.

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Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

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Aimin Jiang, Hon Keung Kwan, Yanping Zhu, Xiaofeng Liu, Ning Xu, and Yibin Tang. "Design of Sparse FIR Filters With Joint Optimization of Sparsity and Filter Order." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 1 (January 2015): 195–204. http://dx.doi.org/10.1109/tcsi.2014.2354771.

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Marchon, Niyan, and Gourish Naik. "Linear phase FIR filter to compute fetal heart rate variability." International Journal of Engineering & Technology 7, no. 4.5 (September 22, 2018): 492. http://dx.doi.org/10.14419/ijet.v7i4.5.21141.

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Continuous monitoring of fetal heart rate (FHR) can detect the well-being of the fetus and thus indicates non-reassuring fetal status. In- vasive fetal electrocardiography (FECG) using the fetal scalp electrode applied to the fetus scalp allows accurate detection of fetal QRS (FQRS) complexes, however with a risk of infection to the fetus. We have proposed a non-invasive fetal heart rate (NIFHR) filtering technique employing finite impulse response (FIR) filters. We applied Fast Fourier Transform (FFT) to the Physionet abdominal ECG (aECG) records and derived the fiduciary edges of the spectrum of the FECG. A FIR band pass filter (BPF) is designed which is a com- posite filter consisting of a high pass filter (HPF) followed by a low pass filter (LPF) in that order. The cut off frequencies of these com- posite filters are the fiduciary edges of the fetal electrocardiography spectrum. A FQRS detector to obtain fetal heart rate variability (FHRV) processes the FQRS signal filtered through these composite FIR filters. It is observed that channel 4 from records r01 and r08 obtained 100% results for sensitivity, positive predictive value and accuracy while, the overall accuracy was 92.21%. This design can also be extended to compute maternal heart rate.

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RIZVANDI, N. BABAII, A. NABAVI, and SH HESSABI. "AN ACCURATE FIR APPROXIMATION OF IDEAL FRACTIONAL DELAY FILTER WITH COMPLEX COEFFICIENTS IN HILBERT SPACE." Journal of Circuits, Systems and Computers 14, no. 03 (June 2005): 497–505. http://dx.doi.org/10.1142/s0218126605002386.

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This paper presents a low-order and accurate method for the design of FIR fractional delay (FD) filters with complex coefficients. This method employs least square technique in Hilbert space to approximate the ideal FD transfer function with a FIR filter and to calculate its coefficients. The main advantages of the resulting filter are: very good response at all frequencies compared to other FD filter design methods and a good method to create very small delay. Design examples are presented to illustrate the effectiveness of this new design approach.

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Reja, Mohammad Istiaque, Md Golam Murtuza, and Roki Roy. "Combinations of Different FIR Windows for Removal of Baseline and Power Line Noise from Electrocardiogram." Modern Applied Science 12, no. 9 (August 20, 2018): 119. http://dx.doi.org/10.5539/mas.v12n9p119.

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Electrocardiogram (ECG) is a vital tool used for diagnosing various heart diseases. It is the graphical representation of the electrical activity of the heart. But the electrocardiographic signals are often corrupted by noise from diverse sources. The most significant noises that corrupt ECG signal are power line interference and baseline wanders. It is necessary to reduce the amount of these disturbances from ECG signal for proper identification and interpretation of heart condition. This paper investigates the performance of the different 'Band stop filter-High Pass filter' combinations of window based FIR filter for removing the baseline wander and power line noise present in electrocardiogram. The ECG signal is generated and then noises are added to the ECG signal using MATLAB® where filters are designed and analyzed using Filter Design and Analysis Tool (FDATool). 49 different 'Band stop filter-High Pass filter' combinations are made using seven different FIR windows namely Bartlett, Chebyshev, Hamming, Hann, Kaiser, Rectangular, Triangular. For filter order of 350 and 450, the performance of different window combinations are compared and analyzed in terms of Signal power, Peak-to-peak value, Signal to Noise Ratio (SNR) and Mean Square Error (MSE) of the filtered output. A further analysis of the waveforms of the filtered output show that the combinations where both the bandstop and highpass filters are either Kaiser or Rectangular window i.e. Kaiser-Kaiser, Kaiser-Rectangular, Rectangular-Kaiser and Rectangular-Rectangular windows give the best performance in reducing both the baseline noise and high frequency power line noise. It is also found that the reduction of baseline noise is better if 450 filter order is used instead of 350 order in the above mentioned best four combinations, although the amount of delay for 450 order is slightly higher.

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Shen, Zhao Jun, and Sen Xu. "Optimization Algorithm Analysis for FIR Filter by FPGA." Applied Mechanics and Materials 373-375 (August 2013): 1269–73. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.1269.

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The article introduces essential method to realize the high accuracy and velocity FIR filter by FPGA. Proposes the FIR filter optimization scheme design of serial shifts based on FPGA. Avoided the shortcoming of the traditional parallel algorithm module taking the massive hardware resources . And give 11-order and 8-bits low pass filter design as the specific research object. Realized the partial functions which the traditional numeral FIR filter cannot.May adjusts the filter exponent number conveniently and suits different application.

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Fursov, V. A. "Constructing a quadratic-exponential FIR-filter with an extended frequency response midrange." Computer Optics 42, no. 2 (July 24, 2018): 297–305. http://dx.doi.org/10.18287/2412-6179-2018-42-2-297-305.

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This article is concerned with synthesizing filter with finite impulse response (FIR-filters) employed to correct radially symmetric distortions such as defocusing. We propose a new parametric class of finite impulse response filters (FIR-filters) based on a model of the one-dimensional radially symmetric frequency response. In the proposed method, the one-dimensional frequency response is composed of quadratic and exponential functions. The two-dimensional impulse response of the filter is constructed by sampling one-dimensional impulse responses for all directions. The development consists in introducing an extended mid-frequency region of the frequency response, thus increasing the contribution of the frequencies to image correction. Examples are given in order to illustrate the possibility of the high-quality distortion correction. In particular, it is shown that the proposed method provides the restoration quality higher than that obtained when using an optimal Wiener filter (taken from OpenCV).

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Comon, P., and D. T. Pham. "Estimating the order of a FIR filter for noise cancellation." IEEE Transactions on Information Theory 36, no. 2 (March 1990): 429–34. http://dx.doi.org/10.1109/18.52496.

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Johansson, Hakan. "On FIR Filter Approximation of Fractional-Order Differentiators and Integrators." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 3, no. 3 (September 2013): 404–15. http://dx.doi.org/10.1109/jetcas.2013.2273853.

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Chung, Daewon, Woon Cho, Inyeob Jeong, and Joonhyeon Jeon. "Design of Cut Off-Frequency Fixing Filters by Error Compensation of MAXFLAT FIR Filters." Electronics 10, no. 5 (February 26, 2021): 553. http://dx.doi.org/10.3390/electronics10050553.

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Maximally-flat (MAXFLAT) finite impulse response (FIR) filters often face a problem of the cutoff-frequency error due to approximation of the desired frequency response by some closed-form solution. So far, there have been plenty of efforts to design such a filter with an arbitrarily specified cut off-frequency, but this filter type requires extensive computation and is not MAXFLAT anymore. Thus, a computationally efficient and effective design is needed for highly accurate filters with desired frequency characteristics. This paper describes a new method for designing cutoff-frequency-fixing FIR filters through the cutoff-frequency error compensation of MAXFLAT FIR filters. The proposed method provides a closed-form Chebyshev polynomial containing a cutoff-error compensation function, which can characterize the “cutoff-error-free” filters in terms of the degree of flatness for a given order of filter and cut off-frequency. This method also allows a computationally efficient and accurate formula to directly determine the degree of flatness, so that this filter type has a flat magnitude characteristic both in the passband and the stopband. The remarkable effectiveness of the proposed method in design efficiency and accuracy is clearly demonstrated through various examples, indicating that the cutoff-fixing filters exhibit amplitude distortion error of less than 10−14 and no cut off-frequency error. This new approach is shown to provide significant advantages over the previous works in design flexibility and accuracy.

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Jan Kikkert, Cornelis. "A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation." Electronics 8, no. 12 (December 11, 2019): 1523. http://dx.doi.org/10.3390/electronics8121523.

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Phasor measurement units (PMU) are increasingly used in electrical power transmission networks, to maintain stability and protect the network. PMUs accurately measure voltage, phase, frequency, and rate of change of frequency (ROCOF). For reliability, it is desirable to implement a PMU using an FPGA. This paper describes a novel algorithm, suited to implementation in an FPGA and based on a simple PMU block diagram. A description of its realization using low hardware complexity infinite impulse response (IIR) filters is given. The IEC/IEEE standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power systems, describes “reference” Finite Impulse Response (FIR) filters for implementing PMU hardware. At the 10 kHz sampling frequency used for our implementation, each “reference” FIR filter requires 100 multipliers, while an 8th order IIR filter only requires 12 multipliers. This paper compares the performance of different order IIR filter-based PMUs with the performance of the same PMU algorithm using the IEC/IEEE FIR reference filter. The IIR-based PMU easily satisfies all the requirements of IEC/IEEE standard and has a much better out of band signal rejection performance than a FIR-based PMU. Steady state errors for a rated voltage ± 10% and a rated frequency ± 5 Hz are < 0.000001% for total vector error (TVE) and < 1 µHz for frequency, with a latency of two mains cycles.

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Kumar, Susheel, Munish Verma, Vijay K. Lamba, Avinash Kumar, and Sandeep Kumar. "COMPARATIVE ANALYSIS OF EXPONENTIAL WINDOW FUNCTION FOR DESIGNING OF FIR FILTERS." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 3, no. 2 (October 30, 2012): 329–34. http://dx.doi.org/10.24297/ijct.v3i2c.2895.

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Filters are very commonly found in everyday life and include examples such as water filters for water purification, mosquito nets that filter out bugs, bouncers at bars filtering the incoming guests according to age (and other criteria), and air filters found in air conditioners that we are sometimes a bit too lazy to change/clean periodically. Filters have two uses: signal separation and signal restoration. Signal separation is needed when a signal has been contaminated with interference, noise, or other signals. For example, imagine a device for measuring the electrical activity of a baby's heart (EKG) while still in the womb. The raw signal will likely be corrupted by the breathing and heartbeat of the mother. A filter might be used to separate these signals so that they can be individually analyzed. Signal restoration is used when a signal has been distorted in some way. For example, an audio recording made with poor equipment may be filtered to better represent the sound as it actually occurred [1, 2]. The main goal of this work is to study the exponential Â window function and analyze a digital low pass FIR filter using the same in MATLAB. Properties of window functions is studied and frequeny domain responses ofÂ window functions is obtained. Then FIR filter is designed using widow design method and its characteristics have also been studied in frequency domain. The performace comparison between LPFs designed using other well known windows like Kaiser, Exponential, Cosh and modified kaiser window is done and it has been intuitively shown that for a given order and transition width, the filter designed using Exponential window provides the worse minimum stop band attenuation but better far end attenuation than filter designed by well known Kaiser Window.

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Petrosian, Ruslan, Vladyslav Chukhov, and Arsen Petrosian. "Development of a method for synthesis the FIR filters with a cascade structure based on genetic algorithm." Technology audit and production reserves 4, no. 2(60) (July 31, 2021): 6–11. http://dx.doi.org/10.15587/2706-5448.2021.237271.

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The object of research is the process of digital signal processing. The subject of research is methods of synthesis of digital filters with a finite impulse response based on a genetic algorithm. Digital filtering is one of the tasks of digital signal processing. FIR filters are always stable and provide a constant group delay. There are various methods for synthesizing digital filters, but they are all aimed at synthesizing filters with a direct structure. One of the most problematic areas of a digital filter with a direct structure in digital processing is the high sensitivity of the filter characteristics to inaccuracies in setting the filter coefficients. Genetic algorithm-based filter synthesis methods use an ideal filter as the approximated filter. This approach has a number of disadvantages: it complicates the search for an optimal solution; computation time increases. The study used random search method, which is the basis of genetic algorithm (used for solving optimization problems); theory of digital filtering in filter analysis; numerical methods for modeling in a Python program. Prepared synthesis method FIR filter with the cascade structure, which is less sensitive to the effect of finite bit width. Computation time was reduced. This is due to the fact that the proposed method searches for the most suitable filter coefficients based on a genetic algorithm and has a number of features, in particular, it is proposed to use a piecewise-linear function as an approximated amplitude-frequency response. This makes it possible to reduce the number of populations of the genetic algorithm when searching for a solution. The synthesis of an FIR filter with a cascade structure based on a genetic algorithm showed that for a 24-order filter it took about 30–40 generations to get the filter parameters close to the optimal values. In comparison with classical methods of filter synthesis, the following advantages are provided: calculations of the coefficients of a filter with a cascade structure directly, the possibility of optimizing coefficients with limited bit depth.

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Grande Naga Jyothi, Anusha Gorantla, and Thirumalesu Kudithi. "ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter." International Journal of e-Collaboration 16, no. 4 (October 2020): 59–71. http://dx.doi.org/10.4018/ijec.2020100105.

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Power consumption plays a crucial role in the design of portable wireless communication devices, as it has a direct influence on the battery weight and volume required for operation. This article presents a novel design for a linear LMS equalizer for the optimization of filter order. The article describes the use of a variable length algorithm for dynamically updating the tap-length of the LMS adaptive filter to optimize the performance and for reducing the power in the adaptive filter core. An algorithm is applied to reduce and adjust the order of the filter in linear equalizer according to the channel conditions. The proposed design is implemented in the synopsis TSMC 65nm technology. The results from using the algorithm uses 28% less power when compared with the conventional 64-tap fixed length adaptive filter design. It has also been shown that the low-complexity of the additional circuitry needed for the variable length adaptive filter presents minimal overhead for this architecture.

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Xu, Guo Sheng. "Design of Reconfigurable FIR Filter System Based on FPGA." Advanced Materials Research 433-440 (January 2012): 4669–74. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4669.

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In order to improve the real-time and flexible of FIR digital filter, a reconfigurable FIR filter system based on FPGA is designed. According to the filter specialties, the filter coefficients are calculated by the computer. And the configured coefficients of the multistage FIR filter are downloaded to the chip. The filtering computing is completed by the FPGA. The filtered data is transmitted to the computer through the USB2.0 interface for further processing, such as displaying, analyzing and storing. The states conversion between coefficients configuring mode and filtering mode is finished by FSM (Finite State Machine), which ensures the system to work orderly. The experimental results demonstrated that the coefficients configuring of the system is easy, which can adjust the filter coefficients flexibly according to the actual demand, and the filter is effective，that it can effectively filter out the noise signals.

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LI, Fei, Yi-cheng ZENG, Chao-qun AN, and Yun-xia YU. "High-order FIR filter design on FPGA using MA distributed algorithm." Journal of Computer Applications 31, no. 2 (April 7, 2011): 533–36. http://dx.doi.org/10.3724/sp.j.1087.2011.00533.

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Morales-Velazquez, Luis, Rene de Jesus Romero-Troncoso, Roque Alfredo Osornio-Rios, and Eduardo Cabal-Yepez. "Sensorless jerk monitoring using an adaptive antisymmetric high-order FIR filter." Mechanical Systems and Signal Processing 23, no. 7 (October 2009): 2383–94. http://dx.doi.org/10.1016/j.ymssp.2009.02.012.

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Punchalard, R., J. Koseeyaporn, and P. Wardkein. "Indirect frequency estimation based on second-order adaptive FIR notch filter." Signal Processing 89, no. 7 (July 2009): 1428–35. http://dx.doi.org/10.1016/j.sigpro.2009.01.016.

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DUNG, L. R., and H. C. YANG. "A Parallel-In Folding Technique for High-Order FIR Filter Implementation." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 12 (December 1, 2006): 3659–65. http://dx.doi.org/10.1093/ietfec/e89-a.12.3659.

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Yuan, Jun, Quan Yuan Feng, and Dan Wang. "Design of High-Precision FIR Filter Based on Verilog HDL." Advanced Materials Research 433-440 (January 2012): 5198–202. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5198.

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This paper presents an optimized FIR filter implementation by using the method of improving coefficient precision at reasonable cost. The comparable results of traditional fix-point implementation and the optimization method show that the high-precision FIR filter design method is universal and easy to implement. Plus the employment of multi-stage pipelining and parallel structure, FIR filter performs higher operating frequency. Let’s take a 32-order lowpass FIR filter as an example, original coefficients are generated on MATLAB, and translated into optimized coefficients according to the optimization method. The functional simulations verify the effective performance, while the synthesis is carried out to analyze the utilization of resources and maximum frequency.

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Astik, Noopur. "Dynamic Partial Reconfiguration with FIR Filter Application." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 201. http://dx.doi.org/10.11591/ijres.v4.i3.pp201-208.

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Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of <em>Field Programmable Gate Array</em> (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented

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Kale, I. "FIR filter order reduction: balanced model truncation and Hankel-norm optimal approximation." IEE Proceedings - Vision, Image, and Signal Processing 141, no. 3 (1994): 168. http://dx.doi.org/10.1049/ip-vis:19941203.

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Mittal, Anubhuti, Ashutosh Nandi, and Disha Yadav. "Comparative study of 16‐order FIR filter design using different multiplication techniques." IET Circuits, Devices & Systems 11, no. 3 (March 20, 2017): 196–200. http://dx.doi.org/10.1049/iet-cds.2016.0146.

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WANG, WEI, M. N. S. SWAMY, and M. O. AHMAD. "NOVEL DESIGN AND FPGA IMPLEMENTATION OF DA-RNS FIR FILTERS." Journal of Circuits, Systems and Computers 13, no. 06 (December 2004): 1233–49. http://dx.doi.org/10.1142/s0218126604001970.

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Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).

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Economou, D., C. Mavroidis, I. Antoniadis, and C. Lee. "Maximally Robust Input Preconditioning for Residual Vibration Suppression Using Low-Pass FIR Digital Filters." Journal of Dynamic Systems, Measurement, and Control 124, no. 1 (July 27, 2000): 85–97. http://dx.doi.org/10.1115/1.1434272.

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A method for suppressing residual vibrations in flexible systems is presented and experimentally demonstrated. The proposed method is based on the preconditioning of the inputs to the system using low-pass Finite Impulse Response (FIR) digital filters. Provided that the cutoff frequency of FIR filters is selected lower than the lowest expected natural frequency of the system and their stop-band is maximized, we show that these filters can be designed to exhibit maximally robust behavior with respect to changes of the system natural frequencies. To perform the proper design of FIR filters for robust vibration suppression, this paper introduces a series of dimensionless performance indexes and the Delay-Error-Order (DEO) curves that represent graphically the delay time introduced by the filter as a function of the remaining residual vibrations, and the filter order. Several classes of FIR filters such as: a) Parks-McClellan; b) Window-based methods (using Chebyshev window); and c) Constrained Least Squares method, are shown to present maximally robust behavior, almost identical to the theoretically predicted. Parallel, they demonstrate excellent vibration suppression while they introduce the minimum possible delay. Further advantages offered by the proposed method, is that no modeling of the flexible system is required, the method can be used in a variety of systems exhibiting vibrations, it is independent of the guidance function and it is simple to implement in practical applications. The results are experimentally verified on a flexible aluminum beam with a significantly varying mass, attached to the end-effector of a robot manipulator. The beam is rotated, using one joint of the manipulator, from an initial to a final position. It is shown that the preconditioned inputs to the flexible system induce very little amount of residual vibrations compared to the inputs with no preconditioning.

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Jain, Shruti, and Mr Dinesh Kumar Verma. "Comparison of Various Window Functions Used in FIR Filter Designing." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 8, no. 3 (June 30, 2013): 902–7. http://dx.doi.org/10.24297/ijct.v8i3.3401.

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In this study, 2-parameter cosh window is modified to improve its spectral characteristic in terms of the ripple ratio by proposing a new additional parameter. It is observed that an increase in the new parameter results in wider mainlobe width and smaller ripple ratio. By choosing the suitable combinations of the two adjustable parameters for the proposed modified window, the optimum windows that yield the minimum ripple ratio for N=51 and N=101 are .found. Simulation results show that the filters designed by proposed 3-parameter Cosh window provide higher quality in terms of the minimum stop-band attenuation for a fixed order, and yield lower order for a fix minimum stop-band attenuation compared to the filters designed by other windows.

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Prashanth, B. U. V., Mohammed Riyaz Ahmed, and Manjunath R. Kounte. "Design and implementation of DA FIR filter for bio-inspired computing architecture." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (April 1, 2021): 1709. http://dx.doi.org/10.11591/ijece.v11i2.pp1709-1718.

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This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.

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Ren, Shan, Xin Zhao, Jie Jiang, and Dong Jin Zhao. "Design and Realization of FIR Band-Pass Digital Filter Based on MATLAB." Advanced Materials Research 503-504 (April 2012): 228–31. http://dx.doi.org/10.4028/www.scientific.net/amr.503-504.228.

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Digital filter is one of the most important parts of digital signal processing. In practice, digital signal processing often need to limit the signal observation time interval within a certain time, choose only one period of signal that signal data will be truncated, this process is equivalent to plus window function operation to signal. In order to obtain finite unit sample response, need to truncate the infinite unit sample response sequence by window function. This paper proposes the method of using window function to design FIR Band-pass filter based on MATLAB, according to the design basic principle of FIR digital filter. Filtering processing for measured signal showed that filtering effect of the filter achieved the expected results.

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Figuli, Shalina Percy Delicia, and Jürgen Becker. "An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter." Journal of Circuits, Systems and Computers 28, no. 01 (October 15, 2018): 1950015. http://dx.doi.org/10.1142/s0218126619500154.

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The need for efficient Finite Impulse Response (FIR) filters in high-speed applications such as telecommunications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offers many advantages, its convolution nature poises a challenge in parallelization due to data dependency and computational complexity. To resolve this, we propose a novel FPGA-based reconfigurable filter architecture, which processes several data samples in parallel and breaks down data interdependency in a spiral fashion. Experimental results show a throughput of 7.2[Formula: see text]GSPS with an operating frequency of only 450[Formula: see text]MHz for a filter length of 11 with 16 parallel inputs. With parallelization of 4, it is 4.44 times faster than the state-of-the-art solution for a filter length of 16 and a promising 1.04[Formula: see text]GSPS throughput is achieved for a higher order of length 61. Incorporated into a generic Quadrature Amplitude Modulation (QAM) transmitter fitted with Forward Error Correction technique, a maximum throughput of 23[Formula: see text]Gb/s is achieved by the system for processing 16 input samples in parallel. In comparison to the state-of-the-art mixed domain approach, a threefold performance gain, while utilizing comparatively less Look-up Tables (LUTs), registers and DSP48 slices with an average gain factor of 43.3[Formula: see text], 4.7[Formula: see text] and 3.9[Formula: see text], respectively, is accomplished.

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Li, Lin, Jian Hui Wang, and Shuai Ban. "A Design Method for IIR and FIR Digital Notch Filter Used to sEMG." Applied Mechanics and Materials 263-266 (December 2012): 184–87. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.184.

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Surface electromyography (sEMG) signals, a non-invasive bioelectric signal, can be used for the rehabilitation and control of artificial extremities. But this signal is so weak that the electrical voltages ranging from -5 to +5 mv. In order to eliminate the 50Hz noise included in sEMG and hold details of the signal, IIR50HZ notch filter and FIR 50Hz notch filter are design. The compared simulation results show that the application of FIR 50Hz is better than IIR 50Hz in sEMG patter recognition system.

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Wulf, Michael, Gerhard Staude, Andreas Knopp, and Thomas Felderhoff. "Efficient design of FIR filter based low-pass differentiators for biomedical signal processing." Current Directions in Biomedical Engineering 2, no. 1 (September 1, 2016): 215–19. http://dx.doi.org/10.1515/cdbme-2016-0048.

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AbstractThis paper describes an alternative design of linear phase low-pass differentiators with a finite impulse response (type III FIR filter). To reduce the number of necessary filter coefficients, the differentiator’s transfer function is approximated by a Fourier series of a triangle function. Thereby the filter’s transition steepness towards the stopband is intentionally reduced. It can be shown that the proposed design of low-pass differentiators yields to similar results as other published design recommendations, while the filter order can be significantly reduced.

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Avelar, Helder Henrique. "Evaluation of Stuck-at Faults in a FIR Filter Design." U.Porto Journal of Engineering 5, no. 2 (November 29, 2019): 38–45. http://dx.doi.org/10.24840/2183-6493_005.002_0005.

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The development of integrated circuits becomes more complex and gets more susceptible to manufacturing errors as technology nodes get smaller. Along with that, the observability of more complex chips gets reduced, making it harder and more expensive to test. Therefore, the impact of different faults must be observed on the design as early as possible, in order to reduce the time to market and the cost of the fault to the project.Since many designs depend on Digital Signal Processing applications, this project proposes a case study of the implementation of a FIR filter design in Verilog and the analysis and comparison of its response by inserting stuck-at faults in its shift registers via test bench simulation.

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46

Punchalard, R., A. Lorsawatsiri, W. Loetwassana, J. Koseeyaporn, P. Wardkein, and A. Roeksabutr. "Direct frequency estimation based adaptive algorithm for a second-order adaptive FIR notch filter." Signal Processing 88, no. 2 (February 2008): 315–25. http://dx.doi.org/10.1016/j.sigpro.2007.08.004.

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Zhao, Hui, Shengnan Li, Hongyu Yang, and Quan Zhou. "A stability controlling-based approach for designing 1-D variable fractional delay all-pass filters." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 6 (November 5, 2018): 2224–31. http://dx.doi.org/10.1108/compel-01-2018-0053.

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Purpose Variable fractional delay filtering is an important technology in signal processing; the research shows that all-pass variable fractional delay (VFD) filters achieve higher design accuracy than FIR VFD filters; therefore, the design, analysis and implementation of all-pass VFD filters are of great importance. Design/methodology/approach In this paper, a two-stage approach for the design of general 1-D stable VFD all-pass filters is proposed. The method takes the desired group delay range [N−1, N], where N is the filter order. Findings The design algorithm is decomposed into two design stages: first, a set of fixed delay all-pass filters are designed by minimizing a set of objective functions defined in terms of approximating error criterion and filter stability constraint. Then, the design result is determined by fitting each of the fixed delay all-pass filter coefficients as 1-D polynomials. A design example together with its comparisons with those of the recent literature studies is given to justify the effectiveness of the proposed design method. Originality/value An illustrating design example shows that the method proposed can achieve better filter performances than the existing ones.

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H Bailmare, Ravi, S. J. Honale, and Pravin V Kinge. "Design and Implementation of Adaptive FIR filter using Systolic Architecture." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 2 (July 1, 2014): 54. http://dx.doi.org/10.11591/ijres.v3.i2.pp54-61.

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<p>The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases.</p>

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Chen, Xiao, Zhi-gong Wang, and Fei Li. "A 3rd-order 1-bit Σ-Δ modulator with a 2-tap FIR filter embedded." IEICE Electronics Express 16, no. 19 (2019): 20190365. http://dx.doi.org/10.1587/elex.16.20190365.

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Roy, Subhabrata, and Abhijit Chandra. "On the Order Minimization of Interpolated Bandpass Method Based Narrow Transition Band FIR Filter Design." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 11 (November 2019): 4287–95. http://dx.doi.org/10.1109/tcsi.2019.2928052.

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Journal articles on the topic 'FIR filter order'

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