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Dissertations / Theses on the topic 'FIR filters'
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Cadena, Pico Jorge Eduardo. "Perfect Reconstruction Filter Bank Structure Based On Interpolated FIR Filters." Thesis, Virginia Tech, 2016. http://hdl.handle.net/10919/71756.
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State of the art filter bank structures achieve practically perfect reconstruction with very high computational efficiency. However, the increase in computational requirements due to the need to process increasingly wider band signals is paramount. New filter bank structures that provide extra information about a signal while achieving the same level of required efficiency, and perfect reconstruction properties, need to be developed. In this work a new filter bank structure, the interpolated FIR (IFIR) filter bank is developed. Such a structure combines the concepts of filter banks, and interpolated FIR filters. The filter design procedures for the IFIR filter bank are developed and explained.
The resulting structure was compared with the non-maximally-decimated filter bank (NMDFB), achieving the same performance in terms of the number of multiplications required per sample and the overall distortion introduced by the system, when operating with Nyquist prototype filters.
In addition, the IFIR filter is tested in both simulated and real communication environments. Performance, in terms of bit-error-rate, was found to not be degraded significantly when using the IFIR filter bank system for transmission and reception of QPSK symbols.Master of Science
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Kasturi, Nitin. "Power reducing algorithms in FIR filters." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/42710.
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Rosler, Lucas Owen. "Design and Analysis of an FPGA Based Low Tap Band-stop FIR Filter." Youngstown State University / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1619798270047225.
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Shahein, Ahmed [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "Power optimization methodologies for digital FIR decimation filters = Leistungsoptimierungsmethoden für digitale FIR Dezimationsfiltern." Freiburg : Universität, 2014. http://d-nb.info/1123480664/34.
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Peng, Su. "Design and analysis of FIR filters based on Matlab." Thesis, Linnéuniversitetet, Institutionen för fysik och elektroteknik (IFE), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-26759.
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In digital control system, interference, which is mixed in the input signal, has a great influence on the performance of the system. Therefore, processing of input signal has to be done to get useful signal. Finite impulse response (FIR) filter plays an important role in the processing of digital signal. Designing the FIR filter by Matlab can simplify the complicated computation in simulation and improve the performance. By using the methods of window function, frequency sampling and convex optimization techniques, the design of FIR filter has been processed by Matlab. In the view of the designed program of Matlab and I can get the amplitude-frequency characterization. By using the FIR digital filters which have been designed to process the input signal based on the Matlab function, the filtering effect of different digital filters is analyzed by comparing the signal’s amplitude-frequency diagrams which have been generated. The experimental results show that the FIR filters designed in this paper are effective.
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Chit, Nassim N. "Weighted Chebyshev complex-valued approximation for FIR digital filters." Thesis, Swansea University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278340.
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Landy, A. "The design and implementation of multiplierless fir image filters." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383241.
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Karam, Lina J. "Design of complex digital FIR filters in the chebyshev sense." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/22219.
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Zhang, Yuhong. "Design and realization of FIR and bireciprocal wave digital filters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0024/MQ51826.pdf.
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Piskin, Hatice. "Design And Implementation Of Fir Digital Filters With Variable Frequency Characteristics." Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/2/12606853/index.pdf.
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Variable digital filters (VDF) find many application areas in communication, audio, speech and image processing. This thesis analyzes design and implementation of FIR digital filters with variable frequency characteristics and introduces two design methods. The design and implementation of the proposed methods are realized on Matlab software program. Various filter design examples and comparisons are also outlilned. One of the major application areas of VDFs is software defined radio (SDR). The interpolation problem on sample rate converter (SRC) unit of the SDR is solved by using these filters. Realizations of VDFs on SRC are outlined and described. Simulations on Simulink and a specific hardware are examined.
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Sokol, Thomas M. "Finite impulse response (FIR) filters to simulate response of an antenna." Connect to resource, 2006. http://hdl.handle.net/1811/6442.
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Thesis (Honors)--Ohio State University, 2006.Title from first page of PDF file. Document formatted into pages: contains 42 p.; also includes graphics. Includes bibliographical references (p. 42). Available online via Ohio State University's Knowledge Bank.
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Park, Shinwoong. "Reconfigurable Discrete-time Analog FIR filters for Wideband Analog Signal Processing." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/99794.
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Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling.
The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations.
Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications.PHD
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Chabbi, Charef. "VLSI NMOS hardware design of a linear phase FIR low pass digital filer." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1183749814.
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González, David Muñoz. "Discovering unknown equations that describe large data sets using genetic programming techniques." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2639.
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FIR filters are widely used nowadays, with applications from MP3 players, Hi-Fi systems, digital TVs, etc. to communication systems like wireless communication. They are implemented in DSPs and there are several trade-offs that make important to have an exact as possible estimation of the required filter order.
In order to find a better estimation of the filter order than the existing ones, genetic expression programming (GEP) is used. GEP is a Genetic Algorithm that can be used in function finding. It is implemented in a commercial application which, after the appropriate input file and settings have been provided, performs the evolution of the individuals in the input file so that a good solution is found. The thesis is the first one in this new research line.
The aim has been not only reaching the desired estimation but also pave the way for further investigations.
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Kwan, Man-Wai. "Minimal transmit redundancy FIR precoder-equalizer systems design /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20KWAN.
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Bae, Cheolyong, and Madhur Gokhale. "Implementation of High-Speed 512-Tap FIR Filters for Chromatic Dispersion Compensation." Thesis, Linköpings universitet, Datorteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-153435.
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A digital filter is a system or a device that modifies a signal. This is an essential feature in digital communication. Using optical fibers in the communication has various advantages like higher bandwidth and distance capability over copper wires. However, at high-rate transmission, chromatic dispersion arises as a problem to be relieved in an optical communication system. Therefore, it is necessary to have a filter that compensates chromatic dispersion. In this thesis, we introduce the implementation of a new architecture of the filter and compare it with a previously proposed architecture.
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Barnes, Leighton P. (Leighton Pate). "Uniform FIR approximation of causal Wiener filters with applications to causal coherence." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100295.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 35-36).
Leveraging the relationship between Wiener filtering and the coherence function, a version of coherence is defined that captures the causal relationship between WSS processes. This causal coherence is interpreted in a modeling context and used to demonstrate what a frequency dependent measure for causality both can and can't represent. To understand how well frequency dependent coherence spectra can be estimated with finite order approximations, the convergence of the FIR causal Wiener lters to the full IIR causal Wiener filter is investigated as filter length goes to infinity. The main results prove Lp convergence of the frequency responses for p = 1, 2, [infinity] under certain Hölder continuity conditions on the power spectra, as well as give asymptotic upper bounds for the convergence error. Keywords: Wiener lters, causality, coherence, FIR approximation
by Leighton P. Barnes.
M. Eng.
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Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.
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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.
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Karlsson, Magnus. "Implementation of digit-serial filters." Doctoral thesis, Linköpings universitet, Institutionen för systemteknik, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3520.
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In this thesis we discuss the design and implementation of Digital Signal Processing (DSP) applications in a standard digital CMOS technology. The aim is to fulfill a throughput requirement with lowest possible power consumption. As a case study a frequency selective filter is implemented using a half-band FIR filter and a bireciprocal Lattice Wave Digital Filter (LWDF) in a 0.35 µm CMOS process. The thesis is presented in a top-down manner, following the steps in the topdown design methodology. This design methodology, which has been used for bit-serial maximally fast implementations of IIR filters in the past, is here extended and applied for digit-serial implementations of recursive and non-recursive algorithms. Transformations such as pipelining and unfolding for increasing the throughput is applied and compared from throughput and power consumption points of view. A measure of the level of the logic pipelining is developed, i.e., the Latency Model (LM), which is used as a tuning variable between throughput and power consumption. The excess speed gained by the transformations can later be traded for low power operation by lowering the supply voltage, i.e., architecture driven voltage scaling. In the FIR filter case, it is shown that for low power operation with a given throughput requirement, that algorithm unfolding without pipelining is preferable. Decreasing the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. The digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput. In the bireciprocal LWDF case, the LM order can be used as a tuning variable for a trade-off between low energy consumption and high throughput. In this case using LM 0, i.e., non-pipelined processing elements yields minimum energy consumption and LM 1, i.e., use of pipelined processing elements, yields maximum throughput. By introducing some pipelined processing elements in the non-pipelined filter design a fractional LM order is obtained. Using three adders between every pipeline register, i.e., LM 1/3, yields a near maximum throughput and a near minimum energy consumption. In all cases should the digit-size be equal to the number of fractional bits in the coefficient. At the arithmetic level, digit-serial adders is designed and implemented in a 0.35 µm CMOS process, showing that for the digit-sizes, , the Ripple-Carry Adders (RCA) are preferable over Carry-Look-Ahead adders (CLA) from a throughput point of view. It is also shown that fixed coefficient digitserial multipliers based on unfolding of serial/parallel multipliers can obtain the same throughput as the corresponding adder in the digit-size range D = 2...4. A complex multiplier based on distributed arithmetic is used as a test case, implemented in a 0.8 µm CMOS process for evaluation of different logic styles from robustness, area, speed, and power consumption points of view. The evaluated logic styles are, non-overlapping pseudo two-phase clocked C2MOS latches with pass-transistor logic, Precharged True Single Phase Clocked logic (PTSPC), and Differential Cascade Voltage Switch logic (DCVS) with Single Transistor Clocked (STC) latches. In addition we propose a non-precharged true single phase clocked differential logic style, which is suitable for implementation of robust, high speed, and low power arithmetic processing elements, denoted Differential NMOS logic (DN-logic). The comparison shows that the two-phase clocked logic style is the best choice from a power consumption point of view, when voltage scaling can not be applied and the throughput requirement is low. However, the DN-logic style is the best choice when the throughput requirements is high or when voltage scaling is used.
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Huang, Walter. "Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed arithmetic." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31653.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Anderson, David V.; Committee Member: Ferri, Bonnie H.; Committee Member: Hasler, Paul E.; Committee Member: Kang, Sung Ha; Committee Member: McClellan, James H.; Committee Member: Wolf, Wayne H. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Fanian, Kaveh Electrical Engineering & Telecommunications Faculty of Engineering UNSW. "Diamond-shaped 2-dimentional digital FIR filters with high performance and low complexity." Publisher:University of New South Wales. Electrical Engineering & Telecommunications, 2008. http://handle.unsw.edu.au/1959.4/42898.
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2-D digital filters have found numerous applications in signal processing and their design is subject to intensive research. In general, these filters are divided into two types: Separable filters as a product of two 1-D filters, and Non-Separable filters. Separable filters are easier to design but work mostly for rectangular-shaped frequency spectrums. On the other hand, non-separable filters are preferred for designing other shapes of spectrum divisions such as diamond-shaped, circular-shaped, fan-shaped, etc. but their design is much more complicated. When designing 2-D filters, there are several important issues which should be considered. These issues are: the accuracy of the pass-band and the transition-band, the pass-band ripple, the stop-band attenuation and the complexity of the filter for its digital implementation. One important class of 2-D filters is the class of 2-D digital filters with Four-Fold symmetry. Despite the fact that these filters can be designed by using some kind of McClellan transform and yet admit fast digital implementation, the shape of their pass-band cannot be easily controlled. The accuracy of the description of the pass-band shape requires a high-order polynomial transformation, but such a transformation leads to the explosive growth of the filter order and its implementation complexity. While there exist some known approaches that can control the pass-band shape more efficiently, they all suffer from the fact that their transition-band should be wide enough to avoid possible singularities that may arise due to the interpolation step. In this study, the semi-definite programming as a tool, is adopted to design non-separable four-fold symmetric 2-D digital filters and it will be shown that unlike previously proposed semi-definite programming based approaches, this approach is advantageous due to the facts that all the filter specifications are met while interpolation is avoided, the dimension of the semi-definite programming formulation is kept moderate, and moreover, the designed filters admit fast digital implementation despite the fact that they are non-separable and are not designed based on 1-D filters. The simulation clearly confirms the viability of this approach. Finally, although only diamond-shaped filters are considered in this study, other filters such as circular-shaped, elliptic-shaped or fan-shaped are expected to be designed in a similar fashion.
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Hounsell, Benjamin Iain. "Programmable architectures for the automated design of digital FIR filters using evolvable hardware." Thesis, University of Edinburgh, 2001. http://hdl.handle.net/1842/14109.
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Continuing increases in both the size and complexity of digital signal processing (DSP) systems places a considerable demand on the design engineer to develop hardware architectures capable of fulfilling the growing functional requirements expected of modern DSP devices. Automated circuit design techniques provide the design engineer with a tool to more effectively generate high performance signal processors capable of meeting demanding specifications. Evolvable hardware (EHW) is a relatively new approach to automated circuit design which utilises advances in reconfigurable hardware technology and the power of modern micro processors to generate circuits based on the principles of natural selection and evolution. This thesis investigates the suitability of software-biased and hardware oriented programmable platforms, configured via EHW, and tailored for the automated design of high performance DSP circuits. Performance criteria such as timing, area and circuit robustness are considered. A number of benchmarked DSP circuits were initially considered. It was shown that by using larger functional logic macros as building blocks EHW is more successful at generating circuit solutions than if only gate primitives are used. In addition, the circuits generated are of comparable or better performance than equivalent circuits developed using a standard digital design methodology. Results also indicated that for more complex DSP functions to be generated, EHW platforms must use larger functional blocks, constrained for a specific application. Finite Impulse Response (FIR) filters were identified as the backbone of many DSP applications, and the multiplication unit was targeted as the performance critical component. A novel Programmable Arithmetic Logic Unit (PALU) was therefore developed as a functional building block suitable for automated digital filter design using EHW. The PALU replaces coefficient multiplication with a series of bit-shifts, additions and subtractions. Two distinct arrays of PALU were developed based on conventional FPGA and PLA re-configurable hardware architectures. Results show that a PLA architecture with 2 levels of hierarchical interconnect and column-based fixed tap outputs provides a platform most suited to automated filter design using the EHW technique. The PLA was also shown to be robust to faults covering up to 25% of the array when configured using EHW.
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Satheesh, Varma Nikhil. "Design and implementation of an approximate full adder and its use in FIR filters." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89430.
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Implementation of the polyphase decomposed FIR filter structure involves two steps; the generation of the partial products and the efficient reduction of the generated partial products. The partial products are generated by a constant multiplication of the filter coefficients with the input data and the reduction of the partial products is done by building a pipelined adder tree using FAs and HAs. To improve the speed and to reduce the complexity of the reduction tree a4:2 counter is introduced into the reduction tree. The reduction tree is designed using a bit-level optimized ILP problem which has the objective function to minimize the overall cost of the hardware used. For this purpose the layout design for a 4:2 counter has been developed and the cost function has been derived by comparing the complexity of the design against a standard FA design. The layout design for a 4:2 counter is implemented in a 65nm process using static CMOS logic style and DPL style. The average power consumption drawn from a 1V power supply, for the static CMOS design was found to be 16.8μWand for the DPL style it was 12.51μW. The worst case rise or fall time for the DPL logic was 350ps and for the static CMOS logic design it was found to be 260ps. The usage of the 4:2 counter in the reduction tree infused errors into the filter response, but it helped to reduce the number of pipeline stages and also to improve the speed of the partial product reduction.
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Ruiz, Fontes Natanael. "An analysis of the IIR an FIR Wiener filters with applications to underwater acoustics." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1997. http://handle.dtic.mil/100.2/ADA333441.
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Thesis (M.S. in Engineering Acoustics and M.S. in Electrical Engineering) Naval Postgraduate School, June 1997.Thesis advisor, Charles W. Therrien. Includes bibliographical references (p. 75). Also available online.
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Fatine, Steven Carleton University Dissertation Engineering Electronics. "Design and VLSI implementation of CMOS decimation and interpolation half-band FIR digital filters." Ottawa, 1996.
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Rusc, Thomas [Verfasser]. "Quality of Quantized and Non-Quantized FIR Filters for Single Channels or Near-Perfect Reconstruction Cosine-Modulated Filter Banks / Thomas Rusc." Aachen : Shaker, 2007. http://d-nb.info/1166509508/34.
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Walters, Allison L. "A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/35765.
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This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s.Master of Science
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Nayebi, Kambiz. "A time domain framework for the analysis and design of FIR multirate filter bank systems." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/13867.
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Rodney, David M. "Digital Channelized Wide Band Receiver Implemented with a Systolic Array of Multi-Rate FIR Filters." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1150923373.
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Tarumi, Toshiyasu. "Data Analysis Strategies for Airborne Remote Sensing of Volatile Organic Compounds Using Passive Fourier Transform Infrared Spectrometry." Ohio University / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1088534216.
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Nakad, Zahi Samir. "High Performance Applications on Reconfigurable Clusters." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/35682.
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Many problems faced in the engineering world are computationally intensive. Filtering using FIR (Finite Impulse Response) filters is an example to that. This thesis discusses the implementation of a fast, reconfigurable, and scalable FIR (Finite Impulse Response) digital filter. Constant coefficient multipliers and a Fast FIFO implementation are also discussed in connection with the FIR filter. This filter is used in two of its structures: the direct-form and the lattice structure. The thesis describes several configurations that can be created with the different components available and reports the testing results of these configurations.Master of Science
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Mousa, Wail Abdul-Hakim. "Design &implementation of complex-valued FIR digital filters with application to migration of seismic data." Thesis, University of Leeds, 2006. http://etheses.whiterose.ac.uk/4712/.
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One-dimensional (I-D) and two-dimensional (2-D) frequency-space seismic migration FIR digital filter coefficients are of complex values when such filters require special space domain as well as wavenumber domain characteristics. In this thesis, such FIR digital filters are designed using Vector Space Projection Methods (VSPMs), which can satisfy the desired predefined filters' properties, for 2-D and three-dimensional (3-D) seismic data sets, respectively. More precisely, the pure and the relaxed projection algorithms, which are part of the VSPM theory, are derived. Simulation results show that the relaxed version of the pure algorithm can introduce significant savings in terms of the number of iterations required. Also, due to some undesirable background artifacts on migrated sections, a modified version of the pure algorithm was used to eliminate such effects. This modification has also led to a significant reduction in the number of computations when compared to both the pure and relaxed algorithms. We further propose a generalization of the l-D (real/complex-valued) pure algorithm to multi-dimensional (m-D) complex-valued FIR digital filters, where the resulting frequency responses possess an approximate equiripple nature. Superior designs are obtained when compared with other previously reported methods. In addition, we also propose a new scheme for implementing the predesigned 2-D migration FIR filters. This realization is based on Singular Value Decomposition (SVD). Unlike the existing realization methods which are used for this geophysical application, this cheap realization via SVD, compared with the true 2-D convolution, results in satisfactory wavenumber responses. Finally, an application to seismic migration of 2-D and 3-D synthetic sections is shown to confirm our theoretical conclusions. The proposed resulting migration FIR filters are applied also to the challenging SEGIEAGE Salt model data. The migrated section (image) outperformed images obtained using other FIR filters and with other standard migration techniques where difficult structures contained in such a challenging model are imaged clearly.
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Sweeney, Paul. "THE NEXT GENERATION AIRBORNE DATA ACQUISITION SYSTEMS. PART 1 - ANTI-ALIASING FILTERS: CHOICES AND SOME LESSONS LEARNED." International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/605378.
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International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, NevadaThe drive towards higher accuracy and sampling rates has raised the bar for modern FTI signal conditioning. This paper focuses on the issue of anti-alias filtering. Today's 16-bit (and greater resolution) ADC’s, coupled with the drive for optimum sampling rates, means that filters have to be more accurate and yet more flexible than ever before. However, in order to take full advantage of these advances, it is important to understand the trade-offs involved and to correctly specify the system filtering requirements. Trade-offs focus on: • Analog vs. Digital signal conditioning • FIR vs. IIR Digital Filters • Signal bandwidth vs. Sampling rate • Coherency issues such as filter phase distortion vs. delay This paper will discuss each of these aspects. In particular, it will focus on some of the advantages of digital filtering various analog filter techniques. This paper will also look at some ideas for specifying filter cut-off and characteristics.
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Uzinski, Julio Cezar [UNESP]. "A state-space parameterization for perfect-reconstruction wavelet FIR filter banks with special orthonormal basis functions." Universidade Estadual Paulista (UNESP), 2016. http://hdl.handle.net/11449/146716.
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
Esta tese apresenta uma parametrização no espaço de estados para a transformada wavelet rápida. Esta parametrização é baseada em funções de base ortonormal e filtros de resposta finita ao impulso simultaneamente, uma vez que, a transformada rápida wavelet é um algoritmo que consiste em decompor sinais no domínio do tempo em sequências de coeficientes baseados numa base ortogonal de funções wavelet. Deste modo, vantagens apresentadas por ambas as propostas são incorporadas. Modelos de resposta finita ao impulso têm propriedades atrativas como vantagens computacionais e analíticas, garantia de estabilidade BIBO e robustez para a mudança de alguns parâmetros, dentre outras. Por outro lado, séries de funções de base ortonormal têm características que as fazem atrativas para a modelagem de sistemas dinâmicos, como ausência de recursão da saída, a não necessidade de se conhecer previamente a estrutura exata do vetor de regressão, possibilidade de aumentar a capacidade de representação do modelo aumentando-se o número de funções ortonormais utilizadas, desacoplamento natural das saídas em modelos multivariáveis; tolerância a dinâmicas não modeladas. Além disso, a realização no espaço de estados é mínima. A contribuição deste trabalho consiste no desenvolvimento de uma realização no espaço de estados para bancos de filtros wavelet, em que há a presença explícita de parâmetros que podem ser livremente ajustados mantendo as propriedades de reconstrução perfeita e ortonormalidade. Para ilustrar o funcionamento e as vantagens da técnica proposta, alguns exemplos de decomposição de sinais no contexto de processamento de sinais mostrando que ela proporciona os mesmos coeficientes wavelet que a transformada wavelet rápida, e uma aplicação em controle através de realimentação dinâmica de estados também são apresentados nesta tese.
This thesis presents a state-space parameterization for the fast wavelet transform. This parameterization is based on orthonormal basis functions and finite impulse response filters at the same time, since the fast wavelet transform is an algorithm, which converts a signal in the time domain into a sequence of coefficients based on an orthogonal basis of small finite wavelet functions. Advantages presented by both proposals are incorporated. Finite impulse response systems have attractive properties, for instance, computational and analytical advantages, BIBO stability and robustness guarantee to some parameter changes, and others. On the other hand, orthonormal basis functions have some characteristics that make them attractive for dynamic systems modeling, examples are, output recursion absence, not requiring prior regression vector exact structure knowledge; possibility of increasing the model representation capacity by increasing the number of orthonormal functions employed; natural outputs uncoupling in multivariable models; tolerance to unmodeled dynamics, and others. Furthermore, the state-space realization is minimal. The contribution of this work consists in the development of a state-space realization for a wavelet filter bank, with the explicit presence of the parameters that can be freely adjusted, keeping perfect-reconstruction and orthonormality guarantees. In order to illustrate advantages and how the proposed technique works, some decomposition examples in signal processing context are presented showing that it provides the same wavelet coefficients as the fast wavelet transform, and an application on dynamic state feedback control is also presented in this thesis.
CNPq: 160545/2013-7
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Uzinski, Julio Cezar. "A state-space parameterization for perfect-reconstruction wavelet FIR filter banks with special orthonormal basis functions /." Ilha Solteira, 2016. http://hdl.handle.net/11449/146716.
Full textAbstract:
Orientador: Francisco Villarreal AlvaradoResumo: Esta tese apresenta uma parametrização no espaço de estados para a transformada wavelet rápida. Esta parametrização é baseada em funções de base ortonormal e filtros de resposta finita ao impulso simultaneamente, uma vez que, a transformada rápida wavelet é um algoritmo que consiste em decompor sinais no domínio do tempo em sequências de coeficientes baseados numa base ortogonal de funções wavelet. Deste modo, vantagens apresentadas por ambas as propostas são incorporadas. Modelos de resposta finita ao impulso têm propriedades atrativas como vantagens computacionais e analíticas, garantia de estabilidade BIBO e robustez para a mudança de alguns parâmetros, dentre outras. Por outro lado, séries de funções de base ortonormal têm características que as fazem atrativas para a modelagem de sistemas dinâmicos, como ausência de recursão da saída, a não necessidade de se conhecer previamente a estrutura exata do vetor de regressão, possibilidade de aumentar a capacidade de representação do modelo aumentando-se o número de funções ortonormais utilizadas, desacoplamento natural das saídas em modelos multivariáveis; tolerância a dinâmicas não modeladas. Além disso, a realização no espaço de estados é mínima. A contribuição deste trabalho consiste no desenvolvimento de uma realização no espaço de estados para bancos de filtros wavelet, em que há a presença explícita de parâmetros que podem ser livremente ajustados mantendo as propriedades de reconstrução perfeita e ortonormalidade. ... (Resumo completo, clicar acesso eletrônico abaixo)
Doutor
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El-Kareh, Flavio Considera. "Algoritmos genéticos aplicados ao projeto de filtros com coeficientes em soma de potências de dois." Universidade do Estado do Rio de Janeiro, 2011. http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=3407.
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Coordenação de Aperfeiçoamento de Pessoal de Nível SuperiorEsta dissertação tem como objetivo aplicar um algoritmo genético (GA) ao projeto de filtros FIR com coeficientes quantizados representados em somas de potências de dois com sinal (SPT). Os filtros FIR apresentam configurações que permitem a obtenção de fase linear, atributo desejado em diversas aplicações que necessitam de atraso de grupo constante. A representação SPT, de fácil implementação em circuitos, foi discutida e uma comparação das representações SPT mínimas e canônicas foi feita, baseada no potencial de redução de operações e na variedade de valores representáveis. O GA é aplicado na otimização dos coeficientes SPTs do filtro, para que este cumpra as suas especificações de projeto. Foram feitas análises sobre o efeito que diversos parâmetros do GA como a intensidade de seleção, tamanho das populações, cruzamento, mutação, entre outros, têm no processo de otimização. Foi proposto um novo cruzamento que produz a recombinação dos coeficientes e que obteve bons resultados. Aplicou-se o algoritmo obtido na produção de filtros dos tipos passa-baixas, passa-altas, passa-faixas e rejeita-faixas.
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Migdadi, Hassan S. O., Raed A. Abd-Alhameed, Huthaifa A. N. Obeidat, James M. Noras, E. A. A. Qaralleh, and Mohammad J. Ngala. "FIR implementation on FPGA: investigate the FIR order on SDA and PDA algorithms." 2015. http://hdl.handle.net/10454/9197.
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NoFinite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) applications. Several attempts have been made to develop hardware realization of FIR filters characterized by implementation complexity, precision and high speed. Field Programmable Gate Array is a reconfigurable realization of FIR filters. Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, are now most often realized by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs. In this paper, distributed arithmetic (DA) realization of FIR filter as serial and parallel are discussed in terms of hardware cost and resource utilization.
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Laio, Shi-Pi, and 廖士弼. "Automatic Chip Design of FIR filters." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/kcexpq.
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碩士亞東技術學院
資訊與通訊工程研究所
100
In this study, we used the Microsoft Visual Studio(MVS) software to achieve Integrated FIR IP/Chip Design Automation(IFICDA) system, provide user a simple GUI interface to set the filter parameters, automatically synthesize the filters of optimize RTL Code, automatic synthesis of logic gates and thus the circuit simulations, and automated chip layout design in final. Validate examples of the system for several FIR digital filter chip design, and the chip performs well and the design process is smooth and simple. CSE (Canonic Signed the Digit) algorithm [9-10] and Booth algorithms have well effectively simplification in the simplification of FIR digital filter design. However, the study found the advantages of simplification group but also concerns of overhead in simplification. That affects the effectiveness of the simplification group. We proposed a new greedy algorithm in IFICDA, first the product term of the filter coefficients are represented as the Booth and CSD as well as Mix expression using a combination of both, and then were the free-paid iterative HCSE (Horizontal Common Subexpression Elimination) simplification and effective HCSE simplification. Respectively, that solves defects of the ungrouped free-paid group and award use of over-paid grouped simplification. The definition of the SG (Select Gain) values as a criterion of group selecting in free-paid iterative HCSE simplification algorithm, this standardization of selecting of simplification group will not miss the group of better efficiency in the process of group simplification. We also defined useful measurement criteria in effective HCSE simplification, and avoid the award use of over-paid simplification. Finally, we select optimal solution from these simplifications of three represents, to generate the IP of the FIR digital filter, to export the better performance of RTL Code. In this study, chip layout design included in IFICDA, proposed a chip design automation of CDA process based on Cell-based. CDA process generates an “ACD.scr” file automatically. In IFICDA, the ACD file uses “OitCellLibrary” of OIT Lab results of chip and application, launches Design Compiler to synthesis the logic gates using aforementioned RTL code, and then runs APR (Auto Place & Route) program by Encounter to produce the FIR digital filter chip layout design. The system is also combined with Hspice simulation, provides circuit simulation and verification of the Gate Level file. A few various types of FIR digital filter specifications of 49taps, 20-bit word (5 integer bits + 15 float bits), have been applied in the IFICDA system for automated design verification. The efficiency of the greedy algorithm can reach more than 68.0%, and the average generation time for each chip design is also in 10 minutes. These application practical confirm the greedy algorithm improving the FIR digital filter design performance in IFICDA, from efficient RTL Code generation to quickly run through the chip design process, greatly shorten the development time of FIR digital filter chip design.
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XU, ZHONG-ZHI, and 徐忠枝. "Eigen design of FIR digital filters." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/72402350033934377789.
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Lin, Yu-Wei, and 林煜偉. "Design of Variable FIR Filters and IIR All-Pass Filters and Filter Banks with Discrete Coefficients." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/20542395782371250093.
Full textAbstract:
碩士國立臺灣大學
電信工程學研究所
92
In this thesis, we consider three kinds of digital filters with filter coefficients taking on -1, 0, +1 only. One is variable fractional delay FIR filter and the others are IIR allpass filter and filter banks. We design these two kinds of digital filters with continuous coefficients using WLS algorithm and Karmarkar algorithm, in minmax criteria methods are proposed.. When we implement a filter of conventional structure, we always need multibit multipliers. But the circuit complexity and high cost of multibit multipliers always confuse us. Thus, we adopt a new filter structure [25] whose main part consists of a transversal filter with tap coefficients restricted to -1, 0, +1 only and cascaded with an appropriate recursive network with some specific resetting function. Therefore, it is not necessary for transversal filter to use multipliers; the adopted configuration is suitable for hardware implementation. We apply the new structure to the design of the digital filter we discuss above. In this thesis, we design variable delay FIR filter, IIR allpass filter, and IIR filter banks. The design examples are demonstrated to illustrate the effectiveness of the new structure.
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Su, Wei. "Decomposition of high-order FIR filters and minimum-phase filter design." 2002. http://etd.utk.edu/2002/SuWei.pdf.
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Thesis (M.S.)--University of Tennessee, Knoxville, 2002.Title from title page screen (viewed Sept 25, 2002). Thesis advisor: L. Montgomery Smith. Document formatted into pages (viii, 135 p. : ill.). Vita. Includes bibliographical references (p. 66-68).
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Tzeng, Shian-Tang, and 曾顯棠. "GENETIC ALGORITHM APPROACH FOR DESIGNING FIR DIGITAL FILTERS AND FUZZY FILTERS." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/94176813703985013306.
Full textAbstract:
博士大同大學
電機工程研究所
88
By minimizing a quadratic measure of the error in the design bands, a new method of designing finite-duration impulse response (FIR) digital filters with genetic algorithm (GA) approach is proposed. These real/complex-valued chromosomes are evolved to get the filter coefficients through appropriate crossover, mutation, and selection operations. The proposed design procedure is general enough to incorporate the frequency-domain constraints. This method is not only simple but also optimal in the least-squares sense. Therefore, the new method with GA approach can design the following filters: 1. 1-D linear-phase FIR digital filters such as Hilbert transformers and lower/higher-order digital differentiators. 2. 1-D nonlinear-phase complex FIR digital filters. 3. Log filters. 4. 2-D FIR digital filters by McClellan transformation. 5. Unified approach to the design of sixteen types 2-D quarter-plane symmetric filters. 6. Fuzzy filters for mixed noise removal during image processing. Furthermore, several new aspects and important properties with GA approach for designing digital filters are proposed as follows: 1. General McClellan transformation for designing 2-D complex filters. 2. Symmetric properties of 2-D sequences and their applications for designing sixteen types 2-D quarter-plane symmetric filters.
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Lin, Ping-Long, and 林品隆. "Designs of FIR Filters Using Convex Programming." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/04126180017388256771.
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碩士國立高雄第一科技大學
電腦與通訊工程研究所
100
In this thesis, the finite impulse response (FIR) digital filters are designed by using convex programming or convex optimization method. First, the convex set, convex function, and convex optimization are reviewed briefly. Then, FIR filters with various specifications are designed including frequency selective filters, digital differentiators, Hilbert transformers and fractional delay filters. For each specification, the mini-max design, least-squares design, and sparse-coefficient design are studied in details. Finally, the numerical examples are demonstrated to show the effectiveness of the convex programming method in the FIR filter designs.
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Lai, You Zhuan, and 賴友專. "Design of fir digital filters for communication." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/41814284391863410928.
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HUANG, YONG-PO, and 黃永波. "Discrete coefficient linear phase FIR filters design." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/54749157881570676813.
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Lin, Chih-Hsin, and 林志新. "The Design of 3-D Perfect Reconstruction Filter Banks, Digital All-Pass Filters, and Complex FIR Digital Filters." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/22345458364143107720.
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碩士國立臺灣科技大學
電子工程系
87
This thesis presents several novel and efficient techniques for designing three-dimensional (3-D) perfect reconstruction (PR) filter banks, FIR digital all-pass filters, and complex FIR digital filters in minimax sense. The proposed approaches are developed based on the affine and dual affine scaling variants of Karmarkar's algorithm. As for the 3-D perfect reconstruction digital filter banks, two novel techniques are proposed for designing PR filter banks with FIR analysis and synthesis filters having linear phase responses. The designed analysis and synthesis filters are in the minimax sense subject to the perfect reconstruction constraints. With regard to the design of FIR digital all-pass filters, we propose design techniques via minimizing the peak magnitude error and peak phase error simultaneously or minimizing the peak magnitude error and peak group delay error simultaneously. The filter coefficients are obtained by an affine scaling variant of Karmarkar's algorithm. For designing complex FIR digital filters, the original complex approximation is divided into two real ones first. Then the affine scaling variant of Karmarkar's algorithm is also applied to minimize the real part and imaginary part error in minimax sense to get the complex impulse response coefficients. From the simulation examples demonstrated in each chapter of this thesis, the effectiveness of the proposed design techniques for each considered problem can be confirmed.
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Huang, Yao-Hsing, and 黃耀興. "esign of multidimensional FIR digital filters for sampling structure conversion and filter banks." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/72403220615918437649.
Full textAbstract:
碩士國立高雄大學
電機工程學系碩士班
100
The conversion between different periodic sampling standards is an important problem, especially for the conversion between quincunx and rectangular structures in television image processing and HDTV applications. For rcconstructing the original picture accurately, minimizing a quadratic measure of the error in the passband and stopband, a two-dimensional diamond-shaped FIR eigenfilter is designed for sampling-structure conversion. Time- and frequency-domain constraints are easily incorporated into this method, such that the design difficulty inherent to sampling-conversion filters can be effectivly solved. Finally this thesis concludes with design of filter banks. It is well known that the multirate systems can be used in many fields, such as video encoding, audio processing and video compression. In this thesis, two- and three-dimensional digital filters are designed by using the weighted least-squares (WLS) approach. The method can be generalized such that multidimensional QMF banks can be designed by the proposed to further reduce the peak error of overall magnitude response. Comparing with the existing works concern the design of perfect-reconstuction QMF bank, only of the filters is needed to be designed under the cost of magnitude distortion, but the system complexity can be reduced drastically. Several examples, including design of 2-D and 3-D QMF bank, will be presented to demonstrate the effectiveness of the proposed method. Keywords: FIR Filter、Weighted Least-Squares Approach、Two-Dimensional Digital Filter、Three-Dimensional Digital Filter、Multirate System、Filter Banks、Sampling Structure Conversion.
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Yang, Tsung-Hsun, and 楊宗訓. "Complexity-Aware Quantization and Design of FIR Filters." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/88637531450470791115.
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碩士國立交通大學
電子工程系
91
FIR filters are widely used in DSP applications, where customized implementations are frequently desirable for area or power optimization. This thesis presents a novel quantization algorithm to optimize the FIR coefficients for efficient implementations. The proposed algorithm precisely distributes a pre-defined addition budget among the quantized coefficients to maximize the filter performance. Both signed-digit representations and our improved common subexpression elimination (CSE) are applied to minimize the complexity at the bit level. Thus, the designers can explicitly trade the implementation complexity for the quantization noise. At the architecture level, we propose an effective algorithm to prevent overflow and to minimize the wordlength of the intermediate variables, which either reduce the adder sizes or improve the round-off error. We describe the systematic synthesis of bit-serial architectures by retiming to further reduce the silicon area. In our experiments, our improved CSE with the optimal signed-digit coding can reduce 50.8%~51.2% additions for comparable quantization errors. Moreover, the bit-serialization can further save 32.99%~34.97% area (estimated in gate counts) for less timing-critical applications. By the way, we also propose a programmable FIR architecture to demonstrate the effectiveness of the trade-offs between quantization errors and execution time at the end of this thesis.
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Μάγκλαρης, Βασίλειος. "FIR φίλτρα σταθερών συντελεστών." Thesis, 2008. http://nemertes.lis.upatras.gr/jspui/handle/10889/1247.
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Στόχος μου ήταν να αναφέρω τις βασικές μεθόδους βελτιστοποίησης της επιφάνειας και της καθυστέρησης ενός FIR φίλτρου σταθερών συντελεστών που έχουν προταθεί τα τελευταία χρόνια, να υλοποιήσω τις μεθόδους βελτιστοποίησης της επιφάνειας και να παραθέσω τα αποτελέσματα εξομοίωσης των παραπάνω μεθόδων.My aim was to present the basic methods of reducing the area and delay of FIR filters of constant coefficients, to create the methods of reducing the area of FIR filters and to compare these methods.
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Zhou, Bo. "High speed digital FIR filter design." Thesis, 1996. http://hdl.handle.net/1957/34326.
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The objective of this thesis is to design a high speed digital FIR filter. The inputs of the
system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs,
multiplies them with their coefficients and adds the results. The main design task is to
take the input data, which are unweighted single-bit binary numbers at 156MHz,
multiply each bit with the corresponding coefficient and add them to get a weighted
multi-bit output at 20MHz.Graduation date: 1997