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Journal articles on the topic 'FIR filters'

Author: Grafiati

Published: 4 June 2021

Last updated: 10 February 2022

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1

Rohini, R., N. V. Satya Narayana, and Durgesh Nandan. "A Crystal View on the Design of FIR Filter." Journal of Computational and Theoretical Nanoscience 17, no. 9 (July 1, 2020): 4235–38. http://dx.doi.org/10.1166/jctn.2020.9052.

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In audio and video signal processing main element is the FIR filter. This paper presents complete information regarding the FIR filters. It also focuses on the design of FIR filters which provide low-area, energy-delay, low-power consumption, high-speed, low critical path, and low complexity. Implementation of FIR filters with different methods like memory-based VLSI architecture, filters for sampling rate conversion, linear phase FIR filters, optimal hybrid form FIR filters, Nyquist filters, hybrid multiplier less FIR filters, low complexity FIR filters, variable partition hybrid form FIR filters, area efficiency FIR filters are discussed in this paper. The objective of this paper to provide all related information regarding FIR filters at one platform.

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Jurisic Bellotti, Maja, and Mladen Vucic. "Sparse FIR Filter Design Based on Signomial Programming." Elektronika ir Elektrotechnika 26, no. 1 (February 16, 2020): 40–45. http://dx.doi.org/10.5755/j01.eie.26.1.23560.

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The goal of sparse FIR filter design is to minimize the number of nonzero filter coefficients, while keeping its frequency response within specified boundaries. Such a design can be formally expressed via minimization of l0-norm of filter’s impulse response. Unfortunately, the corresponding minimization problem has combinatorial complexity. Therefore, many design methods are developed, which solve the problem approximately, or which solve the approximate problem exactly. In this paper, we propose an approach, which is based on the approximation of the l0-norm by an lp-norm with 0 < p < 1. We minimize the lp-norm using recently developed method for signomial programming (SGP). Our design starts with forming a SGP problem that describes filter specifications. The optimum solution of the problem is then found by using iterative procedure, which solves a geometric program in each iteration. The filters whose magnitude responses are constrained in minimax sense are considered. The design examples are provided illustrating that the proposed method, in most cases, results in filters with higher sparsity than those of the filters obtained by recently published methods.

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Jameil, Ahmed K., Yassir A. Ahmed, and Saad Albawi. "Efficient FIR Filter Architecture using FPGA." Recent Advances in Computer Science and Communications 13, no. 1 (March 13, 2020): 91–98. http://dx.doi.org/10.2174/2213275912666190603115506.

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Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

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Parameshappa, G., and D. Jayadevapp. "Efficient uniform digital filter bank with linear phase and FRM technique for hearing aids." International Journal of Engineering & Technology 7, no. 1.9 (March 1, 2018): 69. http://dx.doi.org/10.14419/ijet.v7i1.9.9738.

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This paper attempts to present an uniform digital filter bank based on linear phase FIR and IIR filters applied for Frequency Response Masking (FRM) technique in hearing aid applications.In the proposed filter bank, nine uniformly spaced sub-bands are formed with the help of half band filters and masking filters. These nine channel FIR filter bank is realized using an interpolated half band linear phase FIR filter and an appropriate number of masking FIR filters. The nine channel IIR filter bank is realized using an interpolated half band approximately linear phase IIR filter and an appropriate number of masking filters. The proposed approximately linear phase IIR half band filter bank is compared with filter bank based on linear phase FIR half band filters in terms of area, power, memory and number of gates needed for implementation. The experiment was carried on various hearing loss cases and the results obtained from these tests proves that, the proposed filter bank achieved the required matching between audiograms and magnitude response of the filter bank at very reasonable range with less computational complexity.

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Stamenkovic, Negovan. "Digital FIR filter architecture based on the residue number system." Facta universitatis - series: Electronics and Energetics 22, no. 1 (2009): 125–40. http://dx.doi.org/10.2298/fuee0901125s.

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In this paper, architecture of residue number system used in FIR filters, is presented. For many years residue number coding has been recognized as a system which provides capability for implementation of a high speed addition and multiplication. These advantages of residue number system coding for the high speed FIR filters design results from the fact that an digital FIR filter requires only addition and multiplication. The proposed FIR filter architecture is performed as series of modulo multiplication and accumulation across each modulo. A numerical example illustrates the principles of FIR filtering of an 32 order low pass filter. This architecture is compared with FIR filters direct synthesis. .

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GUSTAFSSON, OSCAR, HÅKAN JOHANSSON, and LARS WANHAMMAR. "SINGLE FILTER FREQUENCY-RESPONSE MASKING FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (October 2003): 601–30. http://dx.doi.org/10.1142/s0218126603001094.

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In this work filter structures that decrease the required number of multipliers and adders for implementation of linear-phase FIR filters using frequency-response masking techniques are introduced. The basic idea of the proposed structures is that identical subfilters are used. This leads to the same arithmetic structure can be multiplexed in the implementation, reducing the number of required multipliers and adders. The subfilters are mapped using the folding transformation to obtain an area-efficient time-multiplexed (or pipeline/interleaved) implementation. Both narrow-band and wide-band frequency-response masking as well as arbitrary bandwidth frequency-response masking techniques are considered. The filter design is discussed and for each filter structure the limits on the specifications are derived. Designed examples show the usefulness of the proposed structures.

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7

Singh, Gurpadam, and Neelam R. Prakash. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (August 1, 2017): 1874. http://dx.doi.org/10.11591/ijece.v7i4.pp1874-1881.

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.

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8

Jiang, Lei, Haijian Zhang, Shuai Cheng, Hengwei Lv, and Pandong Li. "An Overview of FIR Filter Design in Future Multicarrier Communication Systems." Electronics 9, no. 4 (March 31, 2020): 599. http://dx.doi.org/10.3390/electronics9040599.

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Future wireless communication systems are facing with many challenges due to their complexity and diversification. Orthogonal frequency division multiplexing (OFDM) in 4G cannot meet the requirements in future scenarios, thus alternative multicarrier modulation (MCM) candidates for future physical layer have been extensively studied in the academic field, for example, filter bank multicarrier (FBMC), generalized frequency division multiplexing (GFDM), universal filtered multicarrier (UFMC), filtered OFDM (F-OFDM), and so forth, wherein the prototype filter design is an essential component based on which the synthesis and analysis filters are derived. This paper presents a comprehensive survey on the recent advances of finite impulse response (FIR) filter design methods in MCM based communication systems. Firstly, the fundamental aspects are examined, including the introduction of existing waveform candidates and the principle of FIR filter design. Then the methods of FIR filter design are summarized in details and we focus on the following three categories—frequency sampling methods, windowing based methods and optimization based methods. Finally, the performances of various FIR design methods are evaluated and quantified by power spectral density (PSD) and bit error rate (BER), and different MCM schemes as well as their potential prototype filters are discussed.

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Shaik, Samdhani, and P. Balanagu. "Functional Verification Architecture Implementation for Power Optimized FIR Filter." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.

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Digital-filters are having universal for audio applications. So that, great digital-filter execution ought to be taken as an imperative for outline of audio system Applications. The utilization of accuracy with limited in Digital filters for speaking to signals which likewise contrast from that of simple filters as computerized filters utilizing a limited exactness number juggling for registering the filter reaction. Here, FIR-filter has been actualized in Xilinx ISE utilizing VERILOG dialect. VERILOG coding for FIR-filter has been actualized here too waveforms are additionally seen in the reproduction.Viper comprises of less weight as contrasted and multipliers as far as silicon territory and this plays a profitable in FIR structure. This paper has picked multipliers as stall and Wallace and the taken the adders as convey spare and convey skip. In this paper it needs to build up a RTL in the purpose of structures and check the usefulness of structures contrasted and playing out the union utilizing Xilinx synthesizer. The outcomes were thought about regarding region (LUT'S), power, deferral and memory for different fir structures.

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Mewada, Hiren K., and Jitendra Chaudhari. "Low computation digital down converter using polyphase IIR filter." Circuit World 45, no. 3 (August 5, 2019): 169–78. http://dx.doi.org/10.1108/cw-02-2019-0015.

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Purpose The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter. Design/methodology/approach Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC. Findings The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption. Originality/value The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

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Chen, Jing, Chang Yin Liu, and Xue Ping Li. "The Design and FPGA Implementation of a Polyphase SRRC FIR Filter in DTMB." Advanced Materials Research 791-793 (September 2013): 2122–26. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.2122.

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Polyphase FIR filters are applied in many practical Digital Signal Processing applications where the sampling rate needs to be changed. This paper focuses on the implementation of polyphase square root raised cosine (SRRC) FIR filter based on Field Programmable Gate Array (FPGA). The filter employs methods like filter's multiphase structure, symmetrical coefficients, I/Q channel multiplexing, pipeline addition and so on to design the SRRC filter. Compared with the traditional method, the designed FIR filter exhibits the advantages of high response speed and low hardware resource s consumption.

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Pachauri, Rahul, Rajiv Saxena, and Sanjeev N. Sharma. "Studies on Z-Window Based FIR Filters." ISRN Signal Processing 2013 (September 1, 2013): 1–8. http://dx.doi.org/10.1155/2013/148646.

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As per classification of the window functions, the Z-windows are grouped in the category of steerable side-lobe dip (SSLD) windows. In this work, the application of these windows for the design of FIR filters with improved filter parameters has been explored. The numbers of dips with their respective positions in the side-lobe region have been compositely used to tailor the window shape. Filter design relationships have been established and included in this paper. Simultaneously, an application of these Z-window based FIR filters in designing two-channel quadrature mirror filter (QMF) bank has been presented. Better values of reconstruction and aliasing errors have been achieved in contrast to the Kaiser window based QMF bank.

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13

Wang, Wei. "Implemention of FIR Filter Based on DSP." Applied Mechanics and Materials 214 (November 2012): 717–20. http://dx.doi.org/10.4028/www.scientific.net/amm.214.717.

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DSP chip is especially fit for digital signal processing. Its main application is realizing all kinds of digital signal processing arithmetic such as clove hitch correlation, all kinds of transforms etc. Realizing digital filters with DSP is an important application. The paper discusses the filter’s software realization based on TMS320C5410 and finished the hardware systems of noise-restraining.The main works accomplished are as following: realization of FIR filter with window function, and realization on TMS320C5410 chip, the result of experiment to make clear.

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Marchon, Niyan, and Gourish Naik. "Linear phase FIR filter to compute fetal heart rate variability." International Journal of Engineering & Technology 7, no. 4.5 (September 22, 2018): 492. http://dx.doi.org/10.14419/ijet.v7i4.5.21141.

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Continuous monitoring of fetal heart rate (FHR) can detect the well-being of the fetus and thus indicates non-reassuring fetal status. In- vasive fetal electrocardiography (FECG) using the fetal scalp electrode applied to the fetus scalp allows accurate detection of fetal QRS (FQRS) complexes, however with a risk of infection to the fetus. We have proposed a non-invasive fetal heart rate (NIFHR) filtering technique employing finite impulse response (FIR) filters. We applied Fast Fourier Transform (FFT) to the Physionet abdominal ECG (aECG) records and derived the fiduciary edges of the spectrum of the FECG. A FIR band pass filter (BPF) is designed which is a com- posite filter consisting of a high pass filter (HPF) followed by a low pass filter (LPF) in that order. The cut off frequencies of these com- posite filters are the fiduciary edges of the fetal electrocardiography spectrum. A FQRS detector to obtain fetal heart rate variability (FHRV) processes the FQRS signal filtered through these composite FIR filters. It is observed that channel 4 from records r01 and r08 obtained 100% results for sensitivity, positive predictive value and accuracy while, the overall accuracy was 92.21%. This design can also be extended to compute maternal heart rate.

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RAMÍREZ, JAVIER, UWE MEYER-BÄSE, and ANTONIO GARCÍA. "EFFICIENT RNS-BASED DESIGN OF PROGRAMMABLE FIR FILTERS TARGETING FPL TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 01 (February 2005): 165–77. http://dx.doi.org/10.1142/s0218126605002131.

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FIR filters are routinely used in the implementation of modern digital signal processing systems. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the residue number system (RNS) implementation of reduced-complexity and high-performance FIR filters, using modern Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields and the Quadratic Residue Number System (QRNS), along with a selection of a small wordwidth modulus set, are the keys for attaining low complexity and high throughput in real and complex FIR filters. RNS–FPL merged FIR filters demonstrated its superiority when compared to 2C (two's complement) filters, being about 65% faster and requiring fewer logic elements for most study cases. Special attention was paid to an efficient implementation of the multi-operand modulo adders. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage reduced area requirements by 10% for a 32-tap FIR filter. On the other hand, an index arithmetic QRNS-based complex FIR filter yielded up to 60% performance improvement over a three-multiplier-per-tap 2C filter, while requiring fewer LEs for filters having more than eight taps. Particularly, a 32-tap filter needed 24% LEs less than the classical design.

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SARAMÄKI, TAPIO, JUHA YLI-KAAKINEN, and HÅKAN JOHANSSON. "OPTIMIZATION OF FREQUENCY-RESPONSE MASKING BASED FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (October 2003): 563–91. http://dx.doi.org/10.1142/s0218126603001070.

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A very efficient technique to drastically reduce the number of multipliers and adders in implementing linear-phase finite-impulse response (FIR) digital filters in applications demanding a narrow transition band is to use the frequency-response masking (FRM) approach originally introduced by Lim. The arithmetic complexity can be even further reduced using a common filter part for constructing the masking filters originally proposed by Lim and Lian. A drawback in the above-mentioned original FRM synthesis techniques is that the subfilters in the overall implementations are separately designed. In order to further reduce the arithmetic complexity in these two FRM approaches, the following two-step optimization technique is proposed for simultaneously optimizing the subfilters. At the first step, a good suboptimal solution is found by using a simple iterative algorithm. At the second step, this solution is then used as a start-up solution for further optimization being carried out by using an efficient unconstrained nonlinear optimization algorithm. An example taken from the literature illustrates that both the number of multipliers and the number of adders for the resulting optimized filter are less than 80% compared with those of the FRM filter obtained using the original FRM design schemes in the case where the masking filters are separately implemented. If a common filter part is used for realizing the masking filters, then an additional reduction of more than 10% is achieved compared with the optimized design with separately implemented masking filters.

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Williamson, D., K. L. Teo, and P. C. Musumeci. "Optimum FIR array filters." IEEE Transactions on Acoustics, Speech, and Signal Processing 36, no. 8 (1988): 1211–22. http://dx.doi.org/10.1109/29.1650.

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18

Heinonen, P., and Y. Neuvo. "FIR-median hybrid filters." IEEE Transactions on Acoustics, Speech, and Signal Processing 35, no. 6 (June 1987): 832–38. http://dx.doi.org/10.1109/tassp.1987.1165198.

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Pang, D., L. A. Ferrari, and P. V. Sankar. "B-spline FIR filters." Circuits Systems and Signal Processing 13, no. 1 (March 1994): 31–64. http://dx.doi.org/10.1007/bf01183840.

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Chung, Daewon, Woon Cho, Inyeob Jeong, and Joonhyeon Jeon. "Design of Cut Off-Frequency Fixing Filters by Error Compensation of MAXFLAT FIR Filters." Electronics 10, no. 5 (February 26, 2021): 553. http://dx.doi.org/10.3390/electronics10050553.

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Maximally-flat (MAXFLAT) finite impulse response (FIR) filters often face a problem of the cutoff-frequency error due to approximation of the desired frequency response by some closed-form solution. So far, there have been plenty of efforts to design such a filter with an arbitrarily specified cut off-frequency, but this filter type requires extensive computation and is not MAXFLAT anymore. Thus, a computationally efficient and effective design is needed for highly accurate filters with desired frequency characteristics. This paper describes a new method for designing cutoff-frequency-fixing FIR filters through the cutoff-frequency error compensation of MAXFLAT FIR filters. The proposed method provides a closed-form Chebyshev polynomial containing a cutoff-error compensation function, which can characterize the “cutoff-error-free” filters in terms of the degree of flatness for a given order of filter and cut off-frequency. This method also allows a computationally efficient and accurate formula to directly determine the degree of flatness, so that this filter type has a flat magnitude characteristic both in the passband and the stopband. The remarkable effectiveness of the proposed method in design efficiency and accuracy is clearly demonstrated through various examples, indicating that the cutoff-fixing filters exhibit amplitude distortion error of less than 10−14 and no cut off-frequency error. This new approach is shown to provide significant advantages over the previous works in design flexibility and accuracy.

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Kumar, Susheel, Munish Verma, Vijay K. Lamba, Avinash Kumar, and Sandeep Kumar. "COMPARATIVE ANALYSIS OF EXPONENTIAL WINDOW FUNCTION FOR DESIGNING OF FIR FILTERS." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 3, no. 2 (October 30, 2012): 329–34. http://dx.doi.org/10.24297/ijct.v3i2c.2895.

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Filters are very commonly found in everyday life and include examples such as water filters for water purification, mosquito nets that filter out bugs, bouncers at bars filtering the incoming guests according to age (and other criteria), and air filters found in air conditioners that we are sometimes a bit too lazy to change/clean periodically. Filters have two uses: signal separation and signal restoration. Signal separation is needed when a signal has been contaminated with interference, noise, or other signals. For example, imagine a device for measuring the electrical activity of a baby's heart (EKG) while still in the womb. The raw signal will likely be corrupted by the breathing and heartbeat of the mother. A filter might be used to separate these signals so that they can be individually analyzed. Signal restoration is used when a signal has been distorted in some way. For example, an audio recording made with poor equipment may be filtered to better represent the sound as it actually occurred [1, 2]. The main goal of this work is to study the exponential Â window function and analyze a digital low pass FIR filter using the same in MATLAB. Properties of window functions is studied and frequeny domain responses ofÂ window functions is obtained. Then FIR filter is designed using widow design method and its characteristics have also been studied in frequency domain. The performace comparison between LPFs designed using other well known windows like Kaiser, Exponential, Cosh and modified kaiser window is done and it has been intuitively shown that for a given order and transition width, the filter designed using Exponential window provides the worse minimum stop band attenuation but better far end attenuation than filter designed by well known Kaiser Window.

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Xu, Wei, Anyu Li, Boya Shi, and Jiaxiang Zhao. "A Novel Design of Sparse FIR Multiple Notch Filters with Tunable Notch Frequencies." Mathematical Problems in Engineering 2018 (2018): 1–7. http://dx.doi.org/10.1155/2018/3490830.

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We focus on the design of finite impulse response (FIR) multiple notch filters. To reduce the computational complexity and hardware implementation complexity, a novel algorithm is developed based on the mixture of the tuning of notch frequencies and the sparsity of filter coefficients. The proposed design procedure can be carried out as follow: first, since sparse FIR filters have lower implementation complexity than full filters, a sparse linear phase FIR single notch filter with the given rejection bandwidth and passband attenuation is designed. Second, a tuning procedure is applied to the computed sparse filter to produce the desired sparse linear phase FIR multiple notch filter. When the notch frequencies are varied, the same tuning procedure can be employed to render the new multiple notch filter instead of designing the filter from scratch. The effectiveness of the proposed algorithm is demonstrated through three design examples.

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LIAN, YONG. "A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (October 2003): 643–54. http://dx.doi.org/10.1142/s0218126603001069.

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This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.

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Konopacki, J., and K. Mościńska. "Estimation of filter order for prescribed, reduced group delay FIR filter design." Bulletin of the Polish Academy of Sciences Technical Sciences 63, no. 1 (March 1, 2015): 209–16. http://dx.doi.org/10.1515/bpasts-2015-0024.

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Abstract FIR filters are often applied, as they possess many advantages, including linear-phase response and well elaborated design methods. However, group delay introduced by FIR filters is usually large. The reduction of group delay can be obtained by restriction of the linear phase requirement only to the passband. One of the problems that appear while designing FIR filters with a prescribed value of group delay is the choice of the filter order. In the paper a formula for filter order calculation for the given filter parameters and dedicated for equiripple or quasi-equiripple approximation of the magnitude response has been derived based on experiments. Numerous examples that explain how to use the derived formula have been included.

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Kocoń, Sławomir, and Jacek Piskorowski. "Digital Finite Impulse Response Notch Filter with Non-Zero Initial Conditions, Based on an Infinite Impulse Response Prototype Filter." Metrology and Measurement Systems 19, no. 4 (December 1, 2012): 767–76. http://dx.doi.org/10.2478/v10178-012-0068-x.

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Abstract In this paper a concept of finite impulse response (FIR) narrow band-stop (notch) filter with non-zero initial conditions, based on infinite impulse response (IIR) prototype filter, is proposed. The filter described in this paper is used to suppress power line noise from ECG signals. In order to reduce the transient response of the proposed FIR notch filter, optimal initial conditions for the filter have been determined. The algorithm for finding the length of the initial conditions vector is presented. The proposed values of the length of initial conditions vector, for several ECG signals and interfering frequencies, are calculated. The proposed filters are tested using various ECG signals. Computer simulations demonstrate that the proposed FIR filters outperform traditional FIR filters with initial conditions set to zero.

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Blok, Marek. "FIR Filter Design Using Distributed Maximal Flatness Method." International Journal of Electronics and Telecommunications 59, no. 1 (March 1, 2013): 59–66. http://dx.doi.org/10.2478/eletel-2013-0007.

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Abstract In the paper a novel method for filter design based on the distributed maximal flatness method is presented. The proposed approach is based on the method used to design the most common FIR fractional delay filter - the maximally flat filter. The MF filter demonstrates excellent performance but only in a relatively narrow frequency range around zero frequency but its magnitude response is no greater than one. This ,,passiveness” is the reason why despite of its narrow band of accurate approximation, the maximally flat filter is widely used in applications in which the adjustable delay is required in feedback loop. In the proposed method the maximal flatness conditions forced in standard approach at zero frequency are spread over the desired band of interest. In the result FIR filters are designed with width of the approximation band adjusted according to needs of the designer. Moreover a weighting function can be applied to the error function allowing for designs differing in error characteristics. Apart from the design of fractional delay filters the method is presented on the example of differentiator, raised cosine and square root raised cosine FIR filters. Additionally, the proposed method can be readily adapted for variable fractional delay filter design regardless of the filter type.

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NERURKAR, SHAILESH B., and KHALID H. ABED. "LOW POWER DIGITAL DECIMATION FILTER FOR RF WIRELESS COMMUNICATIONS." Journal of Circuits, Systems and Computers 17, no. 02 (April 2008): 239–51. http://dx.doi.org/10.1142/s0218126608004241.

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In this paper, we present a unique low power decimation filter architecture for RF wireless applications. To implement the low power decimation filter, we considered low power design techniques such as multi-rate, multi-stage signal processing, proper selection of decimation factor, one multiplier realization of 1/3-band filters, and poly-phase 1/2-band filters. We have designed three conventional decimation filter architectures using a single-stage FIR filter, a three-stage FIR filter, and a three-stage half-band FIR filter. Compared to the 55-tap comb-FIR filter architecture, the proposed decimation filter has only 13 taps, and requires 76% less hardware and consumes 64% less power.

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Ye, Wenbin, and Ya Jun Yu. "Power Oriented Design of Linear Phase FIR Filters." Journal of Circuits, Systems and Computers 25, no. 07 (April 22, 2016): 1650075. http://dx.doi.org/10.1142/s0218126616500754.

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In the design of low computational complexity and low power FIR filters, researchers have made every effort to reduce the number of adders when coefficients multipliers are considered as the multiple constant multiplication problem. In this paper, for the first time, we propose a power oriented optimization of linear phase FIR filters, where a power cost is used as the criteria in the discrete coefficient searches and synthesis. The power cost is computed based on a newly proposed power model, which takes both the static power and dynamic power into consideration. With the new power model, a new coefficient synthesis scheme is proposed such that the synthesized coefficient consumes the minimum power. Compared to the adder-cost oriented algorithm, the proposed power-oriented algorithm has two advantages: First, the algorithm can optimize filters with lower power consumption, and second, the optimal design in the sense of power consumption is frequency aware. Unlike the adder-cost oriented algorithms that generate the same final coefficient set and the same synthesis of the coefficient set regardless of the frequency for a given filter specification, the proposed algorithm search and synthesizes the coefficients with the awareness of the working frequency; different designs may be resulted for the same filter specification but different working frequency, and each designed filter has lower power consumption in its specified frequency. Transistor level simulations of benchmark filters verified the above claims.

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29

Heinonen, P., and Y. Neuvo. "FIR-median hybrid filters with predictive FIR substructures." IEEE Transactions on Acoustics, Speech, and Signal Processing 36, no. 6 (June 1988): 892–99. http://dx.doi.org/10.1109/29.1600.

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RAMACHANDRAN, V., and V. NINOV. "2D ZERO-PHASE FIR FILTER DESIGN WITH NONUNIFORM FREQUENCY SAMPLING." Journal of Circuits, Systems and Computers 10, no. 05n06 (October 2000): 239–77. http://dx.doi.org/10.1142/s0218126600000172.

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In this paper, nonuniform frequency sampling techniques used in the design of two-dimensional zero-phase FIR filters are proposed and investigated. The design problem is treated as a bivariate interpolation problem with unevenly spaced data. The main idea is to select (find) sampling locations in the (ω1, ω2) frequency plane and corresponding sample values Hd(ω1k, ω2k) of the desired filter frequency response such that the designed filter performance is high. Although the filters designed with the proposed techniques are not optimal, the methods are conceptually simple and produce filters with high degree of shape regularity and approximation error comparable and sometimes even smaller than the "conventional" 2D FIR filter design methods.

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31

Petraglia, M. R., and S. K. Mitra. "Adaptive FIR filter structure based on the generalized subband decomposition of FIR filters." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 40, no. 6 (June 1993): 354–62. http://dx.doi.org/10.1109/82.277880.

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32

Fan, Xuefeng, and Fei Liu. "State Fusion of Decentralized Optimal Unbiased FIR Filters." Journal of Electrical and Computer Engineering 2018 (June 3, 2018): 1–11. http://dx.doi.org/10.1155/2018/1505137.

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The paper presents a decentralized fusion strategy based on the optimal unbiased finite impulse response (OUFIR) filter for discrete systems with correlated process and measurement noise. We extend OUFIR filter to apply in the model with control inputs. Taking it as local filters, cross covariance between any two is calculated; then it is expressed to the fast iterative form. Finally based on cross covariance, optimal weights are utilized to fuse local estimates and the overall outcome is obtained. The numerical examples show that the proposed filter exhibits better robustness against temporary modeling uncertainties than the fusion Kalman filter used commonly.

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Fan, Xuefeng, Shunyi Zhao, and Yuriy S. Shmaiy. "Linear Optimal Fusion of Local Unbiased FIR Filters." MATEC Web of Conferences 210 (2018): 05004. http://dx.doi.org/10.1051/matecconf/201821005004.

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This paper presents a multi-sensor decentralized fusion unbiased finite impulse response (UFIR) filter for discrete time-invariant state-space models. Fusion is provided in the minimum variance sense. By calculating the cross covariance between any of two local filters for the extended state-space model, linear optimal weights are derived to fuse local UFIR estimates. Simulation conduced for a two-state polynomial model shows that the proposed fusion UFIR filter has higher robustness than the fusion Kalman filter against errors in the noise statistics and temporary model uncertainties.

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Grati, Khaled, Nadia Khouja, Bertrand Le Gal, and Adel Ghazel. "Power Consumption Models for Decimation FIR Filters in Multistandard Receivers." VLSI Design 2012 (May 27, 2012): 1–15. http://dx.doi.org/10.1155/2012/870546.

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Decimation filters are widely used in communication-embedded systems. In fact, decimation filters are useful for implementing channel filtering or selection with low-computation complexity requirements. Many multistandard receiver designs that are required in ubiquitous embedded systems are based on a cascade of decimation filter processing. Filter number and implementation architectures have a significant impact on system performances, such as computation complexity, area, throughput, and power consumption. In this work, we present filter power consumption estimation models for FIR filters. Power consumption models were obtained from a large number of FIR filter syntheses using a direct form. Several curves that estimate power consumption were extracted from these synthesis results. Then, we have evaluated the impact of polyphase decomposition on power consumption of FIR filter and compared it with the direct form results. Some tips regarding power consumption were deduced for the polyphase implementation form. The aim of this work is to help a system designer to select an efficient implementation for FIR in terms of power consumption without having to implement and synthesize the different possible solutions. The proposed method is applied for STMicroelectronics libraries 90 nm and 65 nm low power then validated with a use case of multistandard receiver designing.

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35

Petrovic, Predrag. "Possible solution of parallel FIR filter structure." Serbian Journal of Electrical Engineering 2, no. 1 (2005): 21–28. http://dx.doi.org/10.2298/sjee0501021p.

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In this paper, a parallel form FIR adaptive filter structure with RLS (Recursive Least Squares) type adaptive algorithm is proposed. The proposed parallel form FIR structure consists of a recursive orthogonal transform stage and sparse FIR sub filters operating in parallel. The adaptive algorithm used to update coefficient vector of the sparse filters is implemented by using modified Hopfield networks. This structure implements the RLS-type adaptive algorithm, without an explicit matrix inversion avoiding numerical instability problems. Simulation results which show the desirable features of proposed structure are given.

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Duda, Krzysztof, and Tomasz P. Zieliński. "Fir Filters Compliant with the IEEE Standard for M Class PMU." Metrology and Measurement Systems 23, no. 4 (December 1, 2016): 623–36. http://dx.doi.org/10.1515/mms-2016-0055.

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Abstract In this paper it is shown that M class PMU (Phasor Measurement Unit) reference model for phasor estimation recommended by the IEEE Standard C37.118.1 with the Amendment 1 is not compliant with the Standard. The reference filter preserves only the limits for TVE (total vector error), and exceeds FE (frequency error) and RFE (rate of frequency error) limits. As a remedy we propose new filters for phasor estimation for M class PMU that are fully compliant with the Standard requirements. The proposed filters are designed: 1) by the window method; 2) as flat-top windows; or as 3) optimal min-max filters. The results for all Standard compliance tests are presented, confirming good performance of the proposed filters. The proposed filters are fixed at the nominal frequency, i.e. frequency tracking and adaptive filter tuning are not required, therefore they are well suited for application in lowcost popular PMUs.

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U.Bilgunde, P., S. K. Sudhansu, and S. M Jagde. "Reducing Complexity of FIR Filters using Narrowband Filters." International Journal of Computer Applications 88, no. 3 (February 14, 2014): 12–16. http://dx.doi.org/10.5120/15331-3655.

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38

Balster, Eric J., Francis D. Fradette, Frank A. Scarpino, and Kerry L. Hill. "Time-Domain Matrix Analysis of Polyphase FIR Filters." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 275–90. http://dx.doi.org/10.7227/ijeee.49.3.7.

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Polyphase filter design is a common subject studied in discrete systems analysis and digital signal processing (DSP) courses. However, the classic z-domain analysis, utilizing the noble identities, gives a conclusion to the true physical structures of polyphase filters which may not be obvious to many students. The proposed time-domain analysis provides a more straightforward development of polyphase implementation of interpolation and decimation functions, and hopes to provide students with a more visual representation of the polyphase interpolation and decimation processes. Results from a student survey show that over 73% of students believe that the proposed polyphase analysis strengthened their understanding of polyphase filters, and over 71% would prefer to use the proposed method over the traditional z-domain analysis when explaining polyphase filters to others.

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39

Aparna, A., and T. Vigneswaran. "DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (April 1, 2017): 66. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19564.

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This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications.

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40

Acha, JoséI, and Rubén Martín-Clemente. "Design of log FIR filters." Signal Processing 62, no. 2 (October 1997): 243–46. http://dx.doi.org/10.1016/s0165-1684(97)00167-9.

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41

Mehrnia, Alireza, and Alan N. Willson. "Further Desensitized FIR Halfband Filters." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 7 (July 2015): 1815–24. http://dx.doi.org/10.1109/tcsi.2015.2423773.

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42

Litwin, L. "FIR and IIR digital filters." IEEE Potentials 19, no. 4 (2000): 28–31. http://dx.doi.org/10.1109/45.877863.

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43

Lyons, R. "Interpolated narrowband lowpass FIR filters." IEEE Signal Processing Magazine 20, no. 1 (January 2003): 50–57. http://dx.doi.org/10.1109/msp.2003.1166628.

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44

Mehrnia, Alireza, and Alan N. Willson. "Optimal Factoring of FIR Filters." IEEE Transactions on Signal Processing 63, no. 3 (February 2015): 647–61. http://dx.doi.org/10.1109/tsp.2014.2379647.

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45

Vlcek, M., P. Zahradnik, and R. Unbehauen. "Analytical design of FIR filters." IEEE Transactions on Signal Processing 48, no. 9 (2000): 2705–9. http://dx.doi.org/10.1109/78.863090.

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46

Vaidyanathan, P. "On power-complementary FIR filters." IEEE Transactions on Circuits and Systems 32, no. 12 (December 1985): 1308–10. http://dx.doi.org/10.1109/tcs.1985.1085656.

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47

Vainio, O., and Y. Neuvo. "Logarithmic arithmetic in FIR filters." IEEE Transactions on Circuits and Systems 33, no. 8 (August 1986): 826–28. http://dx.doi.org/10.1109/tcs.1986.1085992.

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48

Lim, Y. C., and B. Liu. "Extrapolated impulse response FIR filters." IEEE Transactions on Circuits and Systems 37, no. 12 (1990): 1548–51. http://dx.doi.org/10.1109/31.101276.

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49

Manduchi, R., and P. Perona. "Least-squares multirate FIR filters." Electronics Letters 32, no. 8 (1996): 726. http://dx.doi.org/10.1049/el:19960483.

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50

Mismar, M. J., and I. H. Zabalawi. "Complex coefficient fir digital filters." Circuits, Systems, and Signal Processing 13, no. 5 (September 1994): 591–600. http://dx.doi.org/10.1007/bf02523185.

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