Relevant bibliographies by topics / Five-transistor

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Five-transistor'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Five-transistor.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Five-transistor"

1

Serrano-Gotarredona, T., and B. Linares-Barranco. "A new five-parameter MOS transistor mismatch model." IEEE Electron Device Letters 21, no. 1 (January 2000): 37–39. http://dx.doi.org/10.1109/55.817445.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Benyettou, L., T. Benslimane, O. Abdelkhalek, T. Abdelkrim, and K. Bentata. "Faults Diagnosis in Five-Level Three-Phase Shunt Active Power Filter." International Journal of Power Electronics and Drive Systems (IJPEDS) 6, no. 3 (September 1, 2015): 576. http://dx.doi.org/10.11591/ijpeds.v6.i3.pp576-585.

Full text
Abstract:
In this paper, characteristics of open transistor faults in cascaded H-bridge five-level three-phase PWM controlled shunt active power filter are determined. Phase currents can’t be trusted as fault indicator since their waveforms are slightly changed in the presence of open transistor fault. The proposed method uses H bridges output voltages to determine the faulty phase, the faulty bridge and more precisely, the open fault transistor.
APA, Harvard, Vancouver, ISO, and other styles
3

Krammer, Markus, James Borchert, Andreas Petritz, Esther Karner-Petritz, Gerburg Schider, Barbara Stadlober, Hagen Klauk, and Karin Zojer. "Critical Evaluation of Organic Thin-Film Transistor Models." Crystals 9, no. 2 (February 6, 2019): 85. http://dx.doi.org/10.3390/cryst9020085.

Full text
Abstract:
The thin-film transistor (TFT) is a popular tool for determining the charge-carrier mobility in semiconductors, as the mobility (and other transistor parameters, such as the contact resistances) can be conveniently extracted from its measured current-voltage characteristics. However, the accuracy of the extracted parameters is quite limited, because their values depend on the extraction technique and on the validity of the underlying transistor model. We propose here a new approach for validating to what extent a chosen transistor model is able to predict correctly the transistor operation. In the two-step fitting approach we have developed, we analyze the measured current-voltage characteristics of a series of TFTs with different channel lengths. In the first step, the transistor parameters are extracted from each individual transistor by fitting the output and transfer characteristics to the transistor model. In the second step, we check whether the channel-length dependence of the extracted parameters is consistent with the underlying model. We present results obtained from organic TFTs fabricated in two different laboratories using two different device architectures, three different organic semiconductors and five different materials combinations for the source and drain contacts. For each set of TFTs, our approach reveals that the state-of-the-art transistor models fail to reproduce correctly the channel-length-dependence of the transistor parameters. Our approach suggests that conventional transistor models require improvements in terms of the charge-carrier-density dependence of the mobility and/or in terms of the consideration of uncompensated charges in the carrier-accumulation channel.
APA, Harvard, Vancouver, ISO, and other styles
4

Mrvić, Jovan, and Vladimir Vukić. "Comparative analysis of the switching energy losses in GaN HEMT and silicon MOSFET power transistors." Zbornik radova Elektrotehnicki institut Nikola Tesla 30, no. 30 (2020): 93–109. http://dx.doi.org/10.5937/zeint30-29318.

Full text
Abstract:
The subject of this paper is the mutual comparison of switching energy losses in cascode gallium nitride HEMT and silicon "superjunction" MOSFET transistor, both designed for a maximum operating voltage of 650 V. For the purpose of analysis the transistor switching characteristics, the double pulse test method was implemented. Detailed computer simulation models developed in programs of the SPICE family were used. Data on transient turn -on and turn-off processes were generated by LTspice simulation tool, in a wide range of drain currents, using two different gate resistance values for driving the transistors under test. The obtained results indicate superior switching characteristics of gallium nitride devices in comparison to silicon components, especially during the high drain current transistor operation. During the one transistor switching cycle, the total energy losses in the GaN HEMT were simulated, for a drain current of 30 A, and found to be five to eight times lower when compared to tested Si MOSFET transistor.
APA, Harvard, Vancouver, ISO, and other styles
5

Yu, Chien-Cheng, and Ming-Chuen Shiau. "Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby." International Journal of VLSI Design & Communication Systems 7, no. 4 (August 30, 2016): 01–11. http://dx.doi.org/10.5121/vlsic.2016.7401.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Nakaya, Yusuke, Tetsuo Nishi, Shin’ichi Oishi, and Martin Claus. "Numerical existence proof of five solutions for certain two-transistor circuit equations." Japan Journal of Industrial and Applied Mathematics 26, no. 2-3 (October 2009): 327–36. http://dx.doi.org/10.1007/bf03186538.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Lagunovich, N. L. "Optimization of guard rings construction and epitaxial film resistivity of power n-channel DMOS-transistor." Proceedings of the National Academy of Sciences of Belarus, Physical-Technical Series 65, no. 1 (April 6, 2020): 97–103. http://dx.doi.org/10.29235/1561-8358-2020-65-1-97-103.

Full text
Abstract:
Powerful n-channel DMOS-transistor with drain-source breakdown voltage Uds br value over 800 V and thresh-old voltage from 2 to 5 V was considered in this paper. One or more guard rings are formed on perimeter of such transistor for the breakdown voltage raising. The optimal guard rings construction was described and resistivity value of epitaxial film ρv was determined for obtaining required transistor Uds br value. The regression model was built, with the help of which the most optimal construction variants of guard rings of investigated transistor and resistivity value of epitaxial film, were selected. It was established that the five-dimensional polynomial of second order using as regression model allowed choosing the optimal topological spaces values in the guard rings area and ρv value which made it possible to obtain required Uds br values of the transistor. Experimental values of transistor drain-source breakdown voltage were 876 and 875 V, but calculated values (at identical parameters of definitional regression model) were 874 and 880 V, accordingly, that were errors of 0.23 % and 0.57 %, i. e. made model fits well with experimental data. It was established that ρv makes contribution to breakdown voltages values of the transistor that is more substantial than parameters of guard rings construction. This NDMOS-transistor was manufactured under production conditions of OJSC INTEGRAL” – “INTEGRAL” Holding Managing Company according to the technological route developed by the author. Such device is used in various electronic devices for energetics, in mobile phones, as part of high-voltage integrated circuits of AC/DC- and DC/DC-converters and high-voltage, high-stable LED-drivers.
APA, Harvard, Vancouver, ISO, and other styles
8

Satputaley, R. J., V. B. Borghate, Vinod Kumar, and Trinath Kumar. "Experimental investigation of new three phase five level transistor clamped H-bridge inverter." EPE Journal 27, no. 1 (January 2, 2017): 12–23. http://dx.doi.org/10.1080/09398368.2017.1299505.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Wang, Hui, and Patrick P. Mercier. "A 3.4-pW 0.4-V 469.3 ppm/°C Five-Transistor Current Reference Generator." IEEE Solid-State Circuits Letters 1, no. 5 (May 2018): 122–25. http://dx.doi.org/10.1109/lssc.2018.2875825.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.

Full text
Abstract:
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Five-transistor"

1

Carlson, Ingvar. "Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2286.

Full text
Abstract:

This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre.

APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Five-transistor"

1

Kiranmayee, V., and A. Sharath Kumar. "Performance Evaluation of Transistor Clamped H-Bridge (TCHB)-Based Five-Level Inverter." In Lecture Notes in Electrical Engineering, 161–72. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2256-7_16.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Five-transistor"

1

Liu, Wei, Dong-xing Wang, Bin An, Lei Wang, Jing-hua Yin, and Hong Zhao. "The five-layer Laminated Structure Organic Transistor Sensor Preparation and Characteristics Analysis." In International Conference on Interdisciplinary Research Theory and Technology. Science & Engineering Research Support soCiety, 2013. http://dx.doi.org/10.14257/astl.2013.29.98.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Choudhary, Rahul, and Indrajit Sarkar. "Single phase five level Transistor Clamped inverter with multi-band hysteresis current control." In 2016 IEEE 6th International Conference on Power Systems (ICPS). IEEE, 2016. http://dx.doi.org/10.1109/icpes.2016.7584043.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Yu, Chien-Cheng, Chung-Bin Wu, and Ming-Chuen Shiau. "A New Single-Port Five-Transistor SRAM Cell Design for Signal Processing Systems." In 2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2019. http://dx.doi.org/10.1109/icicm48536.2019.8977159.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Mukherjee, Biswarup, Biplab Roy, Arindam Biswas, and Aniruddha Ghosal. "Design of a low power 4×4 multiplier based on five transistor (5-T) half adder, eight transistor (8-T) full adder & two transistor (2-T) AND gate." In 2015 3rd International Conference on Computer, Communication, Control and Information Technology (C3IT). IEEE, 2015. http://dx.doi.org/10.1109/c3it.2015.7060143.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Bhaskar, Mahajan Sagar, Sanjeevikumar Padmanaban, Viliam Fedak, Frede Blaabjerg, and Patrick Wheeler. "Transistor Clamped Five-Level Inverter using Non-Inverting Double Reference Single Carrier PWM Technique for photovoltaic applications." In 2017 International Conference on Optimization of Electrical and Electronic Equipment (OPTIM) & 2017 Intl Aegean Conference on Electrical Machines and Power Electronics (ACEMP). IEEE, 2017. http://dx.doi.org/10.1109/optim.2017.7975063.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Huhman, B. M., A. Hathaway, and H. B. Ma. "Evaluation of the Integration of Oscillating Heat Pipes in High Power DC-DC Converters for Pulsed Power Applications." In ASME 2013 Heat Transfer Summer Conference collocated with the ASME 2013 7th International Conference on Energy Sustainability and the ASME 2013 11th International Conference on Fuel Cell Science, Engineering and Technology. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/ht2013-17173.

Full text
Abstract:
The Pulsed Power Physics Branch at the U.S. Naval Research Laboratory (NRL) is developing a battery-powered, rep-rate charger for a 60-kJ capacitor bank. The goal is to charge a 4800μF capacitor to 5kV in five seconds for a fifty shot burst. A bank of LiFePO4 batteries is used with a full H-bridge converter and transformer to elevate the 500V battery voltage to a 5kV secondary voltage. The operation of the Integrated Gate Bipolar Transistor (IGBT) generates heat as a byproduct of the energy transfer from the batteries to the capacitor, which must be effectively removed. The traditional method of cooling the IGBTs involves a passive heat sink and forced air cooling, which can be quite large if the dissipated power load is high enough. This work investigates the replacement of the forced air cooling method with an oscillating heat pipe (OHP). The OHP investigated herein was made of aluminum with dimensions of 130.1 mm × 101.9 mm × 2.5 mm. The OHP channel dimension imbedded in the aluminum block is 1.0 mm by 1.0 mm. Utilizing high effective thermal conductivity, the integrated OHP has the potential to reduce the overall system volume and enable the design of a sealed converter package. Numerical analysis and experimental results demonstrate that the OHP can significantly increase the effective thermal conductivity and enable a fast time response of the pulsed power DC-DC converter. Comparison with the numerical analysis show that the heat transfer resistance occurring in the cooling block is the primary resistance for the investigated IGBT OHP cooling.
APA, Harvard, Vancouver, ISO, and other styles
7

Romero, David A., Elham Pakseresht, Daniel Sellan, Aydin Nabovati, and Cristina Amon. "A Hierarchical Framework for Thermal Modelling of Electronic Devices: From Atoms to Chips." In ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/ipack2013-73202.

Full text
Abstract:
In this work, we provide an overview of a hierarchical computational framework to predict thermal transport in electronic devices through integration of physics-based models at different length scales. Information from atomistic simulations at the smallest length scales are transferred to upper levels of the hierarchy, up to thermal models for the chip. The proposed methodology includes five levels of length scales in electronic devices, namely (i) atomistic level, (ii) thin film and nanowire level, (iii) transistor and logic gate level, (iv) functional block level, and (v) chip level. At the first level of the hierarchy, properties of energy carriers in a semiconductor material (e.g., phonons) are obtained from atomistic level simulations, such as Molecular Dynamics (MD) and Lattice Dynamics (LD) calculations. At the second level, thermal transport in thin silicon films is modelled using a Lattice Boltzmann Method (LBM) for phonons. The outcome of these simulations is a size-dependent thermal conductivity for silicon films. At the third level of the hierarchy, these effective thermal conductivities are used in thermal modelling of logic gates. Detailed structures of different types of logic gates are reconstructed based on different manufacturing technologies (MOSFET and FinFET) at different technology nodes. Since the characteristic sizes of different parts of the logic gates are comparable to the mean free path of energy carriers, we use the size-dependent, effective thermal conductivities that were calculated at lower levels of the hierarchy to build simulation models for the logic gates. Based on these models, we calculate an equivalent thermal conductance for the logic gates, which would then be used in the upper level simulations to determine an equivalent thermal conductance for different functional blocks of the die based on their internal structure and the number and type of logic gates found in each functional block. Overall, the proposed hierarchical model enables us to include the effect of atomistic-level physics into package-level simulations, and thus, have an accurate prediction of thermal transport in an electronic device.
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Five-transistor' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography