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Journal articles on the topic 'Five-transistor'

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Published: 4 June 2021
Last updated: 12 February 2022

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1

Serrano-Gotarredona, T., and B. Linares-Barranco. "A new five-parameter MOS transistor mismatch model." IEEE Electron Device Letters 21, no. 1 (January 2000): 37–39. http://dx.doi.org/10.1109/55.817445.

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2

Benyettou, L., T. Benslimane, O. Abdelkhalek, T. Abdelkrim, and K. Bentata. "Faults Diagnosis in Five-Level Three-Phase Shunt Active Power Filter." International Journal of Power Electronics and Drive Systems (IJPEDS) 6, no. 3 (September 1, 2015): 576. http://dx.doi.org/10.11591/ijpeds.v6.i3.pp576-585.

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In this paper, characteristics of open transistor faults in cascaded H-bridge five-level three-phase PWM controlled shunt active power filter are determined. Phase currents can’t be trusted as fault indicator since their waveforms are slightly changed in the presence of open transistor fault. The proposed method uses H bridges output voltages to determine the faulty phase, the faulty bridge and more precisely, the open fault transistor.
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3

Krammer, Markus, James Borchert, Andreas Petritz, Esther Karner-Petritz, Gerburg Schider, Barbara Stadlober, Hagen Klauk, and Karin Zojer. "Critical Evaluation of Organic Thin-Film Transistor Models." Crystals 9, no. 2 (February 6, 2019): 85. http://dx.doi.org/10.3390/cryst9020085.

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The thin-film transistor (TFT) is a popular tool for determining the charge-carrier mobility in semiconductors, as the mobility (and other transistor parameters, such as the contact resistances) can be conveniently extracted from its measured current-voltage characteristics. However, the accuracy of the extracted parameters is quite limited, because their values depend on the extraction technique and on the validity of the underlying transistor model. We propose here a new approach for validating to what extent a chosen transistor model is able to predict correctly the transistor operation. In the two-step fitting approach we have developed, we analyze the measured current-voltage characteristics of a series of TFTs with different channel lengths. In the first step, the transistor parameters are extracted from each individual transistor by fitting the output and transfer characteristics to the transistor model. In the second step, we check whether the channel-length dependence of the extracted parameters is consistent with the underlying model. We present results obtained from organic TFTs fabricated in two different laboratories using two different device architectures, three different organic semiconductors and five different materials combinations for the source and drain contacts. For each set of TFTs, our approach reveals that the state-of-the-art transistor models fail to reproduce correctly the channel-length-dependence of the transistor parameters. Our approach suggests that conventional transistor models require improvements in terms of the charge-carrier-density dependence of the mobility and/or in terms of the consideration of uncompensated charges in the carrier-accumulation channel.
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4

Mrvić, Jovan, and Vladimir Vukić. "Comparative analysis of the switching energy losses in GaN HEMT and silicon MOSFET power transistors." Zbornik radova Elektrotehnicki institut Nikola Tesla 30, no. 30 (2020): 93–109. http://dx.doi.org/10.5937/zeint30-29318.

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The subject of this paper is the mutual comparison of switching energy losses in cascode gallium nitride HEMT and silicon "superjunction" MOSFET transistor, both designed for a maximum operating voltage of 650 V. For the purpose of analysis the transistor switching characteristics, the double pulse test method was implemented. Detailed computer simulation models developed in programs of the SPICE family were used. Data on transient turn -on and turn-off processes were generated by LTspice simulation tool, in a wide range of drain currents, using two different gate resistance values for driving the transistors under test. The obtained results indicate superior switching characteristics of gallium nitride devices in comparison to silicon components, especially during the high drain current transistor operation. During the one transistor switching cycle, the total energy losses in the GaN HEMT were simulated, for a drain current of 30 A, and found to be five to eight times lower when compared to tested Si MOSFET transistor.
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5

Yu, Chien-Cheng, and Ming-Chuen Shiau. "Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby." International Journal of VLSI Design & Communication Systems 7, no. 4 (August 30, 2016): 01–11. http://dx.doi.org/10.5121/vlsic.2016.7401.

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6

Nakaya, Yusuke, Tetsuo Nishi, Shin’ichi Oishi, and Martin Claus. "Numerical existence proof of five solutions for certain two-transistor circuit equations." Japan Journal of Industrial and Applied Mathematics 26, no. 2-3 (October 2009): 327–36. http://dx.doi.org/10.1007/bf03186538.

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7

Lagunovich, N. L. "Optimization of guard rings construction and epitaxial film resistivity of power n-channel DMOS-transistor." Proceedings of the National Academy of Sciences of Belarus, Physical-Technical Series 65, no. 1 (April 6, 2020): 97–103. http://dx.doi.org/10.29235/1561-8358-2020-65-1-97-103.

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Powerful n-channel DMOS-transistor with drain-source breakdown voltage Uds br value over 800 V and thresh-old voltage from 2 to 5 V was considered in this paper. One or more guard rings are formed on perimeter of such transistor for the breakdown voltage raising. The optimal guard rings construction was described and resistivity value of epitaxial film ρv was determined for obtaining required transistor Uds br value. The regression model was built, with the help of which the most optimal construction variants of guard rings of investigated transistor and resistivity value of epitaxial film, were selected. It was established that the five-dimensional polynomial of second order using as regression model allowed choosing the optimal topological spaces values in the guard rings area and ρv value which made it possible to obtain required Uds br values of the transistor. Experimental values of transistor drain-source breakdown voltage were 876 and 875 V, but calculated values (at identical parameters of definitional regression model) were 874 and 880 V, accordingly, that were errors of 0.23 % and 0.57 %, i. e. made model fits well with experimental data. It was established that ρv makes contribution to breakdown voltages values of the transistor that is more substantial than parameters of guard rings construction. This NDMOS-transistor was manufactured under production conditions of OJSC INTEGRAL” – “INTEGRAL” Holding Managing Company according to the technological route developed by the author. Such device is used in various electronic devices for energetics, in mobile phones, as part of high-voltage integrated circuits of AC/DC- and DC/DC-converters and high-voltage, high-stable LED-drivers.
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8

Satputaley, R. J., V. B. Borghate, Vinod Kumar, and Trinath Kumar. "Experimental investigation of new three phase five level transistor clamped H-bridge inverter." EPE Journal 27, no. 1 (January 2, 2017): 12–23. http://dx.doi.org/10.1080/09398368.2017.1299505.

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9

Wang, Hui, and Patrick P. Mercier. "A 3.4-pW 0.4-V 469.3 ppm/°C Five-Transistor Current Reference Generator." IEEE Solid-State Circuits Letters 1, no. 5 (May 2018): 122–25. http://dx.doi.org/10.1109/lssc.2018.2875825.

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10

Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
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11

Liao, Congwei, Changde He, Tao Chen, David Dai, Smart Chung, T. S. Jen, and Shengdong Zhang. "Implementation of an a-Si:H TFT Gate Driver Using a Five-Transistor Integrated Approach." IEEE Transactions on Electron Devices 59, no. 8 (August 2012): 2142–48. http://dx.doi.org/10.1109/ted.2012.2197624.

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12

Yu, Chien-Cheng, Ming-Chuen Shiau, and Ching-Chih Tsai. "Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current." International Journal of VLSI Design & Communication Systems 9, no. 4 (August 30, 2018): 01–15. http://dx.doi.org/10.5121/vlsic.2018.9401.

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13

Atan, Norani, Burhanuddin Yeop Majlis, Ibrahin Ahmad, and K. H. Chong. "Analysis the Effect of Control Factors Optimization on the Threshold Voltage of 18 nm PMOS Using L27 Taguchi Method." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 3 (June 1, 2018): 934. http://dx.doi.org/10.11591/ijeecs.v10.i3.pp934-942.

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This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 ± 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.
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14

Mahmoud, Elhussien A., Ayman S. Abdel-Khalik, and Hussien F. Soliman. "An improved fault tolerant for a five-phase induction machine under open gate transistor faults." Alexandria Engineering Journal 55, no. 3 (September 2016): 2609–20. http://dx.doi.org/10.1016/j.aej.2016.04.040.

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15

Prommee, Pipat, Natapong Wongprommoon, Montree Kumngern, and Winai Jaikla. "Low-Voltage Low-Pass and Band-Pass Elliptic Filters Based on Log-Domain Approach Suitable for Biosensors." Sensors 19, no. 24 (December 17, 2019): 5581. http://dx.doi.org/10.3390/s19245581.

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This research proposes bipolar junction transistor (BJT)-based log-domain high-order elliptic ladder low-pass (LPF) and band-pass filters (BPF) using a lossless differentiator and lossless and lossy integrators. The log-domain lossless differentiator was realized by using seven BJTs and one grounded capacitor, the lossy integrator using five BJTs and one grounded capacitor, and the lossless integrator using seven BJTs and one grounded capacitor. The simplified signal flow graph (SFG) of the elliptic ladder LPF consisted of two lossy integrators, one lossless integrator, and one lossless differentiator, while that of the elliptic ladder BPF contained two lossy integrators, five lossless integrators, and one lossless differentiator. Log-domain cells were directly incorporated into the simplified SFGs. Simulations were carried out using PSpice with transistor array HFA3127. The proposed filters are operable in a low-voltage environment and are suitable for mobile equipment and further integration. The log-domain principle enables the frequency responses of the filters to be electronically tunable between 10k Hz–10 MHz. The proposed filters are applicable for low-frequency biosensors by reconfiguring certain capacitors. The filters can efficiently remove low-frequency noise and random noise in the electrocardiogram (ECG) signal.
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16

Kumar, Manoj. "A Low Power Voltage Controlled Oscillator Design." ISRN Electronics 2013 (May 15, 2013): 1–6. http://dx.doi.org/10.1155/2013/987179.

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The performance of voltage controlled oscillator (VCO) is of great importance for any telecommunication or data transmission network. Here, voltage controlled oscillators (VCOs) using three-transistor NAND gates have been designed. New delay cell with three-transistor NAND gate has been used for designing the ring based VCO circuits. Three-, five-, and seven-stage VCOs have been proposed. Output frequency has been controlled with supply voltage variation from 1.8 V to 2.4 V. Three stage VCO shows output frequency variation in the range of 3.2909 GHz to 4.2280 GHz whereas power consumption varies in the range of 335.4071 μW to 486.1816 μW. Five-stage VCO depicts frequency in the range of 1.9406 GHz to 2.5769 GHz with power consumption variation from 559.0118 μW to 810.3027 μW. Moreover a seven-stage VCO shows frequency variation from 1.3984 GHz to 1.8077 GHz. Power consumption of seven-stage VCO varies from 782.6165 μW to 1134.400 μW. Phase noise results for these VCOs have also been obtained. Power consumption, output frequency, and phase noise results of proposed circuits have been compared with earlier reported circuits, and the proposed circuits show significant improvements.
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17

Wang, Chua-Chin, Zong-You Hou, Deng-Shian Wang, and Chia-Lung Hsieh. "A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry." Journal of Circuits, Systems and Computers 29, no. 06 (August 13, 2019): 2050095. http://dx.doi.org/10.1142/s0218126620500954.

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A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.
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18

Singamsetti, Mrudula, and Sarada Musala. "A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors." International Journal of Engineering Trends and Technology 11, no. 6 (May 25, 2014): 277–83. http://dx.doi.org/10.14445/22315381/ijett-v11p253.

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19

Kumar, Prateek, Maneesha Gupta, and Kunwar Singh. "Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Transistor." Silicon 12, no. 12 (January 14, 2020): 2809–17. http://dx.doi.org/10.1007/s12633-020-00376-7.

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20

Shokrani, Mohammad Reza, Mojtaba Khoddam, Mohd Nizar B. Hamidon, Noor Ain Kamsani, Fakhrul Zaman Rokhani, and Suhaidi Bin Shafie. "An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/963709.

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This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.
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21

Xia, Bingbing, Jun Wu, Hongjin Liu, Kai Zhou, and Zhifu Miao. "Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process." Journal of Circuits, Systems and Computers 25, no. 12 (September 2, 2016): 1650163. http://dx.doi.org/10.1142/s0218126616501632.

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With the need for fast and low-power radiation-hardened processors, advanced technology process is applied to obtain both high performance as well as high reliability. However, scaling down of the size of the transistor makes the transistor sensitive to outside disturbances, such as soft error introduced by the strikes of the cosmic neutron beams. Besides aerospace applications, such reliability should also be taken into consideration for the sub-100[Formula: see text]nm CMOS designs to ensure the robustness of the circuit. In such circumstances, several radiation-hardened flip-flops are designed and simulated under SMIC 40[Formula: see text]nm process. Simulation results show that with five aspects (performance, power, area, PVT variation and reliability) taken into consideration, TSPC-based DICE and TMR combined architecture has the best soft-error robustness in comparison with other radiation-hardened flip-flops, and the critical charge of such architecture is 490[Formula: see text]fC, which is 12.5X higher than the traditional unhardened flip-flop.
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22

Yarmukhamedov, A., A. Zhabborov, and B. Turimbetov. "EXPERIMENTAL RESEARCH AND COMPUTER SIMULATION OF MULTI-CASCADE COMPOSITE TRANSISTORS FOR STABILIZING THE OPERATING MODE OF OUTPUT CASCADES OF RADIO ENGINEERING DEVICES." Technical science and innovation 2019, no. 1 (June 11, 2019): 33–42. http://dx.doi.org/10.51346/tstu-01.18.2.-77-0009.

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Experimental results and computer simulation of multi-stage composite transistors are presented. To study the volt - ampere characteristics of multistage composite transistors, a dialogue computer simulation program, the Delphi programming environment, has been developed. It is shown that the proposed multistage composite transistors can improve manufacturability in its industrial production. It is shown that multistage homostructure transistors according to the Darlington and Shiklai circuits operate stably at collector-emitter voltages five times higher than in the case of individual transistors. The power dissipated on the collector is 3 times higher than the rated value of the maximum permissible power of the composite transistors. It is established that the efficiency of the method of stabilizing the emitter current of a three-link homostructure transistor is 7 times higher in voltage and three orders of magnitude higher in temperature compared to a conventional composite transistor. The proposed homostructure transistors are designed to operate in terminal stages of power amplifiers, radio transmitting devices, electronic equipment of industrial and automotive electronics
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23

Singh, Shradhya, Shashi Bala, Balwant Raj, and Balwinder Raj. "Improved Sensitivity of Dielectric Modulated Junctionless Transistor for Nanoscale Biosensor Design." Sensor Letters 18, no. 4 (April 1, 2020): 328–33. http://dx.doi.org/10.1166/sl.2020.4224.

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This work has proposed a device i.e., Dielectric Modulated (DM) Junctionless Transistor which is utilizes as Label-Free (LF) electrical characteristic detection of bio-molecules. The electrical characteristics used for the detection of biomolecules are electric field, surface potential, drain current and threshold voltage (Vth). Due to immobilization of biomolecules in the cavity region, the threshold voltage change in comparison to the absence of biomolecule, which is utilizes as the sensitivity metric. The sensitivity of biomolecule detection can be enhanced by using asymmetric gate operation of the device. In asymmetric mode the degree of sensitivity is almost five times higher than that of the symmetric mode of operation.
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24

Teh, Yijun, Asral Bahari Jambek, and Uda Hashim. "The latest trend in nano-bio sensor signal analysis." Sensor Review 36, no. 3 (June 20, 2016): 303–11. http://dx.doi.org/10.1108/sr-08-2015-0132.

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Purpose This paper aims to discuss a nanoscale biosensor and its signal analysis algorithms. Design/methodology/approach In this work, five nanoscale biosensors are reviewed, namely, silicon nanowire field-effect-transistor biosensors, polysilicon nanogap capacitive biosensors, nanotube amperometric biosensors, gold nanoparticle-based electrochemical biosensors and quantum dot-based electrochemical biosensors. Findings Each biosensor produces a different output signal depending on its electrical characteristics. Five signal analysers are studied, with most of the existing signal analyser analyses based on the amplitude of the signal. Based on the analysis, auto-threshold peak detection is proposed for further work. Originality/value Suitability of the signal processing algorithm to be applied to nano-biosensors was reported.
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25

Sato, Yoji, Max Harry Weil, Wanchun Tang, Shijie Sun, Jianlin Xie, Joe Bisera, and Hidehiro Hosaka. "Esophageal P CO 2 as a monitor of perfusion failure during hemorrhagic shock." Journal of Applied Physiology 82, no. 2 (February 1, 1997): 558–62. http://dx.doi.org/10.1152/jappl.1997.82.2.558.

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Sato, Yoji, Max Harry Weil, Wanchun Tang, Shijie Sun, Jianlin Xie, Joe Bisera, and Hidehiro Hosaka. Esophageal[Formula: see text] as a monitor of perfusion failure during hemorrhagic shock. J. Appl. Physiol. 82(2): 558–562, 1997.—Measurement of gastric wall [Formula: see text]([Formula: see text]) by tonometric method has emerged as an attractive option for estimating visceral perfusion during circulatory shock. However, gastric acid secretion obfuscates the tonometric measurement. We, therefore, investigated the option of measuring[Formula: see text] in the esophagus to minimize these restraints. Hemorrhagic shock was induced in five Sprague-Dawley rats, and five rats served as sham controls.[Formula: see text] was measured with an ion-sensitive field effect transistor that was surgically implanted into the gastric wall. Esophageal luminal[Formula: see text]([Formula: see text]) was measured by a second ion-sensitive field effect transistor sensor. During hemorrhagic shock, mean aortic pressure declined from 150 to 50 mmHg. Gastric blood flow decreased from 58 to 12 ml ⋅ min−1 ⋅ 100 g−1 (21% of preshock) and esophageal blood flow from 44 to 7 ml ⋅ min−1 ⋅ 100 g−1 (16% of preshock).[Formula: see text]simultaneously increased from 47 to 116 Torr and[Formula: see text] from 47 to 127 Torr. The increases in[Formula: see text] were highly correlated with increases in[Formula: see text]( r = 0.90). Esophageal tonometry may, therefore, serve as a practical alternative to gastric tonometry.
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26

Chen, Liang. "Design and Thermal Analysis of SiGe HBT with Non-Uniform Segmented Emitter Fingers and Non-Uniform Emitter Finger Spacing." Applied Mechanics and Materials 713-715 (January 2015): 938–41. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.938.

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A novel multi-finger power SiGe heterojunction bipolar transistor (HBT) with non-uniform segmented emitter fingers and non-uniform emitter finger spacing was proposed to improve the thermal stability. Thermal simulation for a five-finger power SiGe HBT with novel structure was conducted with ANSYS software. Three-dimensional temperature distribution on emitter fingers was obtained. Compared with non-uniform segmented emitter fingers structure and non-uniform emitter finger spacing structure, the maximum junction temperature of novel structure reduce significantly, the thermal resistance reduce, temperature distribution were significantly improved. Thermal stability was effective enhanced.
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Chen, Liang, Cheng Zhong Hu, and Chun Ling Jiang. "Design and Thermal Analysis of SiGe HBT with Segmented Emitter Fingers and Non-Uniform Emitter Finger Spacing." Applied Mechanics and Materials 462-463 (November 2013): 592–96. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.592.

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A novel multi-finger power SiGe heterojunction bipolar transistor (HBT) with segmented emitter fingers and non-uniform emitter finger spacing was proposed to improve the thermal stability. Thermal simulation for a five-finger power SiGe HBT with novel structure was conducted with ANSYS software. Three-dimensional temperature distribution on emitter fingers was obtained. Compared with traditional emitter structure, the maximum junction temperature of novel structure reduce significantly from 429.025K to 414.252K, the thermal resistance reduce from 159K/W to 141K/W, temperature distribution were significantly improved. Thermal stability was effective enhanced.
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28

Atan, Norani, Burhanuddin Bin Yeop Majlis, Ibrahim Bin Ahmad, and K. H. Chong. "Influence of optimization of control factors on threshold voltage of 18 nm HfO2/TiSi2 NMOS." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (April 1, 2019): 295. http://dx.doi.org/10.11591/ijeecs.v14.i1.pp295-302.

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<span>This paper presents the influence of control factors as the process in development of 18 nm gate length NMOS transistor. The threshold voltage (VTH) can be minimized by optimal the control factors. Five control factors were selected through experiments. They are Adjustment VTH Implantation, Compensation Implantation, Compensation Energy Implantation, Source/Drain Implantation and Halo Implantation. While the two noise factors were introduced which are Phosphor Silicate Glass (PSG) temperature and Boron Phosphor Silicate Glass (BPSG) temperature to complete the combination with five control factors in process of Taguchi method L27 orthogonal array. The purpose of this research is to find the best value of interaction between combination controls factors and noise factors to achieve the best point of threshold voltage. In CMOS design, the threshold voltage is the benchmarking of physical parameter for determining the functional of transistor. The Virtual Wafer Fabrication SILVACO software was used to fabricate the 18 nm NMOS device. Hafnium Oxide (HfO2) and Titanium dioxide (TiO2) were utilized as the high-K materials and the Titanium Silicide (TiSi2) was utilized as metal gate. The statistics data are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) of L27 orthogonal array are executed to minimize the variance of threshold voltage. The results show that the optimization and interaction method is achieved to perform the threshold voltage value with least variance is 0.3055 volts while the target value that is 0.302 ± 12.7% volts from value recommendation by the International Roadmap for Semiconductor prediction 2012.</span>
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29

Mullner, David, Brooke Garner, and Donald Plumlee. "Feasibility of Micro-Plasma Transistor Devices in LTCC." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (September 1, 2012): 000365–69. http://dx.doi.org/10.4071/cicmt-2012-wa43.

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The project will determine if making a novel micro-plasma transistor device (MPT device) in LTCC is feasible and advantageous. MPT devices control plasma, created by an antenna, by using electrodes. Using LTCC could be beneficial due to its properties involving plasma erosion and the ability for integrated 3D electronic construction. The layer construction of LTCC makes it relatively easy to implement the design, using five layers to produce a variety of configurations. The device will consist of source, gate, and drain electrodes on different layers of LTCC, with the antenna creating the plasma. The MPT device will be fabricated using DuPont 951 LTCC tapes and the ceramic MEMS fabrication process. A test matrix will be made to understand how micro-plasma transistors behave in LTCC. The matrix will include variations in hole diameter and operational parameters such as electrode configuration and voltage. The MPT device will be tested at BSU using a vacuum chamber and associated electronic hardware. After the tests are administered, the feasibility of micro-plasma transistors in LTCC will be determined.
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30

Salehifar, Mehdi, Ramin Salehi Arashloo, Manuel Moreno Eguilaz, and Vicent Sala. "FPGA Based Robust Open Transistor Fault Diagnosis and Fault Tolerant Sliding Mode Control of Five-Phase PM Motor Drives." Journal of Power Electronics 15, no. 1 (January 20, 2015): 131–45. http://dx.doi.org/10.6113/jpe.2015.15.1.131.

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31

McCormick, Frederick B., Tom J. Cloonan, Anthony L. Lentine, Jose M. Sasian, Rick L. Morrison, Martin G. Beckman, Sonya L. Walker, et al. "Five-stage free-space optical switching network with field-effect transistor self-electro-optic-effect-device smart-pixel arrays." Applied Optics 33, no. 8 (March 10, 1994): 1601. http://dx.doi.org/10.1364/ao.33.001601.

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32

SIMIN, GRIGORY, MICHAEL S. SHUR, and REMIS GASKA. "5-TERMINAL THzGaN BASED TRANSISTOR WITH FIELD- AND SPACE-CHARGE CONTROL ELECTRODES." International Journal of High Speed Electronics and Systems 19, no. 01 (March 2009): 7–14. http://dx.doi.org/10.1142/s0129156409006047.

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We present a novel approach to achieve terahertz-range cutoff frequencies and maximum frequencies of operation of GaN based heterostructure field-effect transistors (HFETs) at relatively high drain voltages. Strong short-channel effects limit the frequency of operation and output power in conventional geometry GaN HFETs. In this work, we propose a novel device with two additional independently biased electrodes controlling the electric field and space-charge close to the gate edges. As a result, the effective gate length extension due to short channel effects is diminished and electron velocity in the device channel is increased. Our simulations show that the proposed five-terminal HFET allows achieving fT=1.28 THz and fmax= 0.815 THz at the drain voltages as high as 12 V. Hence, this device opens up a new approach to designing THz transistor sources.
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33

Lovinger, Andrew J., and Lewis J. Rothberg. "Electrically active organic and polymeric materials for thin-film-transistor technologies." Journal of Materials Research 11, no. 6 (June 1996): 1581–92. http://dx.doi.org/10.1557/jmr.1996.0198.

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Organic and polymeric materzials have seen a tremendous growth in research in the last five years as potential electroactive elements in thin-film-transistor (TFT) applications. These are driven by the increasing interest in flat-panel-display applications, for which organic and polymeric materials offer strong promise in terms of properties, processability, cost, and compatibility with eventual lightweight, flexible plastic displays. In this review we summarize the current status of our knowledge on the science of these organic and polymeric semiconducting materials. Most of these are based on linear thiophenes, especially a-hexathienyl, which has elicited by far the most attention. Mobility values in the 10−2–10−1 cm2/Vs and especially source-drain current on/off ratios of up to 106 make this a highly promising potential alternative to amorphous silicon. Other thienyl compounds are also discussed, as are polymeric analogues. A brief discussion of technological potential, limitations, and problems that need to be overcome is given at the end.
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34

Itoh, Yoshimitsu, Bumjung Kim, Raluca I. Gearba, Noah J. Tremblay, Ron Pindak, Yutaka Matsuo, Eiichi Nakamura, and Colin Nuckolls. "Simple Formation of C60and C60-Ferrocene Conjugated Monolayers Anchored onto Silicon Oxide with Five Carboxylic Acids and Their Transistor Applications." Chemistry of Materials 23, no. 4 (February 22, 2011): 970–75. http://dx.doi.org/10.1021/cm1025975.

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35

Simmich, Sebastian, Andreas Bahr, and Robert Rieger. "Noise Efficient Integrated Amplifier Designs for Biomedical Applications." Electronics 10, no. 13 (June 23, 2021): 1522. http://dx.doi.org/10.3390/electronics10131522.

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The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√Hz with a 10 µA bias current, which results in a NEF of 1.2.
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36

Abuelma'atti, M. T., and O. O. Fares. "A New Universal Second-Order Filter using Configurable Analog Building Blocks (CABs) for Filed-Programmable Analogue Arrays." Journal of Engineering Research [TJER] 7, no. 2 (June 1, 2011): 83. http://dx.doi.org/10.24200/tjer.vol8iss1pp83-91.

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In this paper, the design of a universal second-order filter using configurable analog blocks (CABs) for field programmable analog arrays is presented. The configurable blocks are capable of performing integration, differentiation, amplification, log, anti-log, add and negate functions. To maintain high frequency operation, the programmability and configurability of the blocks are achieved by digitally modifying the block's biasing conditions. Using at most four CABs, this article shows that it is possible to design a versatile second-order filter realizing all the standard five filter functions; lowpass, highpass, bandpass, notch and allpass. SPICE simulation results using practical bipolar junction transistor (BJT) parameters confirm the feasibility of using the CABs in designing second-order filters.
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37

Al jewari, Maher Abd Ibrahim, Auzani Jidin, Siti Azura Ahmad Tarusan, and Mohammed Rasheed. "Implementation of SVM for five-level cascaded H-Bridge multilevel inverters utilizing FPGA." International Journal of Power Electronics and Drive Systems (IJPEDS) 11, no. 3 (September 1, 2020): 1132. http://dx.doi.org/10.11591/ijpeds.v11.i3.pp1132-1144.

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The Space Vector Modulation SVM technique has won large acceptance for AC drive applications. However the utilization of multilevel inverters connected with SVM by Digital signal processor (DSP) raise the intricacy of control algorithm or computational load, increases of the obtaining distortions output voltage. The development of SVM in multilevel inverters may offer higher numbers of switching vectors for acquiring further enhancements of output voltage performances and implement by using Field Programmer Gate Array (FPGA), investigate lower Total Hormonic Distortion (THD). This paper reports the performance evaluation of SVM for five-level of Cascaded H-Bridge Multilevel Inverter CHMI using MATLAB/Simulink, which is sampled at the minimum sampling time, i.e. DT = 5 μs. The switching signals for driving insulated gate bipolar transistor (IGBTs) which are stored in MATLAB workspaces, are then used to be programmed in FPGA using a Quartus II software. Which can be stated the lower THD of the simulation result is about 14.48% for five-level CHMI and experiment result is about 14.31% for five-level CHMI at modulation index M_i=0.9. The error percentage between the simulation results and experimental results of the fundamental output voltage in SVM is small which is approximately less than 1 %.
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38

Weissbrodt, Ernst, Michael Schlechtweg, Oliver Ambacher, and Ingmar Kallfass. "W-band active loads and switching front-end MMICs for radiometer calibration." International Journal of Microwave and Wireless Technologies 5, no. 3 (May 24, 2013): 293–99. http://dx.doi.org/10.1017/s1759078713000470.

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A millimeter-wave monolithic integrated circuit consisting of a W-band (75–100 GHz) single-pole-five-throw (SP5T) switch and multiple internal active and passive loads for radiometer calibration was designed and manufactured in a low noise 50 nm GaAs metamorphic high electron mobility transistor technology. This highly compact and integrated front-end device for radiometer systems is capable of ultra fast switching between two identical input ports (e.g. for polarimetric applications) and three internal calibration references. It allows an accurate multi-load calibration with noise temperatures between 220 and 1750 K at the output of the device. Compared to conventional calibration methods this marks a substantial advantage in terms of size, mass, power consumption, complexity, and repetition rate.
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39

Tsai, Jung-Hui, Jing-Shiuan Niu, Xin-Yi Huang, and Wen-Chau Liu. "Comparative Investigation of AlGaN/AlN/GaN High Electron Mobility Transistors with Pd/GaN and Pd/Al2O3/GaN Gate Structures." Science of Advanced Materials 13, no. 2 (February 1, 2021): 289–93. http://dx.doi.org/10.1166/sam.2021.3856.

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In this article, the electrical characteristics of Al0.28Ga0.72 N/AlN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) with a 20-nm-thick Al2O3 layer by using radio-frequency sputtering as the gate dielectric layer are compared to the conventional metal-semiconductor HEMT (MS-HEMT) with Pd/GaN gate structure. For the insertion of the Al2O3 layer, the energy band near the AlN/GaN heterojunction is lifted slightly up and the 2DEG at the heterojunction is reduced to shift the threshold voltage to the right side. Experimental results exhibits that though the maximum drain current decreases about 6.5%, the maximum transconductance increases of 9%, and the gate leakage current significantly reduces about five orders of magnitude for the MOS-HEMT than the MS-HEMT.
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40

Hou, Yanfei, Weihua Yu, Qin Yu, Bowu Wang, Yan Sun, Wei Cheng, and Ming Zhou. "A 56–161 GHz Common-Emitter Amplifier with 16.5 dB Gain Based on InP DHBT Process." Electronics 10, no. 14 (July 11, 2021): 1654. http://dx.doi.org/10.3390/electronics10141654.

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This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.
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41

Rastayesh, Sima, Sajjad Bahrebar, Amir Sajjad Bahman, John Dalsgaard Sørensen, and Frede Blaabjerg. "Lifetime Estimation and Failure Risk Analysis in a Power Stage Used in Wind-Fuel Cell Hybrid Energy Systems." Electronics 8, no. 12 (November 26, 2019): 1412. http://dx.doi.org/10.3390/electronics8121412.

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This paper presents a methodology based on the failure mode and effect analysis (FMEA) to analyze the failures in the power stage of wind-fuel cell hybrid energy systems. Besides, fault tree analysis (FTA) is applied to describe the probabilistic failures in the vital subcomponents. Finally, the reliability assessment of the system is carried out for a five-year operation that is guaranteed by the manufacturer. So, as the result, the reliability analysis proves that the metal oxide semiconductor field effect transistor (MOSFET) and electrolytic capacitor are the most critical components that introduce damages in the power circuit. Moreover, a comparative study on the reliability assessment by the exponential distribution and the Weibull distribution show that the B1 lifetime obtained by the Weibull distribution is closer to reality.
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42

Salehifar, Mehdi, Ramin Salehi Arashloo, Manuel Moreno‐Eguilaz, Vicent Sala, and Luis Romeral. "Observer‐based open transistor fault diagnosis and fault‐tolerant control of five‐phase permanent magnet motor drive for application in electric vehicles." IET Power Electronics 8, no. 1 (January 2015): 76–87. http://dx.doi.org/10.1049/iet-pel.2013.0949.

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43

Rathore, Pradeep Kumar, Brishbhan Singh Panwar, and Jamil Akhtar. "A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique." Microelectronics International 32, no. 2 (May 5, 2015): 81–95. http://dx.doi.org/10.1108/mi-11-2014-0048.

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Purpose – The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors. Design/methodology/approach – This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge. Findings – The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits. Originality/value – The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.
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44

Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.
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45

Chen, Huajie, Zhaoxia Liu, Zhiyuan Zhao, Liping Zheng, Songting Tan, Zhihong Yin, Chunguang Zhu, and Yunqi Liu. "Synthesis, Structural Characterization, and Field-Effect Transistor Properties of n-Channel Semiconducting Polymers Containing Five-Membered Heterocyclic Acceptors: Superiority of Thiadiazole Compared with Oxadiazole." ACS Applied Materials & Interfaces 8, no. 48 (November 22, 2016): 33051–59. http://dx.doi.org/10.1021/acsami.6b12540.

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46

RATHOD, S. S., A. K. SAXENA, and S. DASGUPTA. "DG-FINFET-BASED SRAM CONFIGURATIONS FOR INCREASED SEU IMMUNITY." Journal of Circuits, Systems and Computers 21, no. 04 (June 2012): 1250032. http://dx.doi.org/10.1142/s0218126612500326.

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In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to radiation. This is primarily due to the modification of the source potential used to reduce the effect of SEU without affecting normal operation. Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) and Power Delay Product (PDP) are the performance metrics computed for each type of SRAM cell. Effect of back gate voltage and back gate oxide thickness variation on device characteristic show detrimental effects on radiation hardened capabilities of a device. Benchmarking is done against DICE latch and it is found that as compared to DICE latch proposed DG-FinFET SRAM has low transistor count, less area, low recovery time and fault tolerance to internal as well as external nodes.
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47

Uttaphut, Prungsak. "Simple Three-Input Single-Output Current-Mode Universal Filter Using Single VDCC." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 4932. http://dx.doi.org/10.11591/ijece.v8i6.pp4932-4940.

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This paper presents a second-order current-mode filter with three-inputs and single-output current using single voltage differencing current conveyors (VDCC) along with one resistor and two grounded capacitors. The design of presented filter emphasizes on the use of a single active element without the multiple terminals VDCC which is convenient to implement the VDCC using commercially available IC for the practical test. Also, it can reduce the current tracking error at current output port and can reduce the number of transistor in the VDCC. The proposed filter can realize all the five generic filter responses, namely, band-pass (BP), band-reject (BR), low-pass (LP), high-pass (HP), and all-pass (AP) functions from the same configuration under various conditions in terms of three input current signals. Furthermore, the natural frequency and quality factor are electronically controlled. The output current node exhibits high impedance. Besides, the non-ideal case is also investigated. The simulation and experimental results using VDCC constructed from commercially available IC can validate the theoretical analyses.
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48

JAMALABADI, ZAHRA, PARVIZ KESHAVARZI, and ALI NADERI. "SDC-CNTFET: STEPWISE DOPING CHANNEL DESIGN IN CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR IMPROVING SHORT CHANNEL EFFECTS IMMUNITY." International Journal of Modern Physics B 28, no. 07 (February 20, 2014): 1450048. http://dx.doi.org/10.1142/s0217979214500489.

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A novel carbon nanotube field-effect transistor with stepwise doping profile channel (SDC-CNTFET) is introduced for short-channel effects (SCEs) improvement. In SDC-CNTFET, the channel is divided into five sections of equal length. Impurity concentration was reduced from 0.8 nm-1 to zero from the source side to the drain side of the channel, with stepwise profile. The devices have been simulated by the self-consistent solution of two-dimensional (2D) Poisson–Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. We demonstrate that the proposed structure for CNTFETs shows considerable improvement in device performance focusing on leakage current and ON–OFF current ratio. In addition, the investigation of SCEs for the proposed structure shows the improved drain-induced barrier lowering (DIBL) and subthreshold swing (SS). Moreover, we will prove that the proposed structure has acceptable performance at different values of channel impurity concentration in terms of delay and power-delay product (PDP). All these investigations introduce SDC-CNTFET as a more reliable device structure in short-channel regime.
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Chen, Huajie, Zhaoxia Liu, Zhiyuan Zhao, Liping Zheng, Songting Tan, Zhihong Yin, Chunguang Zhu, and Yunqi Liu. "Correction to Synthesis, Structural Characterization, and Field-Effect Transistor Properties of n-Channel Semiconducting Polymers Containing Five-Membered Heterocyclic Acceptors: Superiority of Thiadiazole Compared with Oxadiazole." ACS Applied Materials & Interfaces 9, no. 4 (January 20, 2017): 4280. http://dx.doi.org/10.1021/acsami.6b16097.

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50

Huh, Yoon-Young, Jong-Mun Choi, Jung-Min Kim, Ey-Goo Kang, and Hun-Suk Chung. "A Study on the Optimization of Deep-Trench Super Junction Metal Oxide Semiconductor Field-Effect Transistor." Journal of Nanoelectronics and Optoelectronics 16, no. 5 (May 1, 2021): 781–85. http://dx.doi.org/10.1166/jno.2021.3006.

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Power metal oxide semiconductor field-effect transistor is a switching device designed to handle large power consumption; it enables fast switching, resulting in low power consumption. Power devices are used as important components that determine the operation and performance of electrically powered products such as home appliances, smartphones, and automobiles. Power devices must be able to block high voltage so that current does not flow in the off state, have no power consumption in the on state, and have a small resistance so that high current can flow. For high efficiency, power loss must be minimized and resistance must be reduced during the turn-on state. To increase the breakdown voltage, the thickness and resistivity of the N-drift region must be increased. However, owing to the trade-off relationship, as the breakdown voltage increases, the on-resistance also increases. The super junction structure was proposed to improve this trade-off relationship. In this study, a process simulation using TCAD tool was carried out. Similar to the multi-epitaxial process, the P-pillar was divided into several layers, and the value of each concentration was specified. Thus, the charge balance of the pillar regions was achieved. For the maximum breakdown voltage characteristics and minimum on-resistance characteristics of the deep-trench super junction MOSFET, an experiment was conducted to optimize the cell pitch and pillar of the super junction MOSFET using a five-deep trench.
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