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Journal articles on the topic 'Flash Translation Layer'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 February 2022

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1

Choi, Yoonsuk, and Shahram Latifi. "Modern flash technologies: a flash translation layer perspective." International Journal of High Performance Systems Architecture 4, no. 3 (2013): 167. http://dx.doi.org/10.1504/ijhpsa.2013.055252.

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2

Chung, Tae-Sun, Dong-Joo Park, Sangwon Park, Dong-Ho Lee, Sang-Won Lee, and Ha-Joo Song. "A survey of Flash Translation Layer." Journal of Systems Architecture 55, no. 5-6 (2009): 332–43. http://dx.doi.org/10.1016/j.sysarc.2009.03.005.

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3

Zhang, Peiyong, and Huanjie Tang. "High‐efficient superblock flash translation layer for NAND flash controller." Electronics Letters 56, no. 6 (2020): 278–80. http://dx.doi.org/10.1049/el.2019.3526.

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4

Kumar, Shailesh, Kumkum Dubey, and P. K. Singh. "A Survey on Flash Translation Layer for NAND Flash Memory." Indian Journal of Science and Technology 11, no. 23 (2018): 1–7. http://dx.doi.org/10.17485/ijst/2018/v11i23/125641.

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5

Chung, Tae-Sun, Dong-Joo Park, and Jongik Kim. "An Efficient Flash Translation Layer for Large Block NAND Flash Devices." Journal of Circuits, Systems and Computers 24, no. 09 (2015): 1550138. http://dx.doi.org/10.1142/s0218126615501388.

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Recently, flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 players, digital cameras and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. Many researchers have proposed FTL algorithms for small block flash memory in which the size of a physical page of flash memory is equivalent to the size of a data sector of the file system. However, major flash vendors have now produced large block flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block flash memory has new features, designing FTL algorithms specialized to large block flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block flash memory and to provide safety by abiding by restrictions of large block flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block flash memory.

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6

Bang, Kwanhu, Sang-Hoon Park, Hyuk-Jun Lee, and Eui-Young Chung. "Flash Translation Layer for Heterogeneous NAND Flash-based Storage Devices Based on Access Patterns of Logical Blocks." Journal of the Institute of Electronics Engineers of Korea 50, no. 5 (2013): 94–101. http://dx.doi.org/10.5573/ieek.2013.50.5.094.

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7

Ryu, Yeonseung. "A Flash Translation Layer for nand Flash-Based Multimedia Storage Devices." IEEE Transactions on Multimedia 13, no. 3 (2011): 563–72. http://dx.doi.org/10.1109/tmm.2011.2114333.

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8

Mong-Ling Chiao and Da-Wei Chang. "ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation." IEEE Transactions on Computers 60, no. 6 (2011): 753–66. http://dx.doi.org/10.1109/tc.2011.67.

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9

Se Jin Kwon, Hyung-Ju Cho, and Tae-Sun Chung. "Fast responsive flash translation layer for smart devices." IEEE Transactions on Consumer Electronics 60, no. 1 (2014): 52–59. http://dx.doi.org/10.1109/tce.2014.6780925.

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10

Shen, Zhaoyan, Zhiping Jia, Xin Li, Xiaojun Cai, and Lei Ju. "A data-driven superblock-based flash translation layer." Optik 126, no. 20 (2015): 2735–42. http://dx.doi.org/10.1016/j.ijleo.2015.06.065.

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11

Luo, Yuhan, and Mingwei Lin. "Flash translation layer: a review and bibliometric analysis." International Journal of Intelligent Computing and Cybernetics 14, no. 3 (2021): 480–508. http://dx.doi.org/10.1108/ijicc-02-2021-0034.

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PurposeThe purpose of this paper is to make an overview of 474 publications and 512 patents of FTL from 1987 to 2020 in order to provide a conclusive and comprehensive analysis for researchers in this field, as well as a preliminary knowledge of FTL for interested researchers.Design/methodology/approachFirstly, the FTL algorithms are classified and its functions are introduced in detail. Secondly, the structures of the publications are analyzed in terms of the fundamental information and the publication of the most productive countries/regions, institutions and authors. After that, co-citation networks of institutions, authors and papers illustrated by VOS Viewer are given to show the relationship among those and the most influential of them is further analyzed. Then, the characteristics of the patent are analyzed based on the basic information and classification of the patent and the most productive inventors. In order to obtain research hotspots and trends in this field, the time-line review and citation burst detection of keywords carried out by Cite Space are made to be visual. Finally, based on the above analysis, it draws some other important conclusions and the development trend of this field.FindingsThe research on FTL algorithm is still the top priority in the future, and how to improve the performance of SSD in the era of big data is one of the research hotspots.Research limitations/implicationsThis paper makes a comprehensive analysis of FTL with the method of bibliometrics, and it is valuable for researchers can quickly grasp the hotspots in this area.Originality/valueThis article draws the structural characteristics of the publications in this field and summarizes the research hotspots and trends in this field in recent years, aiming to inspire new ideas for researchers.

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12

He, Qinlu, Genqing Bian, Weiqi Zhang, Fenglang Wu, and Zhen Li. "TCFTL: Improved Real-Time Flash Memory Two Cache Flash Translation Layer Algorithm." Journal of Nanoelectronics and Optoelectronics 16, no. 3 (2021): 403–13. http://dx.doi.org/10.1166/jno.2021.2970.

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The traditional flash translation layer (FTL) algorithm is mainly aimed at optimizing the average response time of flash reading and writing. Since it cannot be updated in place, for the traditional FTL algorithm, it is necessary to find a free page for writing each time. When a block is full, it will redistribute a free block. Therefore, when the flash memory is almost full, a written request will lead to a garbage collection, which will have many write copies, which will lead to a substantial decline in response time. This paper proposes an algorithm that makes full use of spatial locality and temporal locality to optimize the address cache in Demand-based Flash Translation Layer (DFTL) algorithm. In the experiment, this algorithm experiment and good results are obtained.

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13

Park, Chanik, Wonmoon Cheon, Jeonguk Kang, Kangho Roh, Wonhee Cho, and Jin-Soo Kim. "A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications." ACM Transactions on Embedded Computing Systems 7, no. 4 (2008): 1–23. http://dx.doi.org/10.1145/1376804.1376806.

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14

Yang, Yin, Wenyi Li, Zhihu Tan, Changsheng Xie, and Kai Wang. "BLF: an efficient flash translation layer scheme for flash-based storage systems." Journal of the Chinese Institute of Engineers 38, no. 7 (2015): 938–46. http://dx.doi.org/10.1080/02533839.2015.1037353.

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15

Han, Dae. "Fast erase algorithm using flash translation layer in NAND-type flash memory." IEEE Transactions on Consumer Electronics 57, no. 4 (2011): 1749–55. http://dx.doi.org/10.1109/tce.2011.6131150.

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16

Wang, Yi, Zhiwei Qin, Renhai Chen, et al. "A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems." IEEE Transactions on Multi-Scale Computing Systems 2, no. 1 (2016): 17–29. http://dx.doi.org/10.1109/tmscs.2016.2516015.

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17

Kwon, Se Jin, Hyung-Ju Cho, Sungsoo Kim, and Tae-Sun Chung. "Random data-aware flash translation layer for NAND flash-based smart devices." Journal of Supercomputing 66, no. 1 (2013): 81–93. http://dx.doi.org/10.1007/s11227-013-0979-7.

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18

Lee, Sang-Won, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park, and Ha-Joo Song. "A log buffer-based flash translation layer using fully-associative sector translation." ACM Transactions on Embedded Computing Systems 6, no. 3 (2007): 18. http://dx.doi.org/10.1145/1275986.1275990.

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19

Yao, Yingbiao, Mingbo Yan, Xiaochong Kong, Xiaorong Xu, Wei Feng, and Xin Xu. "An Adaptive Read-Write Partitioning Flash Translation Layer Algorithm." IEEE Access 7 (2019): 179063–73. http://dx.doi.org/10.1109/access.2019.2958609.

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20

Jesung Kim, Jong Min Kim, S. H. Noh, Sang Lyul Min, and Yookun Cho. "A space-efficient flash translation layer for CompactFlash systems." IEEE Transactions on Consumer Electronics 48, no. 2 (2002): 366–75. http://dx.doi.org/10.1109/tce.2002.1010143.

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21

Lin, Pei-Kuan, Mong-Ling Chiao, and Da-Wei Chang. "Improving flash translation layer performance by supporting large superblocks." IEEE Transactions on Consumer Electronics 56, no. 2 (2010): 642–50. http://dx.doi.org/10.1109/tce.2010.5505982.

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22

Kim, Youngjae, Aayush Gupta, and Bhuvan Urgaonkar. "A Temporal Locality-Aware Page-Mapped Flash Translation Layer." Journal of Computer Science and Technology 28, no. 6 (2013): 1025–44. http://dx.doi.org/10.1007/s11390-013-1395-4.

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23

Chung, Tae-Sun, Dong-Joo Park, and Sehyeong Cho. "An Efficient System Software of Flash Translation Layer for Large Block Flash Memory." KIPS Transactions:PartA 12A, no. 7 (2005): 621–26. http://dx.doi.org/10.3745/kipsta.2005.12a.7.621.

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24

Park, Kwanghee, Junsik Yang, Joon-Hyuk Chang, and Deok-Hwan Kim. "Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory." ETRI Journal 30, no. 6 (2008): 790–98. http://dx.doi.org/10.4218/etrij.08.0108.0145.

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25

Lee, Hyun-Seob, Hyun-Sik Yun, and Dong-Ho Lee. "HFTL: hybrid flash translation layer based on hot data identification for flash memory." IEEE Transactions on Consumer Electronics 55, no. 4 (2009): 2005–11. http://dx.doi.org/10.1109/tce.2009.5373762.

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26

Liao, Xue-Liang, and Shi-Min Hu. "Bridging the information gap between buffer and flash translation layer for flash memory." IEEE Transactions on Consumer Electronics 57, no. 4 (2011): 1765–73. http://dx.doi.org/10.1109/tce.2011.6131152.

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27

Pan, Yubiao, Yongkun Li, Huizhen Zhang, Hao Chen, and Mingwei Lin. "GFTL: Group-Level Mapping in Flash Translation Layer to Provide Efficient Address Translation for NAND Flash-Based SSDs." IEEE Transactions on Consumer Electronics 66, no. 3 (2020): 242–50. http://dx.doi.org/10.1109/tce.2020.2991213.

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28

Yeo, Dong Bin, Joon-Yong Paik, and Tae-Sun Chung. "Hierarchical Request-Size-Aware Flash Translation Layer Based on Page-Level Mapping." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950117. http://dx.doi.org/10.1142/s0218126619501172.

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Owing to the increasing Internet population, there has been an explosion in the amount of digital data generated and also an increase in data complexity. This trend is called big data paradigm. As the Internet of Things (IoT) takes center stage, the growth of data will continue to increase. Therefore, the demand for mass storage devices that have high access speed is increasing. Industry has been paying attention to flash memories that can process large amounts of data at high speed. It will be a good alternative for storing and processing ever-increasing amounts of data because of low power consumption, high shock resistance, portability and fast access speed. However, the write speed is about 10–20 times slower than the read speed in flash memory. In addition, write operations are not allowed to be performed with in-place updates. Garbage collection mechanism is proposed in order to solve the problem incurred by the not-in-place update property of write operations. However, garbage collection mechanism unavoidably causes overhead of additional internal operations, which leads to performance degradation. In this paper, to prevent performance degradation caused by garbage collection, we propose a request-size-aware flash translation layer (RSaFTL) and a hierarchical request-size-aware flash translation layer (HiRSaFTL). They are designed based on page-level address translation. In RSaFTL and HiRSaFTL, page-sized data with high temporal locality cluster into a special area called active blocks by exploiting the property of realistic traces. As a result of the experiments, RSaFTL and HiRSaFTL reduce the number of pages migrated during garbage collections by up to 17.9% and 21.3%, respectively, compared with pure page-level flash transition layer.

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29

Wu, Chin-Hsien, Hsin-Hung Lin, and Tei-Wei Kuo. "An Adaptive Flash Translation Layer for High-Performance Storage Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 6 (2010): 953–65. http://dx.doi.org/10.1109/tcad.2010.2048362.

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30

Shim, Gyudong, Youngwoo Park, and Kyu Ho Park. "A hybrid flash translation layer with adaptive merge for SSDs." ACM Transactions on Storage 6, no. 4 (2011): 1–27. http://dx.doi.org/10.1145/1970338.1970339.

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31

Liu, Jiakun, and Wonyong Sung. "COPR: a cost-oriented recycling policy for flash translation layer." IEEE Transactions on Consumer Electronics 56, no. 2 (2010): 673–81. http://dx.doi.org/10.1109/tce.2010.5505987.

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32

Bai, Shi, Jie Yin, Gang Tan, Yu-Ping Wang, and Shi-Min Hu. "FDTL: a unified flash memory and hard disk translation layer." IEEE Transactions on Consumer Electronics 57, no. 4 (2011): 1719–27. http://dx.doi.org/10.1109/tce.2011.6131146.

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33

Liu, Chien-Yu, Ying-Shiuan Pan, Hsin-Hung Chen, Ying-Chih Wu, and Da-Wei Chang. "Techniques for improving performance of the FAST (fully-associative sector translation) flash translation layer." IEEE Transactions on Consumer Electronics 57, no. 4 (2011): 1740–48. http://dx.doi.org/10.1109/tce.2011.6131149.

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34

Choi, Hwan-Pil, and Yong-Seok Kim. "An Efficient Cache Management Scheme of Flash Translation Layer for Large Size Flash Memory Drives." Journal of the Korea Society of Computer and Information 20, no. 11 (2015): 31–38. http://dx.doi.org/10.9708/jksci.2015.20.11.031.

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35

Kwon, Se Jin, Hyung-Ju Cho, and Tae-Sun Chung. "Hybrid Associative Flash Translation Layer for the Performance Optimization of Chip-Level Parallel Flash Memory." ACM Transactions on Storage 9, no. 4 (2013): 1–24. http://dx.doi.org/10.1145/2535931.

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36

PARK, Dongchul, Biplob DEBNATH, and David H. C. DU. "A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping." IEICE Transactions on Information and Systems E99.D, no. 6 (2016): 1502–11. http://dx.doi.org/10.1587/transinf.2015edp7406.

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37

Boukhobza, Jalil, Pierre Olivier, and Stéphane Rubini. "A Scalable and Highly Configurable Cache-Aware Hybrid Flash Translation Layer." Computers 3, no. 1 (2014): 36–57. http://dx.doi.org/10.3390/computers3010036.

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38

Wang, Wei, and Tao Xie. "PCFTL: A Plane-Centric Flash Translation Layer Utilizing Copy-Back Operations." IEEE Transactions on Parallel and Distributed Systems 26, no. 12 (2015): 3420–32. http://dx.doi.org/10.1109/tpds.2014.2371022.

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39

Baek, SeungJin, MinSoo Park, and Tae-Sun Chung. "A Reliable and Efficient Recovery Scheme for Flash Translation Layer Algorithms." Advanced Science Letters 22, no. 11 (2016): 3356–59. http://dx.doi.org/10.1166/asl.2016.7870.

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40

Shen, Zhaoyan, Xin Li, Lei Ju, and Zhiping Jia. "A real-time flash translation layer via adaptive partial garbage collection." International Journal of Embedded Systems 6, no. 2/3 (2014): 167. http://dx.doi.org/10.1504/ijes.2014.063814.

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41

Shin, Ilhoon. "Applying Background Garbage Collection to the SBAST Flash Translation Layer Scheme." International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 1 (2015): 294–97. http://dx.doi.org/10.17762/ijritcc2321-8169.150160.

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42

Wu, Chin-Hsien. "A self-adjusting flash translation layer for resource-limited embedded systems." ACM Transactions on Embedded Computing Systems 9, no. 4 (2010): 1–26. http://dx.doi.org/10.1145/1721695.1721697.

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43

Shin, Ilhoon. "Reducing computational overhead of flash translation layer with hashed page tables." IEEE Transactions on Consumer Electronics 56, no. 4 (2010): 2344–49. http://dx.doi.org/10.1109/tce.2010.5681110.

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44

Park, Jung-Wook, Seung-Ho Park, Charles C. Weems, and Shin-Dug Kim. "A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk." Microprocessors and Microsystems 35, no. 1 (2011): 48–59. http://dx.doi.org/10.1016/j.micpro.2010.08.001.

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45

Chang, Yuan-Hao, Ming-Chang Yang, Tei-Wei Kuo, and Ren-Hung Hwang. "A reliability enhancement design under the flash translation layer for MLC-based flash-memory storage systems." ACM Transactions on Embedded Computing Systems 13, no. 1 (2013): 1–28. http://dx.doi.org/10.1145/2512467.

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46

Chang, Yuan-Hao, Ming-Chang Yang, Tei-Wei Kuo, and Ren-Hung Hwang. "A reliability enhancement design under the flash translation layer for MLC-based flash-memory storage systems." ACM Transactions on Embedded Computing Systems 13, no. 1 (2013): 1–28. http://dx.doi.org/10.1145/2501626.2512467.

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47

Hung, Ji Jun, Kai Bu, Zhao Lin Sun, Jie Tao Diao, and Jian Bin Liu. "PCI Express-Based NVMe Solid State Disk." Applied Mechanics and Materials 464 (November 2013): 365–68. http://dx.doi.org/10.4028/www.scientific.net/amm.464.365.

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This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

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48

Forouhar, Peyman, and Farshad Safaei. "Increasing the Lifetime of Flash Memory Based SSDs by Improving the Merge Operation in Flash Translation Layer." IEEE Access 8 (2020): 134324–33. http://dx.doi.org/10.1109/access.2020.3010804.

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49

Kwon, Se Jin. "A Cache-Based Flash Translation Layer for TLC-Based Multimedia Storage Devices." ACM Transactions on Embedded Computing Systems 15, no. 1 (2016): 1–28. http://dx.doi.org/10.1145/2820614.

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50

Shin, Ilhoon. "Performance Evaluation of Flash Translation Layer Considering Utilization and Dynamic Over-provisioning." International Journal of Control and Automation 7, no. 6 (2014): 169–76. http://dx.doi.org/10.14257/ijca.2014.7.6.17.

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