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Relevant bibliographies by topics / Flip Chip Ball Grid Array

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Journal articles
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Academic literature on the topic 'Flip Chip Ball Grid Array'

Author: Grafiati

Published: 3 June 2025

Last updated: 7 July 2025

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Journal articles on the topic "Flip Chip Ball Grid Array"

1

Reddy, Vishnu V. B., Jaimal Williamson, and Suresh K. Sitaraman. "Measurement Capability of Laser Ultrasonic Inspection System for Evaluation of Ball-Grid Array Package Solder Balls." Journal of Microelectronics and Electronic Packaging 18, no. 4 (2021): 183–89. http://dx.doi.org/10.4071/imaps.1501802.

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Abstract Laser ultrasonic inspection is a novel, noncontact, and nondestructive technique to evaluate the quality of solder interconnections in microelectronic packages. In this technique, identification of defects or failures in solder interconnections is performed by comparing the out-of-plane displacement signals, which are produced from the propagation of ultrasonic waves, from a known good reference sample and sample under test. The laboratory-scale dual-fiber array laser ultrasonic inspection system has successfully demonstrated identifying the defects and failures in the solder interconnections in advanced microelectronic packages such as chip-scale packages, plastic ball grid array packages, and flip-chip ball grid array packages. However, the success of any metrology system depends upon precise and accurate data to be useful in the microelectronic industry. This paper has demonstrated the measurement capability of the dual-fiber array laser ultrasonic inspection system using gage repeatability and reproducibility analysis. Industrial flip-chip ball grid array packages have been used for conducting experiments using the laser ultrasonic inspection system and the inspection data are used to perform repeatability and reproducibility analysis. Gage repeatability and reproducibility studies have also been used to choose a known good reference sample for comparing the samples under test.

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2

Su, Ay, and Yi-Wei Liu. "Thermal analysis of flip chip plastic ball grid array assembly." Heat Transfer?Asian Research 33, no. 6 (2004): 371–82. http://dx.doi.org/10.1002/htj.20026.

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3

Dudek, Rainer, Ralf Do¨ring, and Bernd Michel. "Reliability Prediction of Area Array Solder Joints." Journal of Electronic Packaging 125, no. 4 (2003): 562–68. http://dx.doi.org/10.1115/1.1604802.

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Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogeneity of the cyclic temperature fields, simplified creep characterization of solder, and the related application of Manson-Coffin failure criteria, are discussed in the paper. The packages chosen for detailed analyses are a PBGA 272 and a FC-CSP 230.

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4

Arnold, Joelle, Steph Gulbrandsen, and Nathan Blattau. "Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices." International Symposium on Microelectronics 2014, no. 1 (2014): 000112–16. http://dx.doi.org/10.4071/isom-ta43.

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The risk of damage caused by reballing SnPb eutectic solder balls onto a commercial off-the-shelf (COTS) active flip chip with a ball grid array (BGA) of SAC305 was studied. The effects of reballing performed by five different reballers were examined and compared. The active flip chip device selected included manufacturer specified resistance between eight (8) differential port pairs. The path resistance between these pins following reballing, as compared to an unreballed device, was used to assess damage accumulation in the package. 2-dimensional x-ray microscopy, acoustic microscopy, and x-ray computer tomography were also used to characterize the effects of reballing. These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices in the same application.

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Yuan, Guo Zheng, Xia Chen, and Xue Feng Shu. "Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test." Advanced Materials Research 936 (June 2014): 628–32. http://dx.doi.org/10.4028/www.scientific.net/amr.936.628.

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The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

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Ramakrishna, K., and T. Y. Tom Lee. "Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array Packages." Journal of Electronic Packaging 126, no. 4 (2004): 449–56. http://dx.doi.org/10.1115/1.1827260.

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Enhancements to thermal performance of FC-PBGA packages due to underfill thermal conductivity, controlled collapse chip connection (C4) pitch, package to printed wiring board (PWB) interconnection through thermal balls, a heat spreader on the backside of the die, and an overmolded die with and without a heat spreader have been studied by solving a conjugate heat transfer problem. These enhancements have been investigated under natural and forced convection conditions for freestream velocities up to 2 m/s. The following ranges of parameters have been covered in this study: substrate size: 25–35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), underfill thermal conductivity: 0.6–3.0 W/(m K), C4 pitch: 250 μm and below, no thermal balls to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of a bare and an overmolded die. Based on our previous work, predictions in this study are expected to be within ±10% of measured data. The conclusions of the study are: (i) Thermal conductivity of the underfill in the range 0.6 to 10 W/(m K) has negligible effect on thermal performance of FC-PBGA packages investigated here. (ii) Thermal resistances decrease 12–15% as C4 pitch decreases below 250 μm. This enhancement is smaller with increase in die area. (iii) Thermal balls connected to the PTHs in the PWB decrease thermal resistance of the package by 10–15% with 9×9 array of thermal balls and PTHs compared to no thermal balls. The effect of die size on this enhancement is more noticeable on junction to board thermal resistance, Ψjb, than the other two package thermal metrics. (iv) Heat spreader on the back of the die decreases junction-to-ambient thermal resistance, Θja, by 6% in natural convection and by 25% in forced convection. (v) An overmolded die with a heat spreader provides better a thermal enhancement than a heat spreader on a bare die for freestream velocities up to about 1 m/s. Beyond 1 m/s, a heat spreader on bare die has better thermal performance.

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Hung, Hao-Hsi, Yu-Chi Cheng, Sheng-Jye Hwang, et al. "Effect of flip-chip ball grid array structure on capillary underfill flow." Results in Engineering 23 (September 2024): 102527. http://dx.doi.org/10.1016/j.rineng.2024.102527.

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Kandasamy, Ravi, and A. S. Mujumdar. "Thermal analysis of a flip chip ceramic ball grid array (CBGA) package." Microelectronics Reliability 48, no. 2 (2008): 261–73. http://dx.doi.org/10.1016/j.microrel.2007.05.005.

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Jen, Ming-Hwa R., Lee-Cheng Liu, and Jenq-Dah Wu. "Flip-Chip Ball Grid Array Lead-Free Solder Joint Under Reliability Test." Journal of Electronic Packaging 127, no. 4 (2005): 446–51. http://dx.doi.org/10.1115/1.2070090.

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The work is aimed to investigate the mechanical responses of bare dies of the combination of pure tin∕Al–NiV–Cu Under bump metallization (UBM) and packages of pure tin∕Al–NiV–Cu UBM/substrate of standard thickness of aurum. The mechanical properties under multiple reflow and long term high temperature storage test (HTST) tests at different temperatures and the operational life were obtained. A scanning electron microscope was used to observe the growth of IMC and the failure modes in order to realize their reaction and connection. From the empirical results of bare dies, the delamination between IMC and die was observed due to the tests at 260 °C multiple reflow. However, their mechanical properties were not affected. Nevertheless, the bump shear strength of bare dies were decreased by HTST tests. In package, all the results of mechanical properties by multiple reflow test and HTST test were significantly lowered. It was shown that the adhesion between bump and die reduced obviously as tests going on. As for high temperature operational life test in the conditions of 150 °C and 320 mA (5040A∕cm2), the average stable service time of the package was 892 h, and the average ultimate service time of the package was 1053 h.

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Bachman, Mark A., Jerry Liao, John Osenbach, Zafer Kutlu, Jaeyun Gim, and Danny Brady. "Large Die Size Lead Free Flip Chip Ball Grid Array Packaging Considerations for 40nm Fab Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 000570–85. http://dx.doi.org/10.4071/2012dpc-ta23.

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To reduce the RC latency, leading edge silicon nodes employ porous SiO2 dielectrics in the interconnect stack. Introduction of porosity lowers the dielectric constant, k, but also significantly decreases both the elastic modulus and fracture toughness of the dielectric. As such, devices manufactured in silicon processes that use low K (90nm, 65nm, and 55nm) and even more so extremely low K ( 45nm, 40nm, and 28nm) interlayer dielectrics are substantially more prone to fracture as a result of package induced stresses than non porous higher K dielectrics. Since the package stresses scale with die size and package body size and inversely with bump pitch, manufacture of large die and package size flip chip devices made with extremely low K dielectrics has proven to be challenging. The stress challenge is further exacerbated by the RoHS requirements for lead free packaging which requires higher process temperatures and somewhat higher yield point solders. The combination of increased stress and reduced mechanical robustness of porous dielectrics has lead to significant reliability and assembly yield issues that have in some cases slowed the introduction of 45nm and 40nm large die lead free flip chip into the market. The work summarized in this paper shows that devices designed to withstand stresses in combination with appropriate assembly processes and bill of materials, yield highly reliable, lead free flip chip packaged devices, with die sizes greater than 400mm2 and package sizes greater than 42.5mm on a side in commercial assembly production lines.

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Dissertations / Theses on the topic "Flip Chip Ball Grid Array"

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Huang, Xingjia. "Investigation and analysis on the solder ball shear strength of plastic ball grid array, chip scale, and flip chip packages with eutectic Pb-Sn and Pb-free solders /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?MECH%202003%20HUANG.

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Tang, Zhenming. "Interfacial reliability of Pb-free flip-chip BGA package." Diss., Online access via UMI:, 2008.

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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.<br>Includes bibliographical references.

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Hariharan, Ganesh Lall Pradeep. "Models for thermo-mechanical eliability trade-offs for ball grid array and flip chip packages in extreme environments." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2006%20Fall/Theses/HARIHARAN_GANESH_55.pdf.

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Kpobie, Wiyao. "Modélisation 3D d'assemblages flip chip pour la fiabilisation des composants électroniques à haute valeur ajoutée de la famille "More than Moore." Thesis, Université de Lorraine, 2014. http://www.theses.fr/2014LORR0236/document.

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La technologie flip chip est de plus en plus répandue dans l'industrie électronique [trois dimensions (3D) System in Package] et est principalement utilisée pour la fabrication de réseaux détecteurs de grand format (mégapixels) et faible pas. Pour étudier la fiabilité de ces assemblages, des simulations numériques basées sur des méthodes d'éléments finis semblent être l'approche la moins chère. Cependant, de très grands assemblages contiennent plus d'un million de billes de brasure, et le processus d'optimisation de ces structures par des simulations numériques se révèle être une tâche très fastidieuse. Dans de nombreuses applications, la couche d'interconnexion de tels assemblages flip chip se compose de microbilles de brasure noyées dans de l'époxy. Pour ces configurations, nous proposons une approche alternative, qui consiste à remplacer cette couche d'interconnexion hétérogène par un matériau homogène équivalent (MHE). Un modèle micromécanique pour l'estimation de ses propriétés thermoélastiques équivalentes a été mis au point. La loi de comportement obtenue pour le MHE a ensuite été implémentée dans le logiciel par éléments finis (Abaqus®). Les propriétés élastiques des matériaux de l'assemblage sont définies par la littérature et également déterminées expérimentalement par une méthode de caractérisation mécanique : la nano-indentation. Les réponses thermomécaniques des assemblages testés soumis à des chargements correspondant aux conditions de fabrication ont été analysées. La technique d'homogénéisation-localisation a permis d'estimer les valeurs moyennes des contraintes et des déformations dans chaque phase de la couche d'interconnexion. Pour accéder plus précisément aux champs de contraintes et déformations dans ces phases, deux modèles de zoom structurel (couplage de modèles et submodeling), en tenant compte de la géométrie réelle de la bille de brasure, ont été testés. Les champs de contrainte et de déformation locaux obtenus corroborent avec les initiations de dommage observées expérimentalement sur les billes de brasure<br>Flip chip technology is increasingly prevalent in electronics assembly [threedimensional (3D) system in package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The constitutive law of the HEM obtained was then implemented in finite-element software (Abaqus®). Elastic properties of materials that compose the assembly were found in literature and by using mechanical characterization method especially nano-indentation. Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization-localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely to the stress and strain fields in these phases, two models of structural zoom (model coupling and submodeling), taking into account the real solder bump geometry, have been tested. The local stress and strain fields obtained corroborate the experimentally damage initiation of the solder bumps observed

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Paydenkar, Chetan S. "Flip chip assembly process development, process characterization, and reliability assessment of polymer stud grid array-chip scaled package." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/19141.

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Panchagade, Dhananjay R. "Damage prediction of lead free ball grid array packages under shock and drop environment." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Spring%20Dissertations/PANCHAGADE_DHANANJAY_35.pdf.

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Gong, Jie. "Quality assessments of solder bump interconnections in ball grid array packages using laser ultrasonics and laser interferometer." Diss., Georgia Institute of Technology, 2016. http://hdl.handle.net/1853/54914.

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Surface mount devices (SMDs), such as flip chip packages and ball grid array (BGA) packages are gaining in popularity in microelectronics industry because they provide high density inputs/outputs, better electrical and thermal performance. However, these solder bump interconnections in SMDs are sandwiched between the silicon die and the substrate, which makes them challenging to be inspected. Current non-destructive solder bump inspection techniques like electrical testing, X-ray and acoustic microscopy have some application gaps. New solder bump inspection technique is urgently needed to fill these gaps. Previous work has shown the potential of using a non-contact, non-destructive laser ultrasonics and laser interferometer based inspection system for assessing solder bump qualities. The system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages and a laser interferometer to measure the transient out-of-plane displacement on the package surface. The quality of the solder bumps can be evaluated by analyzing the out-of-plane displacement. However, there are still some gaps that need to be addressed before the system is ready on the shelf. This dissertation focuses on addressing some of these existing issues. The research work consists of the following: 1) a control interface was developed to integrate all the different modules to achieve automation. 2) a new signal-processing method for analyzing the transient out-of-plane displacement signals without requiring a known-good reference chip was developed. 3) the application scope of the system was expanded to inspect the second level solder bumps in BGA packages. Two types of process-induced defects including poor-wetting and solder bump voids were investigated. Meanwhile, solder bump fatigue caused by cyclic mechanical bending and thermal cycle was also studied using this system. 4) a finite element analysis was performed to study the thermo-mechanical reliability of solder bumps in PBGA package under cyclic thermal loads. The successful completion of the research objectives has led to a laser ultrasound solder bump inspection system prototype with more user-friendliness, higher throughputs, better repeatability and more flexibility, which accelerate the commercialization the system.

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Ng, Siu Lung. "Effect of thermal and mechanical factors on single and multi-chip BGA packages." Diss., Online access via UMI:, 2007.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.

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Chen-JungWong and 翁振榮. "Reliability of Flip Chip-Plastic Ball Grid Array Package." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54558979279914245759.

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碩士<br>國立成功大學<br>機械工程學系碩博士班<br>100<br>We used Mechanic APDL(ANSYS 12.0) to build three types of the leaded(Sn37Pb) and lead-free(Sn3.8Ag0.7Cu) solder of the flip-chip plastic ball grid array. These three types are: Type1 (no heat spreader and no molding compound), Type2 (added molding compound with no heat spreader), Type3 (added heat spreader and molding compound).The model set the chip center as the original point, and both X and Y directions are Geometric symmetry, so that the model is a quarter of the entire model. There are totally 90 minutes to proceed the temperature cycling test(TCT) simulation with 30 minutes for each cycle. In the simulations, all the solder bumps and the solder balls are modeled as nonlinear visco-plastic, and time and temperature dependent material based on Anand's constitutive equation, and other materials are treated as linear elasticity. This study uses Modified Coffin-Manson To analyze the fatigue life of the solder joint with plastic strain results from finite element simulations, and finds out the maximum and minimum stress-load and thermal strain on the solder joint. Comparing the effect of fatigue life of leaded or non-leaded solder joint with different types was then performed in this thesis.

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Yi-wei, Liu, and 劉怡威. "Thermal Analysis of Flip Chip -Plastic Ball Grid Array Assembly." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/51320434324780394856.

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碩士<br>元智大學<br>機械工程研究所<br>89<br>The steady-state thermal performance of the 164-Lead flip chip plastic ball grid array (FC-PBGA) under low to moderate convective air cooling conditions has been simulated through computational fluid dynamics (CFD) methods with CFX. Package with three different substrates were investigated. Package performance has been presented in the form of a linear relationship between the normalized junction to ambient thermal parameter (θJA) verses the normalized board to ambient thermal parameter (θJB). Results cast in the form represent a first order thermal figure of merit for packages. Such a figure of merit can be used to rank in a consistent manner the thermal performance of different package types.

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Book chapters on the topic "Flip Chip Ball Grid Array"

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Jen, Yi-Ming, Hsi Hsin Chien, Tsung-Shu Lin, and Shih Hsiang Huang. "Effect of Lid Materials on the Solder Ball Reliability of Thermally Enhanced Flip-Chip Plastic Ball Grid Array Packages." In Fracture and Strength of Solids VI. Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-989-x.1043.

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Ținca, Iulia-Eliza. "Optimized FE Model for System-Level Solder Joint Reliability Analysis of a Flip-Chip Ball Grid Array Package." In New Advances in Mechanisms, Mechanical Transmissions and Robotics. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-60076-1_26.

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Conference papers on the topic "Flip Chip Ball Grid Array"

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Wen, Jing, Jinyang Su, Canwen Wang, Siyuan Lu, Liancheng Wang, and Wenhui Zhu. "Novel Copper Foam/Indium Composite Thermal Interface Materials for Advanced Flip Chip Ball Grid Array Packaging." In 2024 25th International Conference on Electronic Packaging Technology (ICEPT). IEEE, 2024. http://dx.doi.org/10.1109/icept63120.2024.10668639.

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Hsieh, Ming-Che, Pu-Shan Huang, Chi-Yuan Chen, et al. "Characterizations of Metal-based Thermal Interface Materials (TIM) in a Singulated Flip Chip Ball Grid Array Package." In 2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC). IEEE, 2024. http://dx.doi.org/10.1109/estc60143.2024.10712026.

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Beh, Keh, Wei Loh, Jenn Leong, and Wooi Tan. "Compressive Load Challenges on Sub 1.00 Ball Pitch for Flip Chip Ball Grid Array (FCBGA)." In 2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis. IEEE, 2005. http://dx.doi.org/10.1109/hdp.2005.251405.

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Beh, Keh Shin, Wei Keat Loh, Jenn Seong Leong, and Wooi Aun Tan. "Solder Joint Reliability Challenges in Sub 1.00 mm Ball Pitch for Flip Chip Ball Grid Array." In ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73216.

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FCBGA is an electronic package used to achieve a high Inputs/Outputs (I/Os). To continue to achieve a higher I/O count without increasing package size, ball pitch reduction is inevitable. However, ball pitch reduction using smaller ball size has posed substantial challenges to solder joint reliability (SJR). On top of that, rising power dissipation requirement in FCBGA package has created a need for high performance heat sinks. These heat sinks require significant compression loading to ensure good thermal conductance of thermal interface materials. The impact of these loads on SJR has typically not been considered in thermal cycle stressing. Hence, this paper focuses on different types of heat sinks and their compressive load effect on solder joint thermal fatigue performance. It also covers package size and board thickness effect when heat sink compressive load is taken into account during thermal stressing. Lastly, lead free and eutectic solders at sub 1.00mm ball pitch technology were also evaluated.

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Kar, Y. B., N. A. Talik, Foong Chee Seng, Leong Hung Yang, R. Vithyacharan, and Tan Chou Yong. "Flux residue cleaning process optimization effect on Flip Chip Ball Grid Array reliability." In 2012 IEEE 14th Electronics Packaging Technology Conference - (EPTC 2012). IEEE, 2012. http://dx.doi.org/10.1109/eptc.2012.6507154.

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Lee, Kang-Wook, Stephane Barbeau, Francois Racicot, et al. "Electrochemical reactions in solder mask of flip chip-plastic ball grid array package." In 2013 IEEE 63rd Electronic Components and Technology Conference (ECTC). IEEE, 2013. http://dx.doi.org/10.1109/ectc.2013.6575876.

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Chen, Eric, Rick Ye, Wen-Yu Teng, Yu-Cheng Pei, and Yu-Po Wang. "Study of Solder Resist Crack Resistance for Flip Chip Ball Grid Array Substrate." In 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC). IEEE, 2023. http://dx.doi.org/10.1109/ectc51909.2023.00260.

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Uchibori, Chihiro J., Michael Lee, Xeufeng Zhang, and Paul S. Ho. "Chip Package Interaction analysis for Cu/Ultra low-k large die Flip Chip Ball Grid Array." In 2008 IEEE 9th VLSI Packaging Workshop of Japan. IEEE, 2008. http://dx.doi.org/10.1109/vpwj.2008.4762216.

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Erdahl, Dathan S., Sheng Liu, and I. Charles Ume. "Application of a Novel Flip Chip Solder Joint Inspection System to Chips on an FR-4 Substrate." In ASME 2000 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2000. http://dx.doi.org/10.1115/imece2000-2262.

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Abstract Because the trend in electronic interconnection technology is toward the development of solder bump technologies, that include flip chips, chip scale packages, multi-chip modules (MCMs), and ball grid array (BGA) packages, solder bump inspection methods must be developed to allow rapid, accurate, and high resolution on-line inspection of joint quality. Although traditional methods can detect some manufacturing defects, they do not actually test the mechanical quality of the connection. A novel solder-joint inspection system has been developed based on laser ultrasound and interferometric techniques. A pulsed laser generates ultrasound on the chip’s surface and the whole chip is excited into vibration modes. An interferometer is used to measure the vibration displacement of the chip’s surface. Solder joints with different qualities cause different vibration responses, acting as constraints on the system. The system was used to inspect the quality of solder joints on a group of flip chips mounted on FR-4 substrates, and the results show the ability of the system to detect defects such as missing solder balls, cracked chips, and gross misalignment.

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Zhang, Leilei, and Lan Hoang. "Build Up Material Effect on High Performance Flip Chip Ball Grid Array Package Reliability." In 2006 7th International Conference on Electronic Packaging Technology. IEEE, 2006. http://dx.doi.org/10.1109/icept.2006.359846.

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