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Huang, Xingjia. "Investigation and analysis on the solder ball shear strength of plastic ball grid array, chip scale, and flip chip packages with eutectic Pb-Sn and Pb-free solders /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?MECH%202003%20HUANG.
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Tang, Zhenming. "Interfacial reliability of Pb-free flip-chip BGA package." Diss., Online access via UMI:, 2008.
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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.<br>Includes bibliographical references.
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Hariharan, Ganesh Lall Pradeep. "Models for thermo-mechanical eliability trade-offs for ball grid array and flip chip packages in extreme environments." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2006%20Fall/Theses/HARIHARAN_GANESH_55.pdf.
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Kpobie, Wiyao. "Modélisation 3D d'assemblages flip chip pour la fiabilisation des composants électroniques à haute valeur ajoutée de la famille "More than Moore." Thesis, Université de Lorraine, 2014. http://www.theses.fr/2014LORR0236/document.
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La technologie flip chip est de plus en plus répandue dans l'industrie électronique [trois dimensions (3D) System in Package] et est principalement utilisée pour la fabrication de réseaux détecteurs de grand format (mégapixels) et faible pas. Pour étudier la fiabilité de ces assemblages, des simulations numériques basées sur des méthodes d'éléments finis semblent être l'approche la moins chère. Cependant, de très grands assemblages contiennent plus d'un million de billes de brasure, et le processus d'optimisation de ces structures par des simulations numériques se révèle être une tâche très fastidieuse. Dans de nombreuses applications, la couche d'interconnexion de tels assemblages flip chip se compose de microbilles de brasure noyées dans de l'époxy. Pour ces configurations, nous proposons une approche alternative, qui consiste à remplacer cette couche d'interconnexion hétérogène par un matériau homogène équivalent (MHE). Un modèle micromécanique pour l'estimation de ses propriétés thermoélastiques équivalentes a été mis au point. La loi de comportement obtenue pour le MHE a ensuite été implémentée dans le logiciel par éléments finis (Abaqus®). Les propriétés élastiques des matériaux de l'assemblage sont définies par la littérature et également déterminées expérimentalement par une méthode de caractérisation mécanique : la nano-indentation. Les réponses thermomécaniques des assemblages testés soumis à des chargements correspondant aux conditions de fabrication ont été analysées. La technique d'homogénéisation-localisation a permis d'estimer les valeurs moyennes des contraintes et des déformations dans chaque phase de la couche d'interconnexion. Pour accéder plus précisément aux champs de contraintes et déformations dans ces phases, deux modèles de zoom structurel (couplage de modèles et submodeling), en tenant compte de la géométrie réelle de la bille de brasure, ont été testés. Les champs de contrainte et de déformation locaux obtenus corroborent avec les initiations de dommage observées expérimentalement sur les billes de brasure<br>Flip chip technology is increasingly prevalent in electronics assembly [threedimensional (3D) system in package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The constitutive law of the HEM obtained was then implemented in finite-element software (Abaqus®). Elastic properties of materials that compose the assembly were found in literature and by using mechanical characterization method especially nano-indentation. Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization-localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely to the stress and strain fields in these phases, two models of structural zoom (model coupling and submodeling), taking into account the real solder bump geometry, have been tested. The local stress and strain fields obtained corroborate the experimentally damage initiation of the solder bumps observed
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Paydenkar, Chetan S. "Flip chip assembly process development, process characterization, and reliability assessment of polymer stud grid array-chip scaled package." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/19141.
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Panchagade, Dhananjay R. "Damage prediction of lead free ball grid array packages under shock and drop environment." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Spring%20Dissertations/PANCHAGADE_DHANANJAY_35.pdf.
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Gong, Jie. "Quality assessments of solder bump interconnections in ball grid array packages using laser ultrasonics and laser interferometer." Diss., Georgia Institute of Technology, 2016. http://hdl.handle.net/1853/54914.
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Surface mount devices (SMDs), such as flip chip packages and ball grid array (BGA) packages are gaining in popularity in microelectronics industry because they provide high density inputs/outputs, better electrical and thermal performance. However, these solder bump interconnections in SMDs are sandwiched between the silicon die and the substrate, which makes them challenging to be inspected. Current non-destructive solder bump inspection techniques like electrical testing, X-ray and acoustic microscopy have some application gaps. New solder bump inspection technique is urgently needed to fill these gaps. Previous work has shown the potential of using a non-contact, non-destructive laser ultrasonics and laser interferometer based inspection system for assessing solder bump qualities. The system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages and a laser interferometer to measure the transient out-of-plane displacement on the package surface. The quality of the solder bumps can be evaluated by analyzing the out-of-plane displacement. However, there are still some gaps that need to be addressed before the system is ready on the shelf. This dissertation focuses on addressing some of these existing issues. The research work consists of the following: 1) a control interface was developed to integrate all the different modules to achieve automation. 2) a new signal-processing method for analyzing the transient out-of-plane displacement signals without requiring a known-good reference chip was developed. 3) the application scope of the system was expanded to inspect the second level solder bumps in BGA packages. Two types of process-induced defects including poor-wetting and solder bump voids were investigated. Meanwhile, solder bump fatigue caused by cyclic mechanical bending and thermal cycle was also studied using this system. 4) a finite element analysis was performed to study the thermo-mechanical reliability of solder bumps in PBGA package under cyclic thermal loads. The successful completion of the research objectives has led to a laser ultrasound solder bump inspection system prototype with more user-friendliness, higher throughputs, better repeatability and more flexibility, which accelerate the commercialization the system.
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Ng, Siu Lung. "Effect of thermal and mechanical factors on single and multi-chip BGA packages." Diss., Online access via UMI:, 2007.
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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.
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Chen-JungWong and 翁振榮. "Reliability of Flip Chip-Plastic Ball Grid Array Package." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54558979279914245759.
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碩士<br>國立成功大學<br>機械工程學系碩博士班<br>100<br>We used Mechanic APDL(ANSYS 12.0) to build three types of the leaded(Sn37Pb) and lead-free(Sn3.8Ag0.7Cu) solder of the flip-chip plastic ball grid array. These three types are: Type1 (no heat spreader and no molding compound), Type2 (added molding compound with no heat spreader), Type3 (added heat spreader and molding compound).The model set the chip center as the original point, and both X and Y directions are Geometric symmetry, so that the model is a quarter of the entire model. There are totally 90 minutes to proceed the temperature cycling test(TCT) simulation with 30 minutes for each cycle.
In the simulations, all the solder bumps and the solder balls are modeled as nonlinear visco-plastic, and time and temperature dependent material based on Anand's constitutive equation, and other materials are treated as linear elasticity. This study uses Modified Coffin-Manson To analyze the fatigue life of the solder joint with plastic strain results from finite element simulations, and finds out the maximum and minimum stress-load and thermal strain on the solder joint. Comparing the effect of fatigue life of leaded or non-leaded solder joint with different types was then performed in this thesis.
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Yi-wei, Liu, and 劉怡威. "Thermal Analysis of Flip Chip -Plastic Ball Grid Array Assembly." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/51320434324780394856.
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碩士<br>元智大學<br>機械工程研究所<br>89<br>The steady-state thermal performance of the 164-Lead flip chip plastic ball grid array (FC-PBGA) under low to moderate convective air cooling conditions has been simulated through computational fluid dynamics (CFD) methods with CFX. Package with three different substrates were investigated. Package performance has been presented in the form of a linear relationship between the normalized junction to ambient thermal parameter (θJA) verses the normalized board to ambient thermal parameter (θJB). Results cast in the form represent a first order thermal figure of merit for packages. Such a figure of merit can be used to rank in a consistent manner the thermal performance of different package types.
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Shuen-JrHuang and 黃舜治. "Fatigue Analysis for Free-Lead Flip-Chip Ball Grid Array Assembly." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/70524369314766450655.
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碩士<br>國立成功大學<br>機械工程學系<br>102<br>This paper uses finite element software ANSYS14.0 to analyze the Flip-Chip Ball Grid Array packaging (FCBGA) under accelerated thermal cycling loading, we observe the thermal and mechanical behaviors of the solder balls and compare their fatigue life.
First we have to use ANSYS to establish the model of FCBGA and set up the material parameters, than describe solder ball's mechanical behaviors with Anand model, after that, mesh the model and analyze it by accelerated thermal cycling loading, finally we use Coffin-Manson equation to calculate solder balls fatigue life.
We use two lead-free materials and three type of models, first compare the mechanical behaviors of the same materials' solder ball in different types, than compare the mechanical behaviors of the different materials' solder ball in same types, eventually calculate the fatigue life and investigate the effect of solder ball with different material and model.
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Liu, Lee-Cheng, and 劉立晟. "Flip-Chip Ball Grid Array Lead Free Solder Joint under Reliability Test." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/21489447602812871559.
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碩士<br>國立中山大學<br>機械與機電工程學系研究所<br>91<br>ABSTRACT
In package, it’s easy to have defects in the solder joint, for the request of environment protection, lead-free solder research is one of the most important topics now. In soldering, the adhesion, diffusion barrier, and wettability of the interface between UBM and a lead-free solder, and the caused IMC structure that are important elements to influence long-term reliability tests. The thesis is aimed to investigate the combination of pure tin/Al-NiV-Cu UBM/STD Au substrate under reliability tests.
The samples are bare dies in which the combination is pure tin/ Al-NiV-Cu UBM and packages of is pure tin/Al-NiV-Cu UBM/STD Au substrate. The goals are to realize the mechanical properties under multiple reflows and long term HTST tests with different temperatures and the operational life. We also uses SEM to observe the growth of IMC and the failure modes that help us to realize the connection between failure modes and IMC.
The results of experiment can be concluded as follows. In a bare die, 260℃multiple reflows test causes delamination between IMC and die, but doesn’t affect the mechanical properties of it, and HTST test lowers the bump shear strength of it. In package, multiple reflows test and HTST test lower the mechanical properties significantly, the result also means that the adhesion between bump and die will drop significantly as tests go on. In HTOL test with the conditions of 150℃ and 320mA, the average stable service time of the package is 892 hours, and the average ultimate service time of the package is 1,053 hours, most probable failure site is in R1 joint.
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Guo, Yu-Lun, and 郭昱綸. "Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/18454344296188222012.
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碩士<br>國立中山大學<br>機械與機電工程學系研究所<br>91<br>The thesis investigates the thermo-mechanical deformation and stress of a flip-chip package (FCBGA) via both experiment and simulation. First, Shadow Moiré is used to evaluate the warpage of a package at elevated temperature. Then we adopt the finite element method incorporated with the software ANSYS to simulate the warpage of a package and compare the obtained results with experiment at data. Then, the material properties of underfill, the thickness of die and the substrate are considered as important parameters. Their effects on stress and strain fields of package are studied.
In case of FCBGA with and without underfill, we find that FCBGA with underfill can reduce stress concentration and increase warpage of a package in comparion with FCBGA without underfill. As for FCBGA with and without heat slug, it is observed that the warpage of FCBGA with heat slug is smaller than that of FCBGA without heat slug. Both stress and strain in the packages of above two cases are similar. The parametric study about the underfill, we find that smaller modulus and CTEs of underfill can reduce the stress and strain of package. However in the consideration of thicknesses of both die and substrate, it is shown that thinner die can reduce stress and strain of package, but thinner substrate does not. So it is suggested that thicknesses of die are the thinner the better.
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Hsieh, SHUN-CHOU, and 謝順州. "Investigation into Cutting Technology during Flip Chip Ball Grid Array Assembly Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/80201457665537420172.
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碩士<br>國立高雄第一科技大學<br>機械與自動化工程研究所<br>102<br>For the past few years, semiconductor assembly is still one of the competitive products of high technical industry. With a view of high technical products’ chain, IC foundries, assembly and test subcontractors, modules assembly and SMT, produce and already overlap each other between the chains from beginning to end. Producing and researching on 2.5D / 3D IC have made industries chain cooperation and mutual symbiosis. Assembly houses must upgrade process capability and cost down plan that might to meet industries requirement.
The faster of new technology the industry can apply, the more benefits and competitive abilities it can make. This research focuses on the assembly process of flipchip devices and its influence on quality promotion of Assembly industry. The study pays attention to the sawing manufacturing process of flipchip series products because sawing plays a key role in yield. The crucial parameters and the corresponding parameter’s range of the sawing process are obtained from engineers’ knowledge. The optimal parameter of sawing is determined by Taguchi method. The confirmation experiment verifies that the average pulling force has increased and the yield of sawing to be raised up to the goal.
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Chia-FanLin and 林家帆. "Analysis of Thermal mechanical behaviors for Flip-Chip Ball Grid Array packaging." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/35475157614766907391.
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碩士<br>國立成功大學<br>機械工程學系碩博士班<br>101<br>This paper uses finite element software ANSYS14.0 to analyze the Flip-Chip Ball Grid Array packaging (FCBGA) under accelerated thermal cycling loading. We will observe the thermal mechanical behaviors of the solder balls and discuss the fatigue life of the FCBGA.
In this simulation, we first use ANSYS to establish the FCBGA model, and apply different materials to each component to finish meshing. For the nonlinearly viscoplastic property of the solder ball, the Anand’s model is used to describe the deformation of the solder ball. However, to increase the solving efficiency, linearly elastic materials can be used to describe other components. After applying accelerated thermal cycling (ATC) loads, we observe the plastic strain range of the solder ball during ATC loads. Eventually, we use the Coffin-Manson equation to predict the fatigue life and reliability of the solder ball.
Results and Discussion is divided into three parts, the first part is about the tin-lead solder ball (60Sn40Pb) analysis results. First, we observe the stress, strain and warpage distribution of each solder ball, to figure out the critical solder ball with the maximum von Mises strain, and then we analyze the stress and strain of the critical solder ball during the whole ATC loads. Eventually the Coffin-Manson equation is used to calculate the fatigue life of the solder ball.
The second part is the parameters design considering the effect of the three types of different FCBGA assembly on the fatigue life of solder ball, and the effect of different polymer components and heat spreader assembly on the fatigue life of solder balls. Analyzing the results we can understand what factors affect the fatigue life of solder ball FCBGA significantly.
The third part is the fatigue life comparison between tin-lead and lead-free solder balls. We focus on the stress, strain and hysteresis loop plot of the critical solder ball, and then compare the fatigue life between the tin-lead and lead-free materials.
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Nai-Hao, Kao, and 高迺澔. "Stress measurement and analyses of Plastic Ball Grid Array and Flip Chip packaging." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/83783432117923783010.
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碩士<br>國立臺灣大學<br>應用力學研究所<br>87<br>This study focuses on the quantitative analysis on the effect of thermal stress on plastic ball grid array and flip chip packaging. The main experimental method is a newly developed non-contact optical technique called Electronic Speckle Pattern Interferometry, ESPI.
The package consists of several different materials which posses various thermal properties. Due to these non-symmetric characteristics, a thermal stress is created on the surface of the package at process temperature, resulting in package warpage. Specific functions of ESPI, including real time and whole field recording, were used to measure the relative warpage and coefficient of thermal expansion (CTE) values under set process temperature. Observations on relative changes in package shape and the different BT substrate CTE values were also compared. Finally, the results from warpage testing were used to predict the die bending stress exerted by flip chip. The prediction can be used to prevent possible cracking during processing.
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Chen, Kuo-Hua, and 陳國華. "Multi-objective Optimization of Flip Chip Ball Grid Array Process Using Embedded Device Substrate." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/25970343355302412722.
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碩士<br>國立高雄第一科技大學<br>機械與自動化工程所<br>98<br>SOC (system on chip) and SiP (system in package) are developed for more complex and highly integrated functions in Electronic products. Even though both of them have the common characteristic of significantly reducing the package size and improving the system effectiveness, they still have their own advantages and dis-advantages. In recent years, SOC technology significantly reduces the chip number for chipset, and SiP technology integrates assembly processes for the chipset and passive components. At the moment, the mainstream of the system process technology is still dominated by multi-chips module. The flip-chip packaging technology can reach 10 3 I/O count per square centimeter. However, under the multimode system operations trends, the system process technology has to integrate the electronic circuits and components with a variety of information and communication system standards. Therefore, the I/O density level will not be able to meet the demand by the present technology.
The embedded SiP 3D packaging technology development began with active component deposited on the substrate surface and passive components embedded in the substrate. In the advanced SiP 3D technology, the active component is embedded into the substrate, which can significantly shorten the connection path between embedded passive components and active component to enhances RF performance。 The embedded SiP application is majorly for handheld communication equipment system IC. This experiment is related to embedded device substrate application in flip-chip packaging process, especially to the study of improving interface quality between chip and substrate. The problem solving is focusing on packaging materials reorganization with the conditions of flip chip thickness, underfill, solder resist at the production stage. The Taguchi and Principal Component Analysis with Fuzzy theory is used to improve flip-chip packaging quality problems such as open circuit, short circuit and delamination.
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LIU, JEN-CHIA, and 劉人嘉. "The Improvement of Ball Mount Machine by Automatic Tooling Cleaning System for Flip Chip Ball Grid Array Package." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/wd956m.
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碩士<br>國立高雄大學<br>電機工程學系--先進電子構裝技術產業研發碩士專班<br>105<br>It is the goal and direction of the engineering staff to improve the yield and production efficiency of the product by using the optimized method and the advanced equipment technology in the semiconductor manufacturing. In this paper, The tooling is automatically cleaned to reduce the tooling waiting for cleaning time and to enhance the production efficiency of the equipment .
When the ball mount machine is running in the flip chip ball grid array package, the ball tooling cleaning degree is very important.The dirty tooling will reduce the yield of the product, so the machine can automatically detect the dirty of ball tooling.The machine issues an alarm when it detects dirty, but the machine have to waiting for the operator to cleaning the tooling before it can continue to running. It will reduce production efficiency, so this paper will study the ball tooling automatic cleaning system, when the machine detects the ball tooling dirty, it can automatically clean the tooling immediately, so that machine can continue to produce, to enhance production efficiency.
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Kuan-YingChen and 陳冠縈. "The Applicability of Using Silver- 95% Alloy Wire for Hybrid Flip Chip Ball Grid Array Packages." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/11999323167683051367.
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碩士<br>國立成功大學<br>工程科學系碩士在職專班<br>103<br>The study explores the bonding capability of the silver-95% alloy wire, including the FAB (Free Air Ball) such as the ball roundness, and the first bond quality. The machine trouble shooting such as non-stick on pad, non-stick on lead, and short tail is also examined. The bonding reliability and IMC growth situations are tested and observed to evaluate the quality of the bonds.
Experimental results show that the yield of the silver-95% alloy wire FAB made by using 20mA current under the inert gas of 0.25 l/min is better. First bond parameters from the Taguchi experimental design indicate that the silver-95% alloy wire can be applied to Hybrid Flip Chip Ball Grid Array Packages because its reliability bond-ability and work-ability all pass the criteria. Moreover, the working window in descending order is gold wire〉 silver alloy wire〉 copper wire.
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Liu, Chun-Chi, and 劉鈞旗. "Optimization of Fatigue Life of the Flip Chip Ball Grid Array by Finite Element method and Taguchi Method." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/16524656746775468905.
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碩士<br>中華大學<br>機械工程學系碩士在職專班<br>99<br>Solder joint reliability is of great concern to semiconductor and electronic product manufacturers. Due to the relative size effect between solder ball and bump, the reliability of solder interconnections for large-size flip chip ball grid array (FCBGA) is investigating vigorously. The purpose of this study is to investigate the solder ball life prediction and optimum design of the large size FCBGA using finite element method and Taguchi method.
A particular FCBGA package with package size of 31×31 mm2, chip size of 18×18 mm2, eutetic solder connections considering the bilinear strain hardebing plasticity and hyperbolic sine creep model, and thermal cycling test in ranging 0 °C to 100 °C was performed the overall analysis processes to predict the solder ball life.
The most robust design of Taguchi method was applied to investigate the critical geometric parameters for optimum design of the large size FCBGA. In utilizing of DOE (design of experimental), one chosen heatsink, ball diameter, ball height, PCB thickness, core height, chip thickness, buildup height and ball upper pad diameter as paremeters to be studied. The Taguchi orthogonal array L18(21×37) was set up based on the heatsink with two levels (with and without) and the other parameters with three levels.
This study observed that (1) With heatsink provides a better life; (2) The smaller buildup thickness and solder ball diameter has a better life performance; (3) The larger ball height and pad diameter has a better life performance; (4) The level 2 of PCB thickness, core thickness and chip thickness provides a better life.
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Juang, Yung-Cheng, and 莊詠程. "On the Study of Process induced Thermal -mechanical Behaviors and Reliability for a Flip-Chip Ball Grid Array Packaging." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/03946676736817211290.
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碩士<br>國立清華大學<br>動力機械工程學系<br>97<br>Nowadays, electronic packages are developed very fast, therefore the flip-chip ball grid array package is devised for the purpose of achieving the requirements for something which is light, thin, short, small, high speed and high input/output pin counts. However the flip-chip ball grid array package, as a new technology, still has many technical challenges remaining in concern, such as the warpage behavior after the packaging process, and the low cycling thermal fatigue failure which is produced by the solder bump after the accelerated thermal cycling test. These features of the flip-chip ball grid array package in this research work worth further study.
Using the element death and birth technology and the finite element global/local analysis model, this study is first to establish an accurate three-dimensional finite element thermal-mechanical analysis model by the ANSYS finite element analysis software.Continuously,the integrated process-dependent analysis simulates for the thermal-mechanical properties which are produced from the chip with Cu/low-k layer of flip- chip ball grid array package after packaging process, including the warpage of the packaging and the strain/stress of the chip, solder bump and the different interfaces of surrounding materials. The validity of the thermal-mechanical analysis model is verified by robotic vision systems inspection (RVSI) and the Twyman-Green interferometry experiments for warpage measurement. In addition, this research explores the elasticity, plasticity and creep behaviors of the solder bump made by different materials, and predicts the fatigue life further when the flip-chip ball grid array package stays in the condition of the accelerated thermal cycling test. At last, this study investigates the effects of related process, materials and geometric parameters on the thermal-mechanical behaviors of this packaging through parametric analysis.
The achievement of this study can help us to understand the thermal-mechanical behaviors of the chip with Cu/low-k layer of flip-chip ball grid array package and the reliability under the accelerated thermal cycling test, also offer an initial design stage for electronic packaging industry.
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Chan, Hsin-Yuan, and 陳欣源. "The Effect of Underfill Materials’ Thermo-mechanical Properties on The Thermal Deformation Behavior of Low-K Flip-Chip Ball Grid Array Packages." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/93483268434641050396.
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碩士<br>國立交通大學<br>工學院半導體材料與製程產業專班<br>97<br>As the advancement of semi-conductor manufacturing technology, the IC manufacturers introduced Cu and low-K dielectric to relieve the resistance-capacitance delay (RC delay) issue. Unfortunately, the low-K dielectric material possessed weaker mechanical strength and adhesion than the traditional SiO2 dielectric, leading to increased delamination potential for low-K layer. In addition, due to the rise of environmental awareness, the conventional eutectic solder alloy Sn37Pb was gradually replaced by lead-free alloys. However, lead-free alloys required higher reflow temperature and the alloys would form Cu-Sn inter-metallic compounds with Cu pads readily, which may degrade the reliability of lead-free packages. Therefore, how to formulate the thermal and mechanical properties of underfill materials to meet the reliability requirements for low-K flip-chip ball grid array (FC-BGA) packages is one of the critical tasks in current research and development of flip-chip technology.
In this study, a high resolution Moiré interferometry (resolution up to 26 nm) was employed to measure and compare the thermo-mechanical deformation of two types of underfill materials. It could provide sufficient sensitivity to observe the thermal deformation behavior in bump/underfill layer. Based on the measurement results, the underfill material with higher elastic modulus induced larger die warpage and lower bump shear strain. In addition, we also evaluated the reliability of six FC-BGA package samples involving different underfill and solder alloys by thermal cycling tests (TCT). The TCT results indicated the package samples with high lead (Sn95Pb) and lead-free bump (Sn0.7Cu) had worse reliability than conventional Sn37Pb bump. Thus, the underfill with more rigid mechanical properties is required in order to protect solder bumps.
Furthermore, a simplified three-dimensional finite element model by ANSYSTM was also established. The die warpage difference between Moiré interferometry measurement and simulation was less than 5%. The stress simulation results by the finite element model also correlated well with aforementioned TCT results.
Finally, finite element analysis (FEA) was employed to find out the optimal mechanical properties of underfill material for low-K FC-BGA packages. The coefficient of thermal expansion (CTE), elastic modulus (E) and glass transition temperature (Tg) of underfill were the three major material properties which directly affected the reliability of FC-BGA packages. Based on FEA results, the underfill with lower CTE would decrease both stress on bumps and low-K layer. For the underfill with higher elastic modulus, it would enhance the bump protection, but induced higher stress in low-K layer. Since CTE and elastic modulus of underfill material would change drastically while environmental temperature exceeded its Tg temperature, Tg temperature was a critical materials property of underfill material. In summary, the underfill material with moderate elastic modulus, low CTE and high Tg temperature was recommended for low-K FC-BGA packages.
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Fan, Chen-Tse, and 范振澤. "A Suitability Study for the Shear and Bend Tests as substitutions for Thermal Cycling Reliability Test of Flip Chip Ball Grid Array Components." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87378753227021255570.
Full textAbstract:
碩士<br>元智大學<br>機械工程學系<br>96<br>The Accelerated Thermal Cycling(ATC) test is probably the most important and widely adopted reliability methods in various electronic packaging applications. However, it usually takes more than a thousand hours on this time-consuming test that also often causes a bottle-neck in the reliability test. As a result, mechanical stress test such as bend test and shear test, that requires much less time are used as a substitute to shorten the cycling time. However, which is the best alternative of ATC test between these two mechanical tests, deserves more detailed studies. Hence, the study conducts the theoretical mechanics analysis, failure modes analyses, and Finite Element Analysis (FEA) on the flip chip ball grid array(FCBGA) components with the bend, shear and thermal cycling test. It is expected to find, in particular, an accelerated mechanical test that can fully represent the ATC test but also compatible in the physics of package reliability.
In the theoretical analysis, a simplified Suhir’s tri-layer beam model which resembles the component’s packaging structure is utilized to evaluate interfacial normal and peeling stresses. In the mean time, the FEA of the same packaging is also conducted to simulate the bend, shear, and ATC test. An insight of the stress distributions on components under those reliability tests are obtained for the comparison purposes. Regarding the reliability test, both leaded solder material with composition of 63Sn37Pb and unleaded solder with Sn3.0Ag0.5Cu, Sn4.0Ag0.5Cu are used both in the bend and shear test.
The study showed that for the two 0.4mm and 0.525mm solder mask openings on components, the latter which with larger solder mask area has better fatigue life. Besides, the lead-free solder material is higher than that of eutectic solder materials in their average fatigue life, whereas the former has much more variations in the failed cycles no matter for cyclic bend tests or shear tests. Moreover, from the magnitude variations and the distributions of the thermal stress on the FCBGA package via the theoretical and nonlinear finite element analyses, it reveals that shear fatigue test is found to be in good agreement with the results from ATC. It is concluded that shear test should be taken as the best alternative for ATC test. The established results can be advantageous to the industry applications in the efficiency by shortening the test time and the correctness due to closer failure physics to that of ATC test.
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Phong-PhuLe and 黎楓富. "Ball-Grid-Array Chip Defects Detection and Classification Using Patch-based Modified YOLOv3." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/vyywa9.
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