Log in

Relevant bibliographies by topics / Flip Chip Ball Grid Array / Journal articles

To see the other types of publications on this topic, follow the link: Flip Chip Ball Grid Array.

Journal articles on the topic 'Flip Chip Ball Grid Array'

Author: Grafiati

Published: 3 June 2025

Last updated: 20 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Flip Chip Ball Grid Array.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Reddy, Vishnu V. B., Jaimal Williamson, and Suresh K. Sitaraman. "Measurement Capability of Laser Ultrasonic Inspection System for Evaluation of Ball-Grid Array Package Solder Balls." Journal of Microelectronics and Electronic Packaging 18, no. 4 (2021): 183–89. http://dx.doi.org/10.4071/imaps.1501802.

Full text

Abstract:

Abstract Laser ultrasonic inspection is a novel, noncontact, and nondestructive technique to evaluate the quality of solder interconnections in microelectronic packages. In this technique, identification of defects or failures in solder interconnections is performed by comparing the out-of-plane displacement signals, which are produced from the propagation of ultrasonic waves, from a known good reference sample and sample under test. The laboratory-scale dual-fiber array laser ultrasonic inspection system has successfully demonstrated identifying the defects and failures in the solder intercon

APA, Harvard, Vancouver, ISO, and other styles

2

Su, Ay, and Yi-Wei Liu. "Thermal analysis of flip chip plastic ball grid array assembly." Heat Transfer?Asian Research 33, no. 6 (2004): 371–82. http://dx.doi.org/10.1002/htj.20026.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Dudek, Rainer, Ralf Do¨ring, and Bernd Michel. "Reliability Prediction of Area Array Solder Joints." Journal of Electronic Packaging 125, no. 4 (2003): 562–68. http://dx.doi.org/10.1115/1.1604802.

Full text

Abstract:

Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogenei

APA, Harvard, Vancouver, ISO, and other styles

4

Arnold, Joelle, Steph Gulbrandsen, and Nathan Blattau. "Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices." International Symposium on Microelectronics 2014, no. 1 (2014): 000112–16. http://dx.doi.org/10.4071/isom-ta43.

Full text

Abstract:

The risk of damage caused by reballing SnPb eutectic solder balls onto a commercial off-the-shelf (COTS) active flip chip with a ball grid array (BGA) of SAC305 was studied. The effects of reballing performed by five different reballers were examined and compared. The active flip chip device selected included manufacturer specified resistance between eight (8) differential port pairs. The path resistance between these pins following reballing, as compared to an unreballed device, was used to assess damage accumulation in the package. 2-dimensional x-ray microscopy, acoustic microscopy, and x-r

APA, Harvard, Vancouver, ISO, and other styles

5

Yuan, Guo Zheng, Xia Chen, and Xue Feng Shu. "Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test." Advanced Materials Research 936 (June 2014): 628–32. http://dx.doi.org/10.4028/www.scientific.net/amr.936.628.

Full text

Abstract:

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop co

APA, Harvard, Vancouver, ISO, and other styles

6

Ramakrishna, K., and T. Y. Tom Lee. "Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array Packages." Journal of Electronic Packaging 126, no. 4 (2004): 449–56. http://dx.doi.org/10.1115/1.1827260.

Full text

Abstract:

Enhancements to thermal performance of FC-PBGA packages due to underfill thermal conductivity, controlled collapse chip connection (C4) pitch, package to printed wiring board (PWB) interconnection through thermal balls, a heat spreader on the backside of the die, and an overmolded die with and without a heat spreader have been studied by solving a conjugate heat transfer problem. These enhancements have been investigated under natural and forced convection conditions for freestream velocities up to 2 m/s. The following ranges of parameters have been covered in this study: substrate size: 25–35

APA, Harvard, Vancouver, ISO, and other styles

7

Hung, Hao-Hsi, Yu-Chi Cheng, Sheng-Jye Hwang, et al. "Effect of flip-chip ball grid array structure on capillary underfill flow." Results in Engineering 23 (September 2024): 102527. http://dx.doi.org/10.1016/j.rineng.2024.102527.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Kandasamy, Ravi, and A. S. Mujumdar. "Thermal analysis of a flip chip ceramic ball grid array (CBGA) package." Microelectronics Reliability 48, no. 2 (2008): 261–73. http://dx.doi.org/10.1016/j.microrel.2007.05.005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Jen, Ming-Hwa R., Lee-Cheng Liu, and Jenq-Dah Wu. "Flip-Chip Ball Grid Array Lead-Free Solder Joint Under Reliability Test." Journal of Electronic Packaging 127, no. 4 (2005): 446–51. http://dx.doi.org/10.1115/1.2070090.

Full text

Abstract:

The work is aimed to investigate the mechanical responses of bare dies of the combination of pure tin∕Al–NiV–Cu Under bump metallization (UBM) and packages of pure tin∕Al–NiV–Cu UBM/substrate of standard thickness of aurum. The mechanical properties under multiple reflow and long term high temperature storage test (HTST) tests at different temperatures and the operational life were obtained. A scanning electron microscope was used to observe the growth of IMC and the failure modes in order to realize their reaction and connection. From the empirical results of bare dies, the delamination betwe

APA, Harvard, Vancouver, ISO, and other styles

10

Bachman, Mark A., Jerry Liao, John Osenbach, Zafer Kutlu, Jaeyun Gim, and Danny Brady. "Large Die Size Lead Free Flip Chip Ball Grid Array Packaging Considerations for 40nm Fab Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 000570–85. http://dx.doi.org/10.4071/2012dpc-ta23.

Full text

Abstract:

To reduce the RC latency, leading edge silicon nodes employ porous SiO2 dielectrics in the interconnect stack. Introduction of porosity lowers the dielectric constant, k, but also significantly decreases both the elastic modulus and fracture toughness of the dielectric. As such, devices manufactured in silicon processes that use low K (90nm, 65nm, and 55nm) and even more so extremely low K ( 45nm, 40nm, and 28nm) interlayer dielectrics are substantially more prone to fracture as a result of package induced stresses than non porous higher K dielectrics. Since the package stresses scale with die

APA, Harvard, Vancouver, ISO, and other styles

11

Kornain, Zainudin, Azman Jalar, Rozaidi Rashid, and Shahrum Abdullah. "An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging." Advanced Materials Research 97-101 (March 2010): 23–27. http://dx.doi.org/10.4028/www.scientific.net/amr.97-101.23.

Full text

Abstract:

Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profi

APA, Harvard, Vancouver, ISO, and other styles

12

Whitchurch, Nathan, Glenn Rinne, Wei Lin, and Devarajan Balaraman. "Direct Measurement of Silicon Strain in a Fine Pitch Flip Chip BGA Package." International Symposium on Microelectronics 2017, no. 1 (2017): 000176–81. http://dx.doi.org/10.4071/isom-2017-wa14_097.

Full text

Abstract:

Abstract A method for directly measuring the silicon strain in a flip chip ball grid array (FCBGA) package is disclosed. The method uses anisotropically etched holes in the die backside to reveal fiducial crosses on the front side of the die. A geometric model is proposed that allows extraction of the strain component of the measured displacement. A finite element model is described which correctly predicts the sign and magnitude of the strain.

APA, Harvard, Vancouver, ISO, and other styles

13

Ricky Lee, Shi‐Wei, and John H. Lau. "Solder joint reliability of plastic ball grid array with solder bumped flip chip." Soldering & Surface Mount Technology 12, no. 2 (2000): 16–23. http://dx.doi.org/10.1108/09540910010312401.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Jen, Yi-Ming, Hsi Hsin Chien, Tsung-Shu Lin, and Shih Hsiang Huang. "Effect of Lid Materials on the Solder Ball Reliability of Thermally Enhanced Flip-Chip Plastic Ball Grid Array Packages." Key Engineering Materials 306-308 (March 2006): 1043–48. http://dx.doi.org/10.4028/www.scientific.net/kem.306-308.1043.

Full text

Abstract:

This research studied the thermal fatigue life for eutectic solder balls of thermally enhanced flip-chip plastic ball grid array (FC-PBGA) packages with different lid materials under thermal cycling tests. Three FC-PBGA packages with different lid materials, i.e., Al, AlSiC, and Cu, were utilized to examine the lid material effect on solder ball reliability. The cyclic stress/strain behavior for the packages was estimated by using the nonlinear finite element method. The eutectic solder was assumed to be elastic-plastic-creep. The stable stress/strain results obtained from FEM analysis were ut

APA, Harvard, Vancouver, ISO, and other styles

15

Bagetti Jeronimo, Mateus, Jens Schindele, Hubert Straub, Przemyslaw Jakub Gromala, Bernhard Wunderle, and André Zimmermann. "On the influence of lid materials for flip-chip ball grid array package applications." Microelectronics Reliability 140 (January 2023): 114869. http://dx.doi.org/10.1016/j.microrel.2022.114869.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Boon Kar, Yap, Noor Azrina Talik, Zaliman Sauli, Jean Siow Fei, and Vithyacharan Retnasamy. "Finite element analysis of thermal distributions of solder ball in flip chip ball grid array using ABAQUS." Microelectronics International 30, no. 1 (2013): 14–18. http://dx.doi.org/10.1108/13565361311298187.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Cheng, Hung-Hsiang, Cheng-Yu Wu, Hung-Chun Kuo, et al. "Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA." International Symposium on Microelectronics 2021, no. 1 (2021): 000119–23. http://dx.doi.org/10.4071/1085-8024-2021.1.000119.

Full text

Abstract:

Abstract There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV S

APA, Harvard, Vancouver, ISO, and other styles

18

Kornain, Zainudin, Azman Jalar, Rozaidi Rashid, and Shahrum Abdullah. "The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging." Key Engineering Materials 462-463 (January 2011): 1194–99. http://dx.doi.org/10.4028/www.scientific.net/kem.462-463.1194.

Full text

Abstract:

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing

APA, Harvard, Vancouver, ISO, and other styles

19

Wang, Tong Hong, Yi-Shao Lai, and Jenq-Dah Wu. "Effect of Underfill Thermomechanical Properties on Thermal Cycling Fatigue Reliability of Flip-Chip Ball Grid Array." Journal of Electronic Packaging 126, no. 4 (2004): 560–64. http://dx.doi.org/10.1115/1.1827271.

Full text

Abstract:

Plane two-dimensional finite element analysis was applied to study the effect of underfill thermomechanical properties on the potential of thermal fatigue failure for flip-chip ball grid array. Two-stage as well as constant thermomechanical properties of underfills were manipulated to represent extremes of practical underfills. The steady-state creep model was incorporated for the eutectic solder bump to represent its real behavior. It was found from the parametric studies that the underfill with high Young’s modulus, low coefficient of thermal expansion, and high glass transition temperature

APA, Harvard, Vancouver, ISO, and other styles

20

Goldmann, Lewis S. "A Model for Deformation of Solder Bumps From Ramp Loading." Journal of Electronic Packaging 118, no. 1 (1996): 37–40. http://dx.doi.org/10.1115/1.2792125.

Full text

Abstract:

A simple model is presented to predict the mechanical squashing or stretching of an axisymmetric solder joint when subjected to a ramp loading. This is a situation which can frequently arise, accidentally or by design, in the processing of flip chip solder bumps, or in surface mounted Ball Grid Array modules. Excessive squashing can have ramifications for subsequent processing or for joint reliability. The proposed method, while involving an extremely simple algorithm, has been found to agree well with experimental data, and is very general in its applicability.

APA, Harvard, Vancouver, ISO, and other styles

21

Leung, Dennis, and Guna Selvaduray. "Effect of Design Factors on Microvia Reliability of Flip Chip Ball Grid Array Polymeric Substrates." Journal of Microelectronics and Electronic Packaging 5, no. 3 (2008): 104–15. http://dx.doi.org/10.4071/1551-4897-5.3.104.

Full text

Abstract:

Microvia failures in flip chip ball grid array (FCBGA) polymeric substrates have been a major concern in the development of reliable packages for high-performance and high-density chips. To determine the relationship between reliability and design factors of the microvias, a 10-layer substrate was used to investigate these contrasting design factors: “stack-on-core” vs. “non–stack-on-core,” “high” vs. “low” aspect ratio, “stacked” vs. “staggered,” and “fillet” vs. “non-fillet.” Temperature cycling was used to generate stresses on the microvias. Electrical resistance was measured and analyzed,

APA, Harvard, Vancouver, ISO, and other styles

22

Kpobie, W., N. Bonfoh, C. Dreistadt, M. Fendler, and P. Lipinski. "Three-Dimensional Thermomechanical Simulation of Fine-Pitch High-Count Ball Grid Array Flip-Chip Assemblies." Journal of Electronic Materials 43, no. 3 (2013): 671–84. http://dx.doi.org/10.1007/s11664-013-2669-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Jie-Hua Zhao. "A probabilistic mechanics approach to die cracking prediction in flip-chip ball grid array package." IEEE Transactions on Components and Packaging Technologies 28, no. 3 (2005): 390–96. http://dx.doi.org/10.1109/tcapt.2005.853590.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Thrasher, Bradley A., William E. McKinzie, Deepukumar M. Nair, et al. "A 10 MHz to 80 GHz BGA Transition from Chip to LTCC Interposer for Chip Scale Packages." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, CICMT (2015): 000067–72. http://dx.doi.org/10.4071/cicmt-tp14.

Full text

Abstract:

Presented here are the design, fabrication, and measurement results of a low temperature cofired ceramic (LTCC) chip-to-interposer transition utilizing a flip-chip ball grid array (BGA) interconnect that provides excellent electrical performance up to and including 80 GHz. A test board fabricated in LTCC is used as the interposer substrate and another smaller LTCC part is used as a surrogate chip for demonstration purposes. The BGA chip-to-interposer transition is designed as a back-to-back pair of transitions with an assembly consisting of an LTCC interposer, an LTCC test chip, and a BGA inte

APA, Harvard, Vancouver, ISO, and other styles

25

Choi, Hyun-Seok, Jeong-Hyun Park, and Jong-Hee Lee. "The Effect of Porosity on the Thermal Conductivity of Highly Thermally Conductive Adhesives for Advanced Semiconductor Packages." Polymers 15, no. 14 (2023): 3083. http://dx.doi.org/10.3390/polym15143083.

Full text

Abstract:

This study suggests promising candidates as highly thermally conductive adhesives for advanced semiconductor packaging processes such as flip chip ball grid array (fcBGA), flip chip chip scale package (fcCSP), and package on package (PoP). To achieve an extremely high thermal conductivity (TC) of thermally conductive adhesives of around 10 Wm−1K−1, several technical methods have been tried. However, there are few ways to achieve such a high TC value except by using spherical aluminum nitride (AlN) and 99.99% purified aluminum oxide (Al2O3) fillers. Herein, by adapting highly sophisticated blen

APA, Harvard, Vancouver, ISO, and other styles

26

Chen, C. I., S. C. Wu, D. S. Liu, C. Y. Ni, and T. D. Yuan. "Global-to-Local Modeling and Experiment Investigation of HFCBGA Package Board-Level Solder Joint Reliability." Journal of Microelectronics and Electronic Packaging 4, no. 4 (2007): 186–94. http://dx.doi.org/10.4071/1551-4897-4.4.186.

Full text

Abstract:

Due to the high speed and high I/O count requirements for semiconductor packages, thousands of soldered interconnections are indispensable, and this situation renders traditional finite element method (FEM) analysis a formidable challenge. This paper presents a 3D-equivalent global model and local submodeling technique to investigate board-level solder joint reliability under cyclic temperature loading. The equivalent global model is capable of addressing critical solder failure locations. An individual local solder ball is used to predict the number of cycles to failure. The high performance

APA, Harvard, Vancouver, ISO, and other styles

27

Jalar, A., Zainudin Kornain, Rozaidi Rasid, Saifollah Abdullah, and Norinsan Kamil Othman. "The Effect of Underfill Fillet Geometry to Die Edge Stress for Flip Chip Packaging." Advanced Materials Research 148-149 (October 2010): 1108–11. http://dx.doi.org/10.4028/www.scientific.net/amr.148-149.1108.

Full text

Abstract:

The possible source of die edge cracking for Flip Chip Ceramic Ball Grid Array (FC-CBGA) package due to thermal cycling have been investigated in this study. Finite Element Analysis (FEA) models were used to analyze the effect of underfill fillet geometry on interfacial stresses between die edge and the underfill fillet. The input parameters of FC-CBGA from industry was used for simulation and the properties of commercial underfill were extracted by using Thermal Mechanical Analyzer (TMA) and Dynamic Mechanical Analyzer (DMA). Die stress distribution for different fillet height were generated

APA, Harvard, Vancouver, ISO, and other styles

28

Chiang, Kuo-Ning, and Chang-Ming Liu. "A Comparison of Thermal Stress/Strain Behavior of Elliptical/Round Solder Pads." Journal of Electronic Packaging 123, no. 2 (1999): 127–31. http://dx.doi.org/10.1115/1.1339196.

Full text

Abstract:

As electronic packaging technology moving to the CSP, wafer level packaging, fine pitch BGA (ball grid array) and high density interconnections, the wireability of the PCB/substrate and soldering technology are as important as reliability issues. In this work, a comparison of elliptical/round pads of area array type packages has been studied for soldering, reliability, and wireability requirements. The objective of this research is to develop numerical models for predicting reflow shapes of solder joint under elliptical/round pad boundary conditions and to study the reliability issue of the so

APA, Harvard, Vancouver, ISO, and other styles

29

Xu, Yu Wen, Liang Jun Liu, and Kun Jia. "Preparation and Performance Study of Thermally Conductive Silicone Adhesive Applying in Flip Chip Ball Grid Array." Key Engineering Materials 994 (November 5, 2024): 47–54. http://dx.doi.org/10.4028/p-t10ife.

Full text

Abstract:

A thermally conductive silicone adhesive UB-5715 was prepared using vinyl silicone oil of medium viscosity, hydrogen-containing silicone oil and micron alumina powder. The results revealed that UB-5715 demonstrated superior thermal and mechanical properties. Specifically, its thermal decomposition temperature exceeded 400 °C, the thermal conductivity coefficient surpassed 1.80 W/m·K, the thermal resistance was under 12.0 °C·cm2/W, the shear strength reached achieved was over 5.00 MPa. Meanwhile, after being subjected to uHAST for 384 hours, thermal cycle for 1000 times and heat aging for 1000

APA, Harvard, Vancouver, ISO, and other styles

30

Hsieh, Ming-Che, Chien Chen Lee, and Li Chiun Hung. "Comprehensive Thermo-Mechanical Stress Analyses and Underfill Selection of Large Die Flip Chip Ball Grid Array." IEEE Transactions on Components, Packaging and Manufacturing Technology 3, no. 7 (2013): 1155–62. http://dx.doi.org/10.1109/tcpmt.2012.2232712.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Zhang, H. Y., D. Pinjala, T. N. Wong, and Y. K. Joshi. "Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations." IEEE Transactions on Components and Packaging Technologies 28, no. 1 (2005): 127–35. http://dx.doi.org/10.1109/tcapt.2004.843164.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Kim, D. H., and J. Joo. "Deformation behaviors of flip chip plastic ball grid array packages subjected to temperature change using moiré interferometry." Materialwissenschaft und Werkstofftechnik 54, no. 4 (2023): 391–400. http://dx.doi.org/10.1002/mawe.202300008.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Su, F., W. J. Li, T. B. Lan, and W. Shang. "Investigation on Hygro-Thermo-Mechanical Stress of a Plastic Electronic Package." Journal of Mechanics 30, no. 6 (2014): 625–30. http://dx.doi.org/10.1017/jmech.2014.52.

Full text

Abstract:

AbstractPlastic packaging materials tend to absorb moisture from ambient environment and get swollen, this may raise hygro-stress in plastic electronic package and redistribute the internal stress. In this paper, we reviewed the dramatic deformation of a plastic package (Flip Chip Plastic Ball Grid Array-FCPBGA) due to moisture absorption first, then hygro-thermo-mechanical stress of the plastic package and its evolution during a period of three months were investigated with finite element method, user development was performed for this investigation. The finite element model was verified with

APA, Harvard, Vancouver, ISO, and other styles

34

Vanam, Kiran, Anthony Newman, Mori Poustinchi, and Stephen Stewart. "Quality Monitors and Inspection Criteria for Bare Die Flip Chip Ball Grid Array and Bare Die PoP Packages." International Symposium on Microelectronics 2014, no. 1 (2014): 000533–36. http://dx.doi.org/10.4071/isom-wa61.

Full text

Abstract:

Package form factor and cost are one of the key drivers in smart phone and tablet landscape. In order to meet these requirements hand held market has seen emergence of bare die flip chip ball grid array (BD FCBGA) and bare die package on package (BD PoP). As the name implies, these packages don't have a mold cap or heat spreader surrounding the silicon die resulting in lower cost and smaller form factor. Further package thickness reduction is possible by thinning of silicon die without significantly affecting high temperature (HT) warpage or coplanarity. One of the main concerns with aforement

APA, Harvard, Vancouver, ISO, and other styles

35

Kornain, Zainudin, A. Jalar, Rozaidi Rasid, C. S. Foong, and T. L. Wong. "Estimation of Curing Profile's Parameters for Flip Chip Packaging Using DSC and TGA." Key Engineering Materials 467-469 (February 2011): 950–55. http://dx.doi.org/10.4028/www.scientific.net/kem.467-469.950.

Full text

Abstract:

This paper presents the method to estimate curing profile's parameters for curing process of Moisture Resistance Cyanate Ester (MRCE) based underfill used in Flip Chip Ceramic Ball Grid Array (FC-CBGA). The two steps curing profile was found to eliminate voids formation in underfill during curing process. The important parameters in two steps curing profile such as first fixed temperature and duration of second temperature rise were estimated by superimposed of cure initiation curve and weight percentage loss curve of underfill epoxy material. Differential Scanning Calorimeter (DSC) analysis w

APA, Harvard, Vancouver, ISO, and other styles

36

Azid, Ishak Abdul, Lee Kor Oon, Ong Kang Eu, K. N. Seetharamu, and Ghulam Abdul Quadir. "Application of Artificial Neural Network for Fatigue Life Prediction." Key Engineering Materials 297-300 (November 2005): 96–101. http://dx.doi.org/10.4028/www.scientific.net/kem.297-300.96.

Full text

Abstract:

An extensively published and correlated solder joint fatigue life prediction methodology is incorporated by which finite element simulation results are translated into estimated cycles to failure. This study discusses the analysis methodologies as implemented in the ANSYSTM finite element simulation software tool. Finite element models are used to study the effect of temperature cycles on the solder joints of a flip chip ball grid array package. Through finite element simulation, the plastic work or the strain-energy density of the solder joints are determined. Using an established methodology

APA, Harvard, Vancouver, ISO, and other styles

37

Kornain. "Comparative Study of Different Underfill Material on Flip Chip Ceramic Ball Grid Array Based on Accelerated Thermal Cycling." American Journal of Engineering and Applied Sciences 3, no. 1 (2010): 83–89. http://dx.doi.org/10.3844/ajeassp.2010.83.89.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Suhir, Ephraim, and Reza Ghaffarian. "Flip-Chip (FC) and Fine-Pitch-Ball-Grid-Array (FPBGA) Underfills for Application in Aerospace Electronics—Brief Review." Aerospace 5, no. 3 (2018): 74. http://dx.doi.org/10.3390/aerospace5030074.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Ho, Cheng-Yu, Hung-Hsiang Cheng, Po-Chih Pan, Chen-Chao Wang, and Chih-Pin Hung. "A Novel Channel Characteristics Estimation Methodology for High-Speed SerDes Interface on Flip-Chip Ball Grid Array Packages." IEEE Transactions on Components, Packaging and Manufacturing Technology 5, no. 12 (2015): 1784–92. http://dx.doi.org/10.1109/tcpmt.2015.2478480.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Lu, Hua, Rasha Hussain, Ming Zhou, and Xijia Gu. "Fiber Bragg Grating Sensors for Failure Detection of Flip Chip Ball Grid Array in Four-Point Bend Tests." IEEE Sensors Journal 9, no. 4 (2009): 457–63. http://dx.doi.org/10.1109/jsen.2009.2014419.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Lau, J. H. "Solder joint reliability of flip chip and plastic ball grid array assemblies under thermal, mechanical, and vibrational conditions." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 19, no. 4 (1996): 728–35. http://dx.doi.org/10.1109/96.544363.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Shidore, S., V. Adams, and T. T. Lee. "A study of compact thermal model topologies in CFD for a flip chip plastic ball grid array package." IEEE Transactions on Components and Packaging Technologies 24, no. 2 (2001): 191–98. http://dx.doi.org/10.1109/6144.926382.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Kim, J. Y., and J. S. Yoon. "Image Distortion Compensation by Using a Polynomial Model in an X-Ray Digital Tomosynthesis System." Key Engineering Materials 297-300 (November 2005): 2034–39. http://dx.doi.org/10.4028/www.scientific.net/kem.297-300.2034.

Full text

Abstract:

X-ray technology has been widely used in a number of industrial applications for monitoring and inspecting inner defects which can hardly be found by normal vision systems as a ball grid array (BGA) or a flip chip array (FCA). Digital tomosynthesis (DT) is one of the most useful X-ray cross-sectional imaging methods for PCB inspection, and it usually uses an X-ray image intensifier. However, the image intensifier distorts X-ray images severely both of shape and intensity. This distortion breaks the correspondences between those images and prevents us from acquiring accurate cross-section image

APA, Harvard, Vancouver, ISO, and other styles

44

Aguirre, Jerry, Paul Garland, Marcos Vargas, Heather Tallo, and Joseph Tallo. "Comparison Between Multilayer Ceramic and Organic Package Substrates Based Upon Signal and Power Integrity." International Symposium on Microelectronics 2011, no. 1 (2011): 000905–13. http://dx.doi.org/10.4071/isom-2011-tha1-paper6.

Full text

Abstract:

Comparisons between organic and ceramic packaging is a difficult task given the considerable number of differences in material properties and potential tradeoffs between cost, electrical performance, thermal performance, and environmental factors. This paper presents a power and signal integrity comparison between a select set of multilayer organic technologies (HDBU and CPCore) and multilayer ceramic technologies (HTCC and LTCC). The geometry and material property impact on electrical performance for the flip-chip first level interconnect are qualitatively discussed and compared. The broadban

APA, Harvard, Vancouver, ISO, and other styles

45

Shih, Meng-Kai, Yu-Hao Liu, Calvin Lee, and C. P. Hung. "Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions." Materials 16, no. 12 (2023): 4291. http://dx.doi.org/10.3390/ma16124291.

Full text

Abstract:

Flip Chip Ball Grid Array (FCBGA) packages, together with many other heterogeneous integration packages, are widely used in high I/O (Input/Output) density and high-performance computing applications. The thermal dissipation efficiency of such packages is often improved through the use of an external heat sink. However, the heat sink increases the solder joint inelastic strain energy density, and thus reduces the board-level thermal cycling test reliability. The present study constructs a three-dimensional (3D) numerical model to investigate the solder joint reliability of a lidless on-board F

APA, Harvard, Vancouver, ISO, and other styles

46

Chen, Chi-Han, Kuan-Chung Lu, Chang-Ying Hung, et al. "GHz High Frequency TSV for 2.5D IC Packaging." International Symposium on Microelectronics 2012, no. 1 (2012): 001215–20. http://dx.doi.org/10.4071/isom-2012-thp62.

Full text

Abstract:

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process. From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconn

APA, Harvard, Vancouver, ISO, and other styles

47

Kim, Jichul, Jae Choon Kim, Mina Choi, et al. "Simultaneous Characterization of Theta-JC and Theta-JB Using Through-Package 1-D Heat Flow." International Symposium on Microelectronics 2011, no. 1 (2011): 000947–52. http://dx.doi.org/10.4071/isom-2011-tha2-paper5.

Full text

Abstract:

A new technique is proposed for simultaneous, in-situ characterization of in-package thermal resistances (junction-to-case and junction-to-board) in a single test. A thin resistive heater is patterned on package top surface to establish one-dimensional heat conduction along the package vertical direction. Accompanying temperature rise at the heater is measured using a thermocouple and analyzed to estimate equivalent thermal R-C network model of the package. Due to the one-dimensionality of the probing thermal wave, the derived R-C network model represents physical package thermal structure, en

APA, Harvard, Vancouver, ISO, and other styles

48

Chen, Ming-Kun, Cheng-Chi Tai, and Yu-Jung Huang. "Electrical Characterization of FCBGA Package Based on Measurement Approach for High-speed SOC Applications." Journal of Microelectronics and Electronic Packaging 3, no. 4 (2006): 216–25. http://dx.doi.org/10.4071/1551-4897-3.4.216.

Full text

Abstract:

With high-speed computers and wireless communications system become more popular in the electronic market, these communication-oriented products require high packaging densities, clock rates and higher switching speeds over Gb/s. A multilayer flip-chip Ball grid array (FCBGA) package used for applications running at more than 1 Gb/s has been characterized in this work. Electrical characterization of the package becomes essential beyond 1 GHz considering that the interconnections on the package behave not only just as interconnections but also as transmission lines. In this paper, we present th

APA, Harvard, Vancouver, ISO, and other styles

49

Hackler, Doug, and Ed Prack. "Advanced Protected Fan-In WLCSP." International Symposium on Microelectronics 2021, no. 1 (2021): 000089–92. http://dx.doi.org/10.4071/1085-8024-2021.1.000089.

Full text

Abstract:

ABSTRACT With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)

APA, Harvard, Vancouver, ISO, and other styles

50

Ding, Shanjun, Jingyi Zhao, Xiaomeng Wu, Chuan Chen, Zhidan Fang, and Qidong Wang. "Curing kinetics of a novel commercial epoxy-phenolic composite build-up film for flip-chip ball grid array (FCBGA) substrates." Microelectronics Journal 161 (July 2025): 106717. https://doi.org/10.1016/j.mejo.2025.106717.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!