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Relevant bibliographies by topics / Flip-flop D

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Academic literature on the topic 'Flip-flop D'

Author: Grafiati

Published: 4 September 2021

Last updated: 18 February 2022

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Journal articles on the topic "Flip-flop D"

1

Yoshida, Shinichi, and Kaoru Hirota. "Lattice Structure of D, T, and SR Fuzzy Flip-Flops Under Max-Min Logic." Journal of Advanced Computational Intelligence and Intelligent Informatics 9, no. 6 (2005): 661–68. http://dx.doi.org/10.20965/jaciii.2005.p0661.

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Lattice structures of fuzzy flip-flops are described. A binary flip-flop (e.g. D, T, set-type SR, or reset-type SR flip-flop) can be extended to a fuzzy flip-flop in various ways. Under max-min fuzzy logic, there are 4 types of D fuzzy flip-flops extended from a binary D flip-flop, 136 types of SR fuzzy flip-flops extended from a binary SR flip-flop, and only one T fuzzy flip-flop. There is a lattice structure among different types of fuzzy flip-flops extended from a same binary flip-flop in terms of the order of ambiguity and the order of fuzzy logical value. These results show that fuzzy flip-flops under max-min fuzzy logic construct distributive lattice structures. Moreover D and T fuzzy flip-flops constructs Boolean lattice. And there exists a order monotone between two lattices of same fuzzy flip-flop under the order of ambiguity and the order of fuzzy logical value. Proposed analysis and results have potential to establish a fuzzy sequential system design method.

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Ray, L. B. "Flip-Flop Messenger." Science 337, no. 6101 (2012): 1434–35. http://dx.doi.org/10.1126/science.337.6101.1434-d.

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CHANG, ROBERT C., L. C. HSU, and M. C. SUN. "A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH." Journal of Circuits, Systems and Computers 11, no. 01 (2002): 51–55. http://dx.doi.org/10.1142/s0218126602000239.

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A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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Dong, Pan, Long Fan, Hong Chao Zheng, and Suge Yue. "Frequency Effect on SEU of D Flip-Flop." Applied Mechanics and Materials 110-116 (October 2011): 3132–37. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3132.

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At present, the research on the radiation-harden ability is the hot spot in the field of aerospace devices. In the paper, one commercial D flip-flop chain and one radiation-harden D flip-flop chain are chosen to be tested on the five conditions of different work frequency in the range of 100k~100M. The test would help us to study the frequency effect on SEE. The result shows that when the work frequency increases 103times, the upset threshold of commercial D flip-flop chain is almost unchanged, but the saturation cross section of the single event upset (SEU) increases about 7.13 times. Compared with radiation-harden D flip-flop chain, the reinforced chain has higher upset threshold, lower upset saturation cross section, and the saturation cross section increases about 3.71 times when the work frequency increases 103times.

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Ponnusamy, Anitha, and Palaniappan Ramanathan. "Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop." Applied Mechanics and Materials 573 (June 2014): 187–93. http://dx.doi.org/10.4028/www.scientific.net/amm.573.187.

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The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

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Archana, K., R. Manohari, and Shanthi Prince. "Performance analysis of different designs of all-optical D flip flop." International Journal of Engineering & Technology 7, no. 2.8 (2018): 578. http://dx.doi.org/10.14419/ijet.v7i2.8.10524.

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All optical flip flops play an important role in optical networks as well as in the field of optical computing. Optical memories are used for storing decisions in photonic packet routers temporarily. In this paper all optical D-flip flop is designed based on all optical gates. The nonlinear effects such as XGM (Cross Gain Modulation), XPM (Cross Phase Modulation) and FWM (Four Wave Mixing) are used to design all optical gates. We designed the D flip flop based on two logic that are NAND-NAND logic and NAND-NOR logic. The performance of both the designs is analyzed and the functionality of all optical D-flip-flop is verified using the truth table. It is proved that NAND-NAND logic is more effective than NAND-NOR logic.

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Lala, P. K., and A. Walker. "A Fine Grain Configurable Logic Block for Self-checking FPGAs." VLSI Design 12, no. 4 (2001): 527–36. http://dx.doi.org/10.1155/2001/83474.

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This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults; otherwise the outputs are identical.

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Deng, Xiao Ying, Yan Yan Mo, and Jian Hui Ning. "High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop." Applied Mechanics and Materials 713-715 (January 2015): 1042–47. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.1042.

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With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

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Surya Ali, Septian. "Trainer Gerbang Logika Digital Berbasis Arduino Mega 2560." JASEE Journal of Application and Science on Electrical Engineering 1, no. 02 (2021): 47–62. http://dx.doi.org/10.31328/jasee.v1i02.13.

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Materi Rangkaian Digital merupakan komponen penting yang perlu di pelajari oleh mahasiswa Teknik Elektro karena di dunia elekronik tidak luput dari yang namanya Rangkaian Digital. Untuk memudahkan hal tersebut maka peneitian ini dengan menggunakan mikrokontrol Arduino Mega 2560 dapat membuat modul praktikum yang simpel dan mudah di pahami. masukan yang dihasilkan adalah dengan menggerakkan posisi toggle switch dan untuk indikator keluaran adalah lampu led, dan pengujian gerbang logika dilakukan dengan beberapa cara yaitu pengujian rangkaian kombinasional gerbang logika AND, OR, NOT, NAND, NOR, XOR, dan XNOR, masing-masing di uji dari 2 input 1 output, 3 input 1 output dan 4 input 1 output. Dan rangkaian sekuensial RS Flip-Flop, D Flip-Flop, T Flip-Flop, JK Flip-Flop, hasil pengujian yang diperoleh, masing-masing rangkaian kombinasional sudah sesuai dengan tabel kebenaran gerbang logika.

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MacVittie, Kevin, Jan Halámek, and Evgeny Katz. "Enzyme-based D-flip-flop memory system." Chemical Communications 48, no. 96 (2012): 11742. http://dx.doi.org/10.1039/c2cc37075a.

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Dissertations / Theses on the topic "Flip-flop D"

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Dennhardt, Robert. "Die Flipflop-Legende und das Digitale eine Vorgeschichte des Digitalcomputers vom Unterbrecherkontakt zur Röhrenelektronik 1837 - 1945." Berlin Kulturverl. Kadmos, 2007. http://d-nb.info/992922232/04.

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Kim, Hyoung-Kook. "Defect-oriented fault analysis of a two-D-flip-flop synchronizer and test method for its application." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1336412762.

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Yongyi, Yuan. "Investigation and implementation of data transmission look-ahead D flip-flops." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2529.

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<p>This thesis investigates four D flip-flops with data transmission look-ahead circuits. Based on logical effort and power-delay products to resize all the transistor widths along the critical path in µm CMOS technology. The main goal is to verify and proof this kind of circuits can be used when the input data have low switching probabilities. From comparing the average energy consumption between the normal D flip-flops and D flip-flops with look-ahead circuits, D flip-flops with look-ahead circuits consume less power when the data switching activities are low.</p>

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Maitra, Ayan. "Nonlinear resonators for all-optical signal processing." Karlsruhe Univ.-Verl. Karlsruhe, 2007. http://d-nb.info/992791707/04.

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Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

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Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.

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Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.

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"Radiation Hardened Pulse Based D Flip Flop Design." Master's thesis, 2014. http://hdl.handle.net/2286/R.I.24764.

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abstract: ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.<br>Dissertation/Thesis<br>M.S. Electrical Engineering 2014

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Peng, Shih-Lun, and 彭士倫. "A Soft Error Tolerant D Flip-Flop Design." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/56202763496143267495.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>100<br>In recent years, soft error problem is an important reliability issue. Soft errors cause a severe problem especially for memories or flip-flops. When various particles strike on the device, a transient pulse occurs. If this transient pulse flips the data stored in the memory or the flip-flop, a soft error occurs. Soft error can be classified into Single Event Transient (SET), which occurs in the combinational logic; and Single Event Upset (SEU), which occurs in memory elements like flip-flop. Researches propose many designs to tolerate soft error in the flip-flop. However, these designs usually have large performance penalty and occupy large area overhead, so that they are not useful in simple circuits. In this thesis, we propose a new flip-flop：Soft Error Tolerant D Flip-Flop (SETDFF) to tolerate SEU, and has some SET tolerate ability. This SETDFF cell achieves the same performance with general D flip-flop and occupies less area overhead. Our SETDFF design use C-element to tolerate soft error: two inputs of the C-element come from different signals with the same value. When SEU or SET occurs, inputs of the C-element disagree with each other, and C-element rejects the transient pulse and blocks the soft error. Experiment results show that, compared with the BISER architecture proposed by other paper, our SETDFF design achieves similar SEU tolerate ability and better SET tolerate ability. At the same time, our design has 13% and 70% less performance and area overhead penalty. In our SETDFF design, SER has relationship with input arrival time. Therefore, we propose Soft Error Tolerant Time (SETT). The concept is that as long as the data arrives in a time period, we guarantee the SER under the threshold, and this time period is SETT. Circuit designers can achieve the balance between performance and SER according to this information.

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Lin, Yung-Hsiang, and 林永祥. "Design and Application of New Double Edge Triggered D-type Flip-Flop." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/76575107056599840629.

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碩士<br>淡江大學<br>電機工程學系<br>91<br>In the modern VLSI design, the System-on-a-Chip (SoC) is becoming an approach to integrate a whole system with complex functional blocks into a single high-density chip. Because of the increased circuit complexity, power consumption becomes a key design consideration of any kinds of high performance SoCs. In many VLSI chips, the power consumption of clocking system, including clock distribution network and flip-flops, is often the largest portion of the total chip power consumption. The power consumption is proportional to clock frequency. Therefore, if the operating frequency is reduced, the power consumption will also be reduced. The single edge triggered D-type flip-flop (SETDFF) can sample the input data D on the rising edge or falling edge of input clock and the double edge triggered D-type flip-flop (DETDFF) can sample the input data D on both rising edge and falling edge of input clock. So the DETDFF can maintain the same data rate at half clock frequency compared with SETDFF. Since the clocking frequency is reduced, a VLSI system with double edge triggered flip-flops can consume less power of clocking system than a system with single edge triggered flip-flops. In this thesis, a new dual-pulse double edge triggered (DPDET) D-type flip-flop is proposed. It consists of two parts, one is dual-pulse generator and another is improved split-latch. Among the proposed dual-pulse generator, two kinds of generators, 6T and 8T dual-pulse generators are presented, respectively. The proposed DPDET flip-flop has several advantages. First, the two reverse narrow pulse trains generated by dual-pulse generator are used to feed multiple flip-flops, so the power dissipation is greatly reduced if more flip-flops share a dual-pulse generator. Second, the DPDET flip-flop is clocked by two reverse narrow pulse trains, so the internal nodes can reach full swing and the flip-flop can operate correctly at low supply voltage. Third, the operating speed of the proposed DPDET flip-flop is faster than that of previous published double edge triggered flip-flops.Finally, the DPDET flip-flop is applied to the 8-bit x 8-bit pipelined multiplier. According to the post-layout simulation results, when the operating frequency is 700MHz, the circuit can operate correctly on 1.8V to 2.5V supply voltage. And when the operating frequency is 400MHz, the circuit can operate correctly on 1.3V to 2.5V supply voltage. This characteristics show that the proposed new DPDET flip-flop is suitable for low-voltage and low-power SoC application.

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Wei-Lun, Sun, and 孫偉倫. "Design of D Flip Flop Circuit and Its Application to Frequency Divider." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/72981970797122807980.

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碩士<br>崑山科技大學<br>電子工程研究所<br>95<br>In terms of general electronic study, Negative Differential Resistor (NDR) often refers to RTD, Resonance Transient Diode. RTD is consisted of composition of semi-conductor material, high electron moving efficiency is most notable character of this material. However, difficulties of CMOS/BiCMOS manufacturing process remain the biggest challenge to over-come low reliable/yield production output. NDR is a widely used component across multiple purpose in the industry, the demand is high and solution has to be found. Therefore, our research focus on a different material approach, we used Metallic Oxide Semi-conductor field effect transistor as our main structure. We adopted SiGe 0.35um 3P3M BiCMOS manufacturing technology by utilizing two enhanced N channel MOS components and one enhanced P channel MOS component and one HBT component to structure our new design. (MOS-HBT-NDR) We observed different peak/valley value by adjusting width/length of MOS component and controlling gate voltage input. Therefore, this new approach has a wide range of electronic characteristic curve available for different engineering applications. Further research and development have high value for alternative design applications. We use Negative Differential Resistance Devices to apply and design in D Flip Flop、Frequency Divider、Oscillator Circuit and Logic Circuit.

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Books on the topic "Flip-flop D"

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Low, Tim D. Low power, high performance pseudo-static D flip-flop. 1999.

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Book chapters on the topic "Flip-flop D"

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Augustin, Larry M., David C. Luckham, Benoit A. Gennart, Youm Huh, and Alec G. Stanculescu. "D- Type Flip-flop." In The Kluwer International Series in Engineering and Computer Science. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-4042-7_6.

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Pooja, M., Guruprasad S. Shetty, Vedantham Shabara Datta, and M. Suchitra. "Design of Set D Flip-Flop and Scannable Set D Flip-Flop with Optimized Area." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0626-0_20.

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Vaquie, Bruno, Sebastien Tiran, and Philippe Maurine. "A Secure D Flip-Flop against Side Channel Attacks." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_33.

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Joshi, Pooja, Saurabh Khandelwal, and Shyam Akashe. "High Performance FinFET Based D Flip Flop Including Parameter Variation." In Springer Proceedings in Physics. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2367-2_30.

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Amarnath, C., and Ankit Mehta. "Textile DOBBY Mechanism Synthesized as a Mechanical D Flip-Flop." In Lecture Notes in Mechanical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-4477-4_23.

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Dua, Tripti, Vishnu Kumar Barodiya, Vivek Arya, and Nilam Choudhary. "High-Speed SET D Flip-Flop Design for Portable Applications." In Algorithms for Intelligent Systems. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6307-6_84.

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Shrivastava, Shruti, Usha Chauhan, and Mohammad Rashid Ansari. "Optimization of dynamic clock-based D flip-flop for low-power applications." In Smart Computing. CRC Press, 2021. http://dx.doi.org/10.1201/9781003167488-85.

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Sasamal, Trailokya Nath, Ashutosh Kumar Singh, and Umesh Ghanekar. "Design of QCA-Based D Flip Flop and Memory Cell Using Rotated Majority Gate." In Smart Innovations in Communication and Computational Sciences. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8971-8_22.

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Swami, Komal, and Ritu Sharma. "Optimum Performance of Carbon Nanotube Field-Effect Transistor Based Sense Amplifier D Flip-Flop Circuits." In Intelligent Computing Techniques for Smart Energy Systems. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0214-9_33.

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Sharma, Uma, and Mansi Jhamb. "A 0.7 V 0.144 µW Frequency Divider Design with CNTFET-Based Master Slave D-Flip Flop." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3767-4_37.

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Conference papers on the topic "Flip-flop D"

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Swami, Neelam, Neha Arora, and B. P. Singh. "Low Power Subthreshold D Flip Flop." In 2011 International Conference on Devices and Communications (ICDeCom). IEEE, 2011. http://dx.doi.org/10.1109/icdecom.2011.5738478.

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Sharma, Manisha, K. G. Sharma, Tripti Sharma, B. P. Singh, and Neha Arora. "SET D-flip flop design for portable applications." In 2010 India International Conference on Power Electronics (IICPE). IEEE, 2011. http://dx.doi.org/10.1109/iicpe.2011.5728081.

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Agrawal, Tarun, Anjan Kumar, Priyanka, et al. "LVCMOS Based Energy Efficient D flip-flop Design." In 2018 2nd International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC). IEEE, 2018. http://dx.doi.org/10.1109/i-smac.2018.8653755.

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Shaikh, Jahangir, and Hafizur Rahaman. "High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop." In 2018 International Symposium on Devices, Circuits and Systems (ISDCS). IEEE, 2018. http://dx.doi.org/10.1109/isdcs.2018.8379677.

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Shandilya, Rahul, and R. K. Sharma. "Low power positive-edge triggered D-type flip-flop." In 2017 International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2017. http://dx.doi.org/10.1109/icoei.2017.8300861.

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Kaur, Ramanpreet, and Gurmeet Kaur. "Improved D fuzzy flip-flop: The design and implementation." In 2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). IEEE, 2016. http://dx.doi.org/10.1109/icpeices.2016.7853504.

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Kumaresan, Raja Sekar, Marshal Raj, and Lakshminarayanan Gopalakrishnan. "Area-Efficient D-Flip Flop and XOR in QCA." In 2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT). IEEE, 2020. http://dx.doi.org/10.1109/icccnt49239.2020.9225372.

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Shandilya, Rahul, and R. K. Sharma. "High speed low power dual-edge triggered D flip-flop." In 2017 International Conference on Intelligent Computing and Control (I2C2). IEEE, 2017. http://dx.doi.org/10.1109/i2c2.2017.8321854.

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Akbari-Hassanjani, Reza, Leila Dehbozorgi, and Reza Sabbaghi-Nadooshan. "Designing D Flip-Flop using a 3×3 reversible gate." In 2020 10th International Conference on Computer and Knowledge Engineering (ICCKE). IEEE, 2020. http://dx.doi.org/10.1109/iccke50421.2020.9303685.

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Li, Meihui, Bei Cao, Fengchang Lai, and Nan Zhang. "Design and Verification of Radiation Hardened Scanning D Flip-Flop." In 2020 IEEE 3rd International Conference on Electronics Technology (ICET). IEEE, 2020. http://dx.doi.org/10.1109/icet49382.2020.9119693.

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