Relevant bibliographies by topics / Floating-point unit

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Floating-point unit'

Author: Grafiati
Published: 4 June 2021
Last updated: 26 July 2025

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Journal articles on the topic "Floating-point unit"

1

Oavrielov, Moshe, and Lev Epstein. "The NS32081 Floating-point Unit." IEEE Micro 6, no. 2 (1986): 6–12. http://dx.doi.org/10.1109/mm.1986.304737.

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Burud, Mr Anand S., and Dr Pradip C. Bhaskar. "Processor Design Using 32 Bit Single Precision Floating Point Unit." International Journal of Trend in Scientific Research and Development Volume-2, Issue-4 (2018): 198–202. http://dx.doi.org/10.31142/ijtsrd12912.

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Galal, Sameh, and Mark Horowitz. "Energy-Efficient Floating-Point Unit Design." IEEE Transactions on Computers 60, no. 7 (2011): 913–22. http://dx.doi.org/10.1109/tc.2010.121.

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Kammer, Hubert. "The SUPRENUM vector floating-point unit." Parallel Computing 7, no. 3 (1988): 315–23. http://dx.doi.org/10.1016/0167-8191(88)90050-6.

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Mehta, Sonali, Balwinder singh, and Dilip Kumar. "Performance Analysis of Floating Point MAC Unit." International Journal of Computer Applications 78, no. 1 (2013): 38–41. http://dx.doi.org/10.5120/13456-1139.

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Hicks, T. N., R. E. Fry, and P. E. Harvey. "POWER2 floating-point unit: Architecture and implementation." IBM Journal of Research and Development 38, no. 5 (1994): 525–36. http://dx.doi.org/10.1147/rd.385.0525.

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Schwarz, E. M., and C. A. Krygowski. "The S/390 G5 floating-point unit." IBM Journal of Research and Development 43, no. 5.6 (1999): 707–21. http://dx.doi.org/10.1147/rd.435.0707.

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Gerwig, G., H. Wetter, E. M. Schwarz, et al. "The IBM eServer z990 floating-point unit." IBM Journal of Research and Development 48, no. 3.4 (2004): 311–22. http://dx.doi.org/10.1147/rd.483.0311.

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Timmermann, D., B. Rix, H. Hahn, and B. J. Hosticka. "A CMOS floating-point vector-arithmetic unit." IEEE Journal of Solid-State Circuits 29, no. 5 (1994): 634–39. http://dx.doi.org/10.1109/4.284719.

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Dr. Vasudeva G and Dr Bharathi Gururaj. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.b3669.15020525.

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In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbers get bigger. For multiplication
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Dissertations / Theses on the topic "Floating-point unit"

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Jain, Sheetal A. 1980. "Low-power single-precision IEEE Floating-point unit." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87426.

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Lugo, Martinez Jose E. "Strategies for sharing a floating point unit between SPEs." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/ucsd/fullcit?p1470744.

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Thesis (M.S.)--University of California, San Diego, 2010.<br>Title from first page of PDF file (viewed February 17, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 55-57).
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Dutta, Sumit Ph D. Massachusetts Institute of Technology. "Floating-point unit (FPU) designs with nano-electromechanical (NEM) relays." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84724.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (pages 71-74).<br>Nano-electromechanical (NEM) relays are an alternative to CMOS transistors as the fabric of digital circuits. Circuits with NEM relays offer energy-efficiency benefits over CMOS since they have zero leakage power and are strategically designed to maintain throughput that is comp
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Ratan, Amrita. "Hardware Modules for Safe Integer and Floating-Point Arithmetic." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

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Hartman, Daniel K. "Floating point multiply/add unit for the M-machine node processor." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38791.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.<br>Includes bibliographical references (p. 177).<br>by Daniel K. Hartman.<br>M.Eng.
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Kannan, Balaji Navalpakkam. "The design of an IC half precision floating point Arithmetic Logic Unit." Connect to this title online, 2009. http://etd.lib.clemson.edu/documents/1263396747/.

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Kaveti, Akil. "HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT." UKnowledge, 2008. http://uknowledge.uky.edu/gradschool_theses/538.

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Processors used in lower-end scientific applications like graphic cards and video game consoles have IEEE single precision floating-point hardware [23]. Double precision offers higher precision at higher implementation cost and lower performance. The need for high precision computations in these applications is not enough to justify the use double precision hardware and the extra hardware complexity needed [23]. Native-pair arithmetic offers an interesting and feasible solution to this problem. This technique invented by T. J. Dekker uses single-length floating-point numbers to represent highe
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Pathanjali, Nandini. "Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA’s." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1017085297.

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Samuel, Reuven Meyer. "Design and optimization of a reconfigurable shared floating point unit in a multi-processor environment." The Ohio State University, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=osu1235242668.

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Baesler, Malte [Verfasser]. "FPGA Implementation of a Decimal Floating-Point Co-Processor with Accurate Scalar Product Unit / Malte Baesler." Aachen : Shaker, 2012. http://d-nb.info/1069045349/34.

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Books on the topic "Floating-point unit"

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N, Levitt Karl, Cohen G. C, and Langley Research Center, eds. Toward a formal verification of a floating-point coprocessor and its composition with a central processing unit. National Aeronautics and Space Administration, Langley Research Center, 1991.

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IEEE Computer Society Standards Committee. Working group of the Microprocessor Standards Subcommittee. and American National Standards Institute, eds. IEEE standard for binary floating-point arithmetic. Institute of Electrical and Electronics Engineers, 1985.

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Kulisch, Ulrich. Computer arithmetic and validity. De Gruyter, 2013.

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Aiyappa, Rekha. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Errata. Microchip Technology Incorporated, 2020.

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Aiyappa, Rekha. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family. Microchip Technology Incorporated, 2019.

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Aiyappa, Rekha. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family. Microchip Technology Incorporated, 2016.

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Aiyappa, Rekha. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Data Sheet. Microchip Technology Incorporated, 2016.

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Aiyappa, Rekha. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Silicon Errata. Microchip Technology Incorporated, 2020.

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Dufseth, Rhonda. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Data Sheet. Microchip Technology Incorporated, 2015.

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Aiyappa, Rekha. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Data Sheet. Microchip Technology Incorporated, 2019.

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Book chapters on the topic "Floating-point unit"

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Kusswurm, Daniel. "X87 Floating-Point Unit." In Modern X86 Assembly Language Programming. Apress, 2014. http://dx.doi.org/10.1007/978-1-4842-0064-3_3.

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Bai, Ying. "MSP432™ floating-point unit (FPU)." In Microcontroller Engineering with MSP432. CRC Press, 2016. http://dx.doi.org/10.1201/9781315367101-11.

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Berg, Christoph, and Christian Jacobi. "Formal Verification of the VAMP Floating Point Unit." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44798-9_26.

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Patil, Ishan A., Prasanna Palsodkar, and Ajay Gurjar. "Floating Point-based Universal Fused Add–Subtract Unit." In Advances in Intelligent Systems and Computing. Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-1602-5_29.

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Stazi, Giulia, Federica Silvestri, Antonio Mastrandrea, Mauro Olivieri, and Francesco Menichelli. "Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11973-7_30.

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Alachiotis, Nikolaos, and Alexandros Stamatakis. "FPGA Optimizations for a Pipelined Floating-Point Exponential Unit." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19475-7_34.

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Kida, Hiroyuki, Mitsuru Watabe, Tetsuaki Nakamikawa, Shigeki Morinaga, Shumpei Kawasaki, and Hideo Inayoshi. "A Floating Point Processing Unit for the Gmicro CPU." In TRON Project 1988. Springer Japan, 1988. http://dx.doi.org/10.1007/978-4-431-68081-9_21.

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Dasu, Vani, and K. Ragini. "Implementation of 64-Bit Inexact Speculative Half Unit Biased Floating-Point Adder." In Intelligent Computing and Communication. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-1588-0_39.

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Mukherjee, Rajdeep, Saurabh Joshi, Andreas Griesmayer, Daniel Kroening, and Tom Melham. "Equivalence Checking of a Floating-Point Unit Against a High-Level C Model." In FM 2016: Formal Methods. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-48989-6_33.

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Dhanabal, R., Sarat Kumar Sahoo, and V. Bharathi. "Implementation of Low Power and Area Efficient Floating-Point Fused Multiply-Add Unit." In Proceedings of the International Conference on Soft Computing Systems. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2671-0_31.

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Conference papers on the topic "Floating-point unit"

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Trong, Son Dao, Martin Schmookler, Eric M. Schwarz, and Michael Kroener. "P6 Binary Floating-Point Unit." In 18th IEEE Symposium on Computer Arithmetic (ARITH '07). IEEE, 2007. http://dx.doi.org/10.1109/arith.2007.26.

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Singh, Prateek, and Kalyani Bhole. "Optimized floating point arithmetic unit." In 2014 Annual IEEE India Conference (INDICON). IEEE, 2014. http://dx.doi.org/10.1109/indicon.2014.7030552.

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Min, Jae Hong, and Earl E. Swartzlander. "Fused floating-point magnitude unit." In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2013. http://dx.doi.org/10.1109/mwscas.2013.6674914.

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Boersma, Maarten, Michael Kroner, Christophe Layer, Petra Leber, Silvia M. Muller, and Kerstin Schelm. "The POWER7 Binary Floating-Point Unit." In 2011 IEEE 20th Symposium on Computer Arithmetic (ARITH). IEEE, 2011. http://dx.doi.org/10.1109/arith.2011.21.

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Saleh, Hani H., and Earl E. Swartzlander. "A floating-point fused dot-product unit." In 2008 IEEE International Conference on Computer Design (ICCD). IEEE, 2008. http://dx.doi.org/10.1109/iccd.2008.4751896.

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Chong, Yee Jern, and Sri Parameswaran. "Automatic Application Specific Floating-point Unit Generation." In Design, Automation & Test in Europe Conference. IEEE, 2007. http://dx.doi.org/10.1109/date.2007.364635.

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Rani, Savita. "Area and speed efficient floating point unit." In 2014 Recent Advances and Innovations in Engineering (ICRAIE). IEEE, 2014. http://dx.doi.org/10.1109/icraie.2014.6909316.

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Harish Anand, T., D. Vaithiyanathan, and R. Seshasayanan. "Optimized architecture for Floating Point computation Unit." In 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT). IEEE, 2013. http://dx.doi.org/10.1109/icevent.2013.6496587.

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Sharma, Jyoti, Pabbisetty Tarun, Sambangi Satishkumar, and S. Sivanantham. "Fused floating-point add and subtract unit." In 2015 Online International Conference on Green Engineering and Technologies (IC-GET). IEEE, 2015. http://dx.doi.org/10.1109/get.2015.7453797.

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Saleh, Hani, and Earl E. Swartzlander. "A floating-point fused add-subtract unit." In 2008 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2008. http://dx.doi.org/10.1109/mwscas.2008.4616850.

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