Relevant bibliographies by topics / Floating-point unit (FPU)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Floating-point unit (FPU)'

Author: Grafiati
Published: 5 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Floating-point unit (FPU)"

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R., Bhuvanapriya, and T. Menakadevi. "Design and Implementation of FPU for Optimised Speed." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 3922–33. https://doi.org/10.35940/ijeat.C6444.029320.

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Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need
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Dr. Vasudeva G and Dr Bharathi Gururaj. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.b3669.15020525.

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In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbers get bigger. For multiplication
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Dr., Vasudeva G. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering (IJSCE) 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.B3669.15020525.

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<strong>Abstract:</strong> In this paper, we dive into the design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps del
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Dr., Vasudeva G. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering (IJSCE) 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.B3669.15020525/.

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<strong>Abstract:</strong> In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning&mdash;our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbe
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G, Vasudeva, and Bharathi Gururaj. "Design of an Efficient Single Precision Floating Point Unit." International Journal of Electrical Engineering and Computer Science 7 (March 26, 2025): 44–54. https://doi.org/10.37394/232027.2025.7.5.

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In this , we design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps delays minimal even as the numbers get bigger. Fo
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Alder, Fritz, Jo Van Bulck, Jesse Spielman, David Oswald, and Frank Piessens. "Faulty Point Unit: ABI Poisoning Attacks on Trusted Execution Environments." Digital Threats: Research and Practice 3, no. 2 (2022): 1–26. http://dx.doi.org/10.1145/3491264.

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This article analyzes a previously overlooked attack surface that allows unprivileged adversaries to impact floating-point computations in enclaves through the Application Binary Interface (ABI). In a comprehensive study across 7 industry-standard and research enclave shielding runtimes for Intel Software Guard Extensions (SGX), we show that control and state registers of the x87 Floating-Point Unit (FPU) and Intel Streaming SIMD Extensions are not always properly sanitized on enclave entry. We furthermore show that this attack goes beyond the x86 architecture and can also affect RISC-V enclav
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Maniatakos, M., P. Kudva, B. M. Fleischer, and Y. Makris. "Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers." IEEE Transactions on Computers 62, no. 7 (2013): 1376–88. http://dx.doi.org/10.1109/tc.2012.81.

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., NARAHARI BHARGAVI, and B. NAGA RAJESH . "VLSI IMPLEMENTATION OF HIGH SPEED SINGLE PRECESSION FLOATING POINT UNIT USING VERILOG." International Journal of Engineering Technology and Management Sciences 6, no. 1 (2022): 16–23. http://dx.doi.org/10.46647/ijetms.2022.v06i01.003.

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Single-precision floating-point format is a computer number format that is used to represent a wide dynamic range of values. Floating point numbers representation has widespread dominance over fixed point numbers. Since the recent years, researchers are putting a lot of efforts in interfacing complex modules which are used in signal processing with processors for increasing the speed. In this work implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, and division functions on 32-bit operands that use the IEEE 754-2008 standard is done using
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Mohammed, Falih Hassan, Farhood Hussein Karime, and Al-Musawi Bahaa. "Design and implementation of fast floating point units for FPGAs." Indonesian Journal of Electrical Engineering and Computer Science 19, no. 3 (2022): 1480–89. https://doi.org/10.11591/ijeecs.v19.i3.pp1480-1489.

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Due to growth in demand for high-performance applications that require high numerical stability and accuracy, the need for floating-point FPGA has been increased. In this work, an open-source and efficient floating-point unit is implemented on a standard Xilinx Sparton-6 FPGA platform. The proposed design is described in a hierarchal way starting from functional block descriptions toward modules level design. Our implementation used minimal resources available on the targeting FPGA board, tested on the Sparton-6 FPGA platform and verified on ModelSim. The open-source framework can be embedded
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Freitas, Jordana Alves de, Kátia Lopes Silva, and Mauro Hemerly Gazzani. "IMPLEMENTAÇÃO DA OPERAÇÃO DE DIVISÃO EM UMA UNIDADE DE PONTO FLUTUANTE DE 32 BITS BASEADA NO PADRÃO IEEE 754 EM VERILOG." Revista ft 29, no. 142 (2025): 21–22. https://doi.org/10.69849/revistaft/ni10202501090721.

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A Floating-Point Unit (FPU) is an essential component of a computer processor responsible for performing arithmetic operations on floating point numbers, following the specifications of the IEEE 754 standard. The UPF consists of a series of circuits and logic designed to handle the representation, manipulation and calculations of floating-point numbers. It is responsible for converting the floating-point numbers into proper internal representations, performing the necessary mathematical operations and providing the result in the correct format. This work presents the implementation of a 32-bit
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Dissertations / Theses on the topic "Floating-point unit (FPU)"

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Dutta, Sumit Ph D. Massachusetts Institute of Technology. "Floating-point unit (FPU) designs with nano-electromechanical (NEM) relays." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84724.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (pages 71-74).<br>Nano-electromechanical (NEM) relays are an alternative to CMOS transistors as the fabric of digital circuits. Circuits with NEM relays offer energy-efficiency benefits over CMOS since they have zero leakage power and are strategically designed to maintain throughput that is comp
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Závada, Vladislav. "C++ knihovna pro práci s čísly v pohyblivé řádové čárce s libovolnou přesností." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2019. http://www.nusl.cz/ntk/nusl-403142.

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This thesis deals with the design of a floating point module, which allows to perform operations with floating point operands that have any bit width. For this purpose, the module is implemented as a template class in C ++. The module is designed to allow it to be used when designing an application-specific processor. First, the floating point number and template functions in c ++ are described. In the practical part the algorithms of the individual operations and the design of the module itself are described as template libraries.
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Chong, Michael Yee Jern Computer Science &amp Engineering Faculty of Engineering UNSW. "Customization of floating-point units for embedded systems and field programmable gate arrays." Publisher:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44399.

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While Application Specific Instruction Set Processors (ASIPs) have allowed designers to create processors with custom instructions to target specific applications, floating-point units (FPUs) are still instantiated as non-customizable general-purpose units, which if under utilized, wastes area and performance. However, customizing FPUs manually is a complex and time-consuming process. Therefore, there is a need for an automated custom FPU generation scheme. This thesis presents a methodology for generating application-specific FPUs customized at the instruction level, with integrated datap
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Book chapters on the topic "Floating-point unit (FPU)"

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Bai, Ying. "MSP432™ floating-point unit (FPU)." In Microcontroller Engineering with MSP432. CRC Press, 2016. http://dx.doi.org/10.1201/9781315367101-11.

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"ARM® Floating Point Unit (FPU)." In Practical Microcontroller Engineering with ARM® Technology. John Wiley & Sons, Inc., 2015. http://dx.doi.org/10.1002/9781119058397.ch11.

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"MSP432™ floating-point unit (FPU)." In Microcontroller Engineering with MSP432. CRC Press, 2016. http://dx.doi.org/10.1201/9781315367101-20.

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Yiu, Joseph. "The Floating-Point Unit (FPU) in the Cortex-M33 processor." In Definitive Guide to Arm® Cortex®-M23 and Cortex-M33 Processors. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-820735-2.00014-7.

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Jones, Oliver P., Hans Fabricius Hansen, and Michael Zhang. "An Improved Method of Establishing Extreme Metocean Conditions in the Gulf of Mexico." In Ageing and Life Extension of Offshore Facilities. ASME, 2022. http://dx.doi.org/10.1115/1.885789_ch13.

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Metocean criteria at a Floating Production Unit (FPU) in the central Gulf Of Mexico (GoM) are being reassessed to support the facility’s Life Extension. Two key shortcomings of previous approaches to the development of hurricane ‘full population’ criteria have been addressed here. These include the extrapolation of correlated grid-point ‘pooled’ data and ‘non-peak’ storm data - both of which can lead to bias in extreme value estimates. These improvements have been achieved through the identification of a statistically homogenous set of hindcast grid-points. Each grid point exhibits variability in the tail region of the distribution, as a result of limited sampling of both storm track and intensity. By first, fitting a non stationary model of the marginal and joint extremes to the tails of storm peaks from each grid point and, then, merging the resulting distribution parameters from each, we establish a method of incorporating the spatial variability in both track and intensity - across a data sparse, homogenous hurricane region - into design estimates, without recourse to grid-point pooling or track-shifting and all their inherent issues. The new method also provides a set of statistically consistent hurricane storm trajectories, based on the extrapolated ensemble of tail distribution parameters. This is expected to provide significant reductions to the joint load cases, compared to standard practise.
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Conference papers on the topic "Floating-point unit (FPU)"

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Hockert, Neil, and Katherine Compton. "FFPU: Fractured floating point unit for FPGA soft processors." In 2009 International Conference on Field-Programmable Technology (FPT). IEEE, 2009. http://dx.doi.org/10.1109/fpt.2009.5377622.

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Azevedo, T. E. S., L. M. Hayashi, R. R. S. Leal, et al. "Sururu Central: Appraisal and Development Plan for a Marginal Presalt Reservoir." In Offshore Technology Conference. OTC, 2024. http://dx.doi.org/10.4043/35273-ms.

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Abstract This paper presents a multidisciplinary view of the evolution in the concept of a development project for the central area of Sururu and the method applied to address the challenges and propose solutions for the project in progress. The central area of Sururu reservoir presents distinct characteristics from typical Brazilian Presalt fields, with low permeabilities despite of high porosity. This context brings challenges to define the best production development plan for the area, since its reservoir features, with low productivities, make conventional Presalt development architectures
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Beauchamp, Michael, Scott Hauck, Keith Underwood, and K. Hemmert. "Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs." In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311260.

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Yu, Chi Wai, Alastair M. Smith, Wayne Luk, Philip H. W. Leong, and Steven J. E. Wilton. "Optimizing coarse-grained units in floating point hybrid FPGA." In 2008 International Conference on Field-Programmable Technology (FPT). IEEE, 2008. http://dx.doi.org/10.1109/fpt.2008.4762366.

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Diniz, Pedro, and Gokul Govindu. "Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit." In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311302.

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Jose, Wilson, Ana Rita Silva, Horacio Neto, and Mario Vestias. "Efficient implementation of a single-precision floating-point arithmetic unit on FPGA." In 2014 24th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2014. http://dx.doi.org/10.1109/fpl.2014.6927391.

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Van Nuffel, F., O. Dasilva, K. Van Lookeren, and M. Krekel. "Congo LNG – Creating a New Fast Track Offshore LNG Terminal Re-Utilizing Existing Assets." In Offshore Technology Conference. OTC, 2025. https://doi.org/10.4043/35870-ms.

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Abstract Objectives/Scope After Tango FLNG became commercially available, a new Client was found for the floating liquefaction unit at the Marine XII oil and gas field in Congo. To implement a fast-track LNG export solution, a solution needed to be found to moor Tango FLNG offshore Congo. Moreover, an FSU needed to be placed adjacent to Tango FLNG to ensure the terminal had sufficient LNG storage capacity. Tango FLNG, which has a liquefaction capacity of approximately 1 billion cubic meters per annum of gas (BCMA), had to be moored 3 kilometers offshore along with the Excalibur FSU. Excalibur
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Journal articles
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