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Dissertations / Theses on the topic 'Floating-point unit'

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Published: 4 June 2021

Last updated: 26 July 2025

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1

Jain, Sheetal A. 1980. "Low-power single-precision IEEE Floating-point unit." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87426.

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2

Lugo, Martinez Jose E. "Strategies for sharing a floating point unit between SPEs." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/ucsd/fullcit?p1470744.

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Thesis (M.S.)--University of California, San Diego, 2010.<br>Title from first page of PDF file (viewed February 17, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 55-57).

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3

Dutta, Sumit Ph D. Massachusetts Institute of Technology. "Floating-point unit (FPU) designs with nano-electromechanical (NEM) relays." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84724.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (pages 71-74).<br>Nano-electromechanical (NEM) relays are an alternative to CMOS transistors as the fabric of digital circuits. Circuits with NEM relays offer energy-efficiency benefits over CMOS since they have zero leakage power and are strategically designed to maintain throughput that is comp

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4

Ratan, Amrita. "Hardware Modules for Safe Integer and Floating-Point Arithmetic." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

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5

Hartman, Daniel K. "Floating point multiply/add unit for the M-machine node processor." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38791.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.<br>Includes bibliographical references (p. 177).<br>by Daniel K. Hartman.<br>M.Eng.

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6

Kannan, Balaji Navalpakkam. "The design of an IC half precision floating point Arithmetic Logic Unit." Connect to this title online, 2009. http://etd.lib.clemson.edu/documents/1263396747/.

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7

Kaveti, Akil. "HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT." UKnowledge, 2008. http://uknowledge.uky.edu/gradschool_theses/538.

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Processors used in lower-end scientific applications like graphic cards and video game consoles have IEEE single precision floating-point hardware [23]. Double precision offers higher precision at higher implementation cost and lower performance. The need for high precision computations in these applications is not enough to justify the use double precision hardware and the extra hardware complexity needed [23]. Native-pair arithmetic offers an interesting and feasible solution to this problem. This technique invented by T. J. Dekker uses single-length floating-point numbers to represent highe

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8

Pathanjali, Nandini. "Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA’s." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1017085297.

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9

Samuel, Reuven Meyer. "Design and optimization of a reconfigurable shared floating point unit in a multi-processor environment." The Ohio State University, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=osu1235242668.

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10

Baesler, Malte [Verfasser]. "FPGA Implementation of a Decimal Floating-Point Co-Processor with Accurate Scalar Product Unit / Malte Baesler." Aachen : Shaker, 2012. http://d-nb.info/1069045349/34.

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11

Pinkiewicz, T. "Design of a 32-bit Arithmetic Unit based on Composite Arithmetic and its Implementation on a Field Programmable Gate Array." Thesis, Honours thesis, University of Tasmania, 1999. https://eprints.utas.edu.au/584/1/Honours_Thesis.pdf.

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As we advance into the new century, computers of the future will require new techniques for arithmetic operations, which take advantage of the modern technology and yield accurate results. Floating-point arithmetic has been in use for nearly forty years, but is plagued with inaccuracies and limitations which necessitate introduction of a new concept in computer arithmetic, called Composite Arithmetic. Composite Arithmetic combines fixed-point and floating-point arithmetic into one integrated concept where numbers are automatically assigned the right form. This negates the need for diffe

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Závada, Vladislav. "C++ knihovna pro práci s čísly v pohyblivé řádové čárce s libovolnou přesností." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2019. http://www.nusl.cz/ntk/nusl-403142.

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This thesis deals with the design of a floating point module, which allows to perform operations with floating point operands that have any bit width. For this purpose, the module is implemented as a template class in C ++. The module is designed to allow it to be used when designing an application-specific processor. First, the floating point number and template functions in c ++ are described. In the practical part the algorithms of the individual operations and the design of the module itself are described as template libraries.

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13

Brunie, Nicolas. "Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués." Thesis, Lyon, École normale supérieure, 2014. http://www.theses.fr/2014ENSL0894/document.

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Au cours des dernières décennies les systèmes embarqués ont dû faire face à des demandes applicatives de plus en plus variées et de plus en plus contraintes. Ce constat s'est traduit pour l’arithmétique par le besoin de toujours plus de performances et d'efficacité énergétique. Ce travail se propose d'étudier des solutions allant du matériel au logiciel, ainsi que les diverses interactions qui existent entre ces domaines, pour améliorer le support arithmétique dans les systèmes embarqués. Certains résultats ont été intégrés au processeur MPPA développé par Kalray. La première partie est consac

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14

Englund, Madeleine. "Hybrid Floating-point Units in FPGAs." Thesis, Linköpings universitet, Datorteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86587.

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Floating point numbers are used in many applications that would be well suited to a higher parallelism than that offered in a CPU. In these cases, an FPGA, with its ability to handle multiple calculations simultaneously, could be the solution. Unfortunately, floating point operations which are implemented in an FPGA is often resource intensive, which means that many developers avoid floating point solutions in FPGAs or using FPGAs for floating point applications. Here the potential to get less expensive floating point operations by using ahigher radix for the floating point numbers and u

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Popescu, Valentina. "Towards fast and certified multiple-precision librairies." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEN036/document.

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De nombreux problèmes de calcul numérique demandent parfois à effectuer des calculs très précis. L'étude desystèmes dynamiques chaotiques fournit des exemples très connus: la stabilité du système solaire ou l’itération à longterme de l'attracteur de Lorenz qui constitue un des premiers modèles de prédiction de l'évolution météorologique. Ons'intéresse aussi aux problèmes d'optimisation semi-définie positive mal-posés qui apparaissent dans la chimie oul'informatique quantique.Pour tenter de résoudre ces problèmes avec des ordinateurs, chaque opération arithmétique de base (addition,multiplicati

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Shah, Syed Yawar Ali. "On synthesis and optimization of floating point units." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ59309.pdf.

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17

Chong, Michael Yee Jern Computer Science &amp Engineering Faculty of Engineering UNSW. "Customization of floating-point units for embedded systems and field programmable gate arrays." Publisher:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44399.

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While Application Specific Instruction Set Processors (ASIPs) have allowed designers to create processors with custom instructions to target specific applications, floating-point units (FPUs) are still instantiated as non-customizable general-purpose units, which if under utilized, wastes area and performance. However, customizing FPUs manually is a complex and time-consuming process. Therefore, there is a need for an automated custom FPU generation scheme. This thesis presents a methodology for generating application-specific FPUs customized at the instruction level, with integrated datap

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18

[Verfasser], Surapong Pongyupinpanich, Manfred [Akademischer Betreuer] Glesner, Michael [Akademischer Betreuer] Hübner, Andreas [Akademischer Betreuer] Binder, Harald [Akademischer Betreuer] Klingbeil, and Hans [Akademischer Betreuer] Eveking. "Optimal Design of Fixed-Point and Floating-Point Arithmetic Units for Scientific Applications / Surapong Pongyupinpanich. Betreuer: Manfred Glesner ; Michael Hübner ; Andreas Binder ; Harald Klingbeil ; Hans Eveking." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2012. http://d-nb.info/1106117581/34.

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19

LaPlante, John R., and Steve G. Barge. "High-Level Language Programming Environment for Parallel Real-Time Telemetry Processor." International Foundation for Telemetering, 1989. http://hdl.handle.net/10150/614649.

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International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California<br>The difficulty of incorporating custom real-time processing into a conventional telemetry system frustrates many design engineers. Custom algorithms such as data compression/conversion, software decommutation, signal processing or sensitive defense related algorithms, are often executed on expensive and time-consuming mainframe computers during post-processing. The cost to implement such algorithms on real-time hardware is greater, because progra

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20

Vangal, Sriram R. "Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures." Licentiate thesis, Linköping : Linköpings universitet, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7845.

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21

Dev, Ruby, and Lipsa Sahu. "An efficient IEEE754 compliant floating point unit using verilog." Thesis, 2012. http://ethesis.nitrkl.ac.in/3638/1/thesis_final.pdf.

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A floating-point unit (FPU) colloquially is a math coprocessor, which is a part of a computer system specially designed to carry out operations on floating point numbers [1]. Typical operations that are handled by FPU are addition, subtraction, multiplication and division. The aim was to build an efficient FPU that performs basic as well as transcendental functions with reduced complexity of the logic used reduced or at least comparable time bounds as those of x87 family at similar clock speed and reduced the memory requirement as far as possible. The functions performed are handling of Floati

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22

Sohn, Jongwook. "Improved architectures for a fused floating-point add-subtract unit." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4722.

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This report presents improved architecture designs and implementations for a fused floating-point add-subtract unit. The fused floating-point add-subtract unit is useful for DSP applications such as FFT and DCT butterfly operations. To improve the performance of the fused floating-point add-subtract unit, the dual path algorithm and pipelining technique are applied. The proposed designs are implemented for both single and double precision and synthesized with a 45nm standard-cell library. The fused floating-point add-subtract unit saves 40% of the area and power consumption and the dual path f

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23

"Procedural layout of a high-speed floating-point arithmetic unit." Massachusetts Institute of Technology, Research Laboratory of Electronics, 1985. http://hdl.handle.net/1721.1/4235.

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Robert Clyde Armstrong.<br>Originally presented as author's thesis (Electrical Engineer --Massachusetts Institute of Technology) 1985.<br>Bibliography: leaf 116.<br>Supported in part by the U.S. Air Force Office of Scientific Research contract F49620-84-C-0004

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24

Chang, Chia-Chou, and 張嘉洲. "Design of a Floating-point Multiplication/Division-Addition Fused Unit." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/55614700772824063040.

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碩士<br>逢甲大學<br>資訊工程所<br>92<br>This thesis presents a design of an IEEE floating-point multiplication/division add fused unit. The design of the unit is based on the design of a multiplication-add fused unit (MAF). We integrated a multiplicative division algorithm into our unit and adopted a new “two-step normalization algorithm” normalization for floating-point multiplication and division. This unit is divided into four stages. The function of the first stage performs the first step of division. The second stage includes the alignment of the exponents, addition and combination of multiplication

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Sohn, Jongwook. "Improved architectures for fused floating-point arithmetic units." 2013. http://hdl.handle.net/2152/21943.

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Most general purpose processors (GPP) and application specific processors (ASP) use the floating-point arithmetic due to its wide and precise number system. However, the floating-point operations require complex processes such as alignment, normalization and rounding. To reduce the overhead, fused floating-point arithmetic units are introduced. In this dissertation, improved architectures for three fused floating-point arithmetic units are proposed: 1) Fused floating-point add-subtract unit, 2) Fused floating-point two-term dot product unit, and 3) Fused floating-point three-term adder. Also,

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26

Lin, Yue-Fon, and 林裕峰. "Implemenation and Formal Verification of 64-bit Pipelined Floating Point Unit." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/72816588406463752429.

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碩士<br>國立交通大學<br>資訊科學系<br>89<br>In this thesis, we present an implemented design "Floating Point Unit", and extend Chen and Bryant's method to verify a pipelined arithmetic circuit. First, implement a 64-bit pipelined Floating Point Unit that supports IEEE double precision and all of four IEEE rounding modes. Then this design is verified with two methods, "Random Test Pattern Generation" and our verification system extended from "Chen and Bryant's method". Random test pattern generation method is to use test patterns generated

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27

Liao, Ying-Chen, and 廖英程. "Multi-precision Floating Point Special Function Unit for Low Power Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/79179451858419463086.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>In today’s modern society, our latest up-to-date technology contains various types of multimedia applications. These applications don’t necessarily have to be executed with the most precise accuracy. In short, they are fault tolerant. As a consequence, this thesis proposes a multi-precision iterative floating-point special function unit, which can be executed under different modes to meet the error requirements of each specific application, and also achieve power reduction during the process. In order to minimize the area of our design, we have developed two

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Jacobi, Christian [Verfasser]. "Formal verification of a fully IEEE compliant floating point unit / Christian Jacobi." 2004. http://d-nb.info/972323171/34.

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Chiang, Chia-Chun, and 江佳峻. "A Floating Point Addition Unit for DSP Processor Using Asynchronous Circuit Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/68376586968432449743.

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30

Yu, Kee-khuan, and 余其坤. "Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/40653496758367242544.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>99<br>In digital signal processing and multimedia applications, floating-point(FP) multiplication and addition are the most commonly used operations. In addition, FP multiplication operations are frequently followed by the FP addition operations. Therefore, in order to achieve high performance and low cost, multiplication and addition are usually combined into a single unit, known as the FP Multiply-Add Fused (MAF). On the other hand, the mobile devices nowadays are rapidly developing. For this kind of devices, performance and power sustainability have to become th

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Chen, Liang-An, and 陳亮安. "Circuit Design and performance analysis of a Fast Floating-Point Multiplication-Add Fused Unit." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/c47dh5.

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碩士<br>逢甲大學<br>資訊工程所<br>90<br>This thesis presents a design of an IEEE floating-point (FLP) multiplication-and-addition fused (MAF) unit by using signed digit (SD) adders. This unit is divided into three pipeline stages. The function of the first pipeline stage includes the alignment of the exponents, the mantissa multiplication and addition. The second stage performs the mantissa normalization. In the third stages, SD-to-SM conversion of the SD mantissa and its rounding are performed. Because of the usage of SD multiplier and SD adders, which are carry-propagation-free, the speed of the first

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Cheng, Chih-jen, and 鄭智仁. "Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Adders." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/87825905626219255151.

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碩士<br>逢甲大學<br>資訊工程學系<br>89<br>To achieve high performance, low lost, and low power objectives, floating-point (FLP) multiplication and FLP addition are usually implemented in one unit for the design of microprocessors. Sign digit addition is adopted in the design of a new floating-point (FLP) multiplication-add fused (MAF) unit. This adoption, together with the proposed two-step normalization method, can reduce the three-word-length addition that is required in the conventional FLP MAF unit to a two-word-length adder. Furthermore, the sign reversion of the intermediate mantissa that requires a

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33

Yen, Hsin-Lin, and 顏杏霖. "Design of a Fast Signed-Digit Multiplier/Divider Fused Unit for Floating-Point Arithmetic." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/50488248517783444600.

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碩士<br>逢甲大學<br>資訊工程學系<br>90<br>Signed-digit (SD) multiplicative normalization method is proposed to compute the reciprocal in the division-by-reciprocal algorithm. The operations in each SD normalization stage can be performed on a fast SD adder without carry propagation. Furthermore, the SD normalization method can facilitate the adoption of the SD termination algorithm. This termination algorithm can replace half of the normalization stages in the linear normalization method by a half word-length SD multiplier. The speed of the proposed divider is therefore comparable to a linear SD multiplie

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NHI, PHU MAN, and 符敏兒. "Design and Implementation of a Pipelined Floating Point Unit with Modified Booth-Wallace Tree Multiplier." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/15208388538647317162.

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Cheng, Hsiu-Wen, and 鄭琇文. "Design of a Carry-Propagation-Free Floating-Point Multiplication Unit Based on a Novel Array Multiplier." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/46062069611954529318.

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碩士<br>逢甲大學<br>資訊工程學系<br>89<br>A new array architecture for implementing multiplication operations is proposed in this research. The proposed new array multiplier will output a non-redundant product without carry propagation addition in its last stage of operation. Furthermore, the rounding of the product can also be performed in an efficient manner without carry propagation. The performance of the pipelined array multiplier can thus be greatly enhanced. The functionality of the proposed multiplication algorithm is first verified by using Turbo C language. Then, the algorithm is adopted to impl

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Min, Jae Hong. "Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2495.

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Fused floating-point arithmetic units such as a floating-point fused Dot-Product (fused DP) and a floating-point fused Add-Subtract (fused AS) are employed for the implementation of the butterfly unit of the FFT due to their characteristics of low power and less area. In addition, the fused DP has less delay and lower error. Among the elements of the fused DP, two internal mantissa multipliers occupy the largest area and consume the largest power. A Multiple-Constant Multiplier (MCM) architecture has high speed, low power consumption, and small area compared to a conventional multiplier. The M

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Shah, Syed Yawar Ali. "On synthesis and optimization of floating point units." Thesis, 2000. http://spectrum.library.concordia.ca/1298/1/MQ59309.pdf.

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This work describes the effect of architectural/system level design decisions on the performance, of floating point arithmetic units. By modeling with VHDL and using design synthesis techniques, different architectures of floating point adders, multipliers and multiply-accumulate fused units, are compared using different technologies and cell libraries. Some modifications to recent published works have been proposed to minimize the energy delay product with special emphasis on power reduction. A new low power, high performance, transition activity scaled, double data path floating point multip

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Pongyupinpanich, Surapong. "Optimal Design of Fixed-Point and Floating-Point Arithmetic Units for Scientific Applications." Phd thesis, 2012. https://tuprints.ulb.tu-darmstadt.de/3091/1/dissertation-final-version.pdf.

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The challenge in designing a floating-point arithmetic co-processor/processor for scientific and engineering applications is to improve the performance, efficiency, and computational accuracy of the arithmetic unit. The arithmetic unit should efficiently support several mathematical functions corresponding to scientific and engineering computation demands. Moreover, the computations should be performed as fast as possible with a high degree of accuracy. Thus, this thesis proposes algorithm, design, architecture, and analysis of floating-point arithmetic units particularly for scientific and en

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Lee, Hsin-mau, and 李昕懋. "Designs, Implementations and Applications of Floating-Point Trigonometric Function Units." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/j8vhqu.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>96<br>In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis. Detailed analysis and comparison of these architectures are addressed in order to choose the best architecture with minimized area cost and computation latency given the required bit accuracy. Based on the comparison, we have chosen the best architecture and implemented an IEEE single precision floating-point CORDIC processor. The mathematical analysis of the computation errors i

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Liu, Chih-Hsiang, and 劉志祥. "A Comparative Study of Short Word-Length Fixed-Point, Floating-Point, and LNS Arithmetic Units." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/37411064866379001880.

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碩士<br>逢甲大學<br>資訊工程所<br>93<br>Arithmetic units are the main components of digital systems for performing the fundamental operations of arithmetic, especially for microprocessors and digital signal processors. When designing arithmetic units, different number systems will result in different architecture, precision, circuit area, delay, and power consumption of the circuits. In this thesis, we compare and analyze these different arithmetic systems, including Fixed-Point (FXP), Floating-Point (FLP), and Logarithmic Number Systems (LNS). We discuss the design methodology of short word length units

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Wu, Kun-Yi, and 吳坤益. "Energy-Efficient Multiple-Mode Floating-Point Arithmetic Units and Instruction Precision Assignment Methods." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/bp5f4w.

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博士<br>國立中山大學<br>資訊工程學系研究所<br>102<br>With the rapid growth in applying floating-point (FP) arithmetic to the modem systems, FP arithmetic units have become the main energy consumers in these systems. Fortunately, many FP applications allow a slight output distortion that human senses can neglect or tolerate. In other words, we can trade the energy consumption with output quality of FP applications by reducing the precision of FP instructions (less accurate than IEEE single-precision FP one) via multiple-mode FP arithmetic units. However, how to quickly and effectively assign each FP instruction

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42

Shao-MingLai and 賴紹銘. "Design of Floating-Point Special Function Units with Dual-Precision in Multi-Core Systems." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/387e7v.

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43

Tout, Wassim. "Quantitative evaluation of the impact of floating point arithmetic units on the performance of DSP structures." Thesis, 2003. http://spectrum.library.concordia.ca/2422/1/MQ91126.pdf.

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Arithmetic operations traditionally used fixed-point processing because it makes them less expensive. In integer and fixed-point arithmetic, multipliers are larger, slower and consume much more power than adders, which are often neglected in performance evaluation of DSP systems. In floating-point arithmetic that is not true and in this thesis we show that multipliers and adders are equally important. The thesis also emphasizes low power design. For that reason, some of the basic digital filter network structures, built with FP arithmetic units, are revisited to map their performance with diff

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44

Seidel, Peter-Michael [Verfasser]. "On the design of IEEE compliant floating-point units and their quantitative analysis / vorgelegt von Peter-Michael Seidel." 2007. http://d-nb.info/984957855/34.

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Δημητρακόπουλος, Γεώργιος. "Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων". Thesis, 2006. http://nemertes.lis.upatras.gr/jspui/handle/10889/1480.

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Οι μονάδες επεξεργασίας δεδομένων αποτελούν τις βασικές δομικές μονάδες όλων των μικροεπεξεργαστών. Κάποια από τα κυκλώματα αυτής της κατηγορίας υλοποιούν τις βασικές αριθμητικές πράξεις πάνω σε δεδομένα τόσο σταθερής όσο και κινητής υποδιαστολής, ενώ κάποια άλλα αναλαμβάνουν την αναδιοργάνωση των δεδομένων αυτών για την επιτάχυνση του υπολογισμού. Σε επεξεργαστές ειδικού σκοπού, όπως οι επεξεργαστές πολυμέσων και γραφικών, οι μονάδες επεξεργασίας δεδομένων καταλαμβάνουν περισσότερο από το 30% του ολοκληρωμένου και η αποτελεσματική σχεδίαση τους έχει άμεσο αντίκτυπο στην απόδοση ολόκληρου του

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