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Relevant bibliographies by topics / Floorplaning

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Academic literature on the topic 'Floorplaning'

Author: Grafiati

Published: 3 June 2025

Last updated: 23 June 2025

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Journal articles on the topic "Floorplaning"

1

Shanavas, I. Hameem, and Ramaswamy Kannan Gnanamurthy. "Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms." VLSI Design 2011 (October 12, 2011): 1–9. http://dx.doi.org/10.1155/2011/896241.

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Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

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Yu, Shenglu, Shimin Du, and Chang Yang. "A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence Pairs." Applied Sciences 14, no. 7 (2024): 2905. http://dx.doi.org/10.3390/app14072905.

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In integrated circuit (IC) design, floorplanning is an important stage in obtaining the floorplan of the circuit to be designed. Floorplanning determines the performance, size, yield, and reliability of very large-scale integration circuit (VLSI) ICs. The results obtained in this step are necessary for the subsequent continuous processes of chip design. From a computational perspective, VLSI floorplanning is an NP-hard problem, making it difficult to be efficiently solved by classical optimization techniques. In this paper, we propose a deep reinforcement learning floorplanning algorithm based on sequence pairs (SP) to address the placement problem. Reinforcement learning utilizes an agent to explore the search space in sequence pairs to find the optimal solution. Experimental results on the international standard test circuit benchmarks, MCNC and GSRC, demonstrate that the proposed deep reinforcement learning floorplanning algorithm based on sequence pairs can produce a superior solution.

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HE, RUINING, GUOQIANG LIANG, YUCHUN MA, YU WANG, and JINIAN BIAN. "UNIFICATION OF PR REGION FLOORPLANNING AND FINE-GRAINED PLACEMENT FOR DYNAMIC PARTIALLY RECONFIGURABLE FPGAS." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350020. http://dx.doi.org/10.1142/s0218126613500205.

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Dynamic Partially Reconfiguration (DPR) designs provide additional benefits compared to traditional FPGA application. However, due to the lack of support from automatic design tools in current design flow, designers have to manually define the dimensions and positions of Partially Reconfigurable Regions (PR Regions). The following fine-grained placement for system modules is also limited because it takes the floorplanning result as a rigid region constraint. Therefore, the manual floorplanning is laborious and may lead to inferior fine-grained placement results. In this paper, we propose to integrate PR Region floorplanning with fine-grained placement to achieve the global optimization of the whole DPR system. Effective strategies for tuning PR Region floorplanning and apposite analytical evaluation models are customized for DPR designs to handle the co-optimization for both PR Regions and static region. Not only practical reconfiguration cost and specific reconfiguration constraints for DPR system are considered, but also the congestion estimation can be relaxed by our approach. Especially, we established a two-stage stochastic optimization framework which handles different objectives in different optimization stages so that automated floorplanning and global optimization can be achieved in reasonable time. Experimental results demonstrate that due to the flexibility benefit from the unification of PR Region floorplanning and fine-grained placement, our approach can improve 20.9% on critical path delay, 24% on reconfiguration delay, 12% on congestion, and 8.7% on wire length compared to current DPR design method.

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PEDRAM, MASSOUD, and ERNEST S. KUH. "BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING." International Journal of High Speed Electronics and Systems 03, no. 01 (1992): 137–70. http://dx.doi.org/10.1142/s0129156492000060.

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This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top-down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques for satisfying a wide range of constraints (physical, topological, timing) and is, therefore, able to generate floorplans for a number of different layout styles. A systematic and efficient optimization procedure during the selection of suitable floorplan patterns that integrates floorplanning, global routing and pin assignment, a new pin assignment technique based on linear assignment and driven by the global routing solution and floorplan topology, and an effective timing-driven floorplanning scheme are among the other novel features of the floorplanner. These techniques have been incorporated in BEAR-FP, a macrocell layout system developed at the University of California, Berkeley. Results on various placement and floorplanning benchmarks are quite good.

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Jiang, Zhongjie, Zhiqiang Li, and Zhenjie Yao. "Multi-Objective Optimization in 3D Floorplanning." Electronics 13, no. 9 (2024): 1696. http://dx.doi.org/10.3390/electronics13091696.

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Three-dimensional integrated circuits can significantly mitigate the challenges posed by shrinking feature sizes and enable heterogeneous integration. This paper focuses on the 3D floorplanning problem. We formulate it as a multi-objective optimization issue and employ multi-objective simulated annealing to simultaneously optimize area, wirelength and number of vias. During the optimization process, neighboring solutions are explored in the design space through inter-layer or intra-layer perturbations, and decision criteria for the exploration process are formulated based on the dominance relationship of solutions. Test results on the GSRC benchmark demonstrate that our approach delivers superior performance in optimizing area and wirelength. Compared to 2D floorplanning, our method reduces the area by approximately 49% and the wirelength by 21%. Compared to other similar 3D floorplanning methods, we raise the success rate in satisfying the fixed-outline constraint to 100% and improve the wirelength by 3%. The multi-objective simulated annealing method proposed in this paper can effectively address the 3D floorplanning problem.

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WANG, LIN. "FAST ALGORITHMS FOR THERMAL-AWARE FLOORPLANNING." Journal of Circuits, Systems and Computers 23, no. 07 (2014): 1450098. http://dx.doi.org/10.1142/s0218126614500984.

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Thermal-aware floorplanning is an effective way to solve the thermal problem in modern integrated circuit (IC) designs. Existing thermal-aware floorplanning methods are all based on simulated annealing (SA), genetic algorithms (GAs) or linear programming (LP), which are quite time-consuming. In this paper, we propose two fast algorithms for thermal-aware floorplanning, a greedy algorithm based on the less-flexibility-first (LFF) principle and a hybrid algorithm combining the greedy algorithm and an SA-based refinement. The greedy algorithm can fast obtain a locally optimized floorplan with reduced area and temperature. The hybrid method can get similar results compared with pure SA-based approaches but it is still much faster.

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Bourbakis, Nikolaos G., and Mohammad Mortazavi. "A FLOORPLANNING-SYNTHESIS METHODOLOGY FOR MULTIPLE CHIP MODULE DESIGN." Journal of Integrated Design and Process Science: Transactions of the SDPS, Official Journal of the Society for Design and Process Science 4, no. 1 (2000): 67–81. http://dx.doi.org/10.3233/jid-2000-4105.

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The VLSI design automation is one of the most computational expensive and complicated processes with significant impact into computer chips manufacturing, especially at the physical layout design cycle. The recent VLSI evolution in multiple chip modules design has introduced new challenges at the physical layout steps (partitioning, floorplanning, placement, routing, compaction,etc). In this paper an efficient synthesis and floorplanning methodology for Multiple Chip Modules (MCM) design is discussed. The floorplanning-synthesis methodology is based on the efficient hierarchical cooperation of two formal languages (Scan, Geometria). Scan determines an acceptable planning by partitioning the floor area and defining a set of planning patterns on it. Geometria performs the synthesis placement part of the methodology by efficiently placing the chips modules and determining their routing.

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Laudis, Lalin L., and Amit Kumar Sinha. "Metaheuristic Approach for VLSI 3D-Floorplanning." International Journal of Scientific Research 2, no. 12 (2012): 202–3. http://dx.doi.org/10.15373/22778179/dec2013/62.

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Xiang, H., X. Tang, and M. D. F. Wong. "Bus-Driven Floorplanning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 11 (2004): 1522–30. http://dx.doi.org/10.1109/tcad.2004.836728.

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Ma, Qiang, Zaichen Qian, Evangeline F. Y. Young, and Hai Zhou. "MSV-Driven Floorplanning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 8 (2011): 1152–62. http://dx.doi.org/10.1109/tcad.2011.2131890.

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Dissertations / Theses on the topic "Floorplaning"

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Perumalla, Anvesh Kumar. "A Genetic Algorithm for ASIC Floorplanning." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.

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Quiring, Artur [Verfasser]. "Routing-driven Multiobjective 3D Floorplanning / Artur Quiring." München : Verlag Dr. Hut, 2016. http://d-nb.info/1120763010/34.

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Chow, Chee-Seng. "Phoenix : an interactive hierarchical topological floorplanning placer." Thesis, Massachusetts Institute of Technology, 1985. http://hdl.handle.net/1721.1/77677.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, (B.S.)--Massachusetts Institute of Technology, Dept. of Physics; and, (B.S.)--Massachusetts Institute of Technology, Dept. of Mathematics, 1985.<br>Bibliography: leaf 141.<br>by Chee-Seng Chow.<br>M.S.<br>B.S.

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Pang, Yingxin. "Floorplanning algorithms for VLSI physical design automation /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970677.

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Raja, Gopalan Sureshwar. "Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34993.

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FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address the implementation problem using a divide-and-conquer approach. The PATIS automatic floorplanner enables dynamic modular design, which sacrifices some design speed and area optimization for faster implementation of layout changes, including addition of debug logic. Automatic generation of a timing-driven floorplan for a partially reconfigurable design aims to remove the need for implementation iterations to meet all constraints. Floorplan speculation may anticipate small changes to a design. Although PATIS supports incremental design, complete re-implementation is still rapid because the partial bitstream for each block is generated by independent concurrent invocations of the standard Xilinx tools.<br>Master of Science

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Chandrasekharan, Athira. "Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34499.

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FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The PATIS floorplanner enables dynamic modular design, which accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. We focus in this work on incremental and speculative floorplanning in PATIS, to accommodate minor design changes and to proactively generate possible floorplan variants. Current floorplan topology is preserved to minimize ripple effects and maintain reasonable module aspect ratios. The design modules are run-time reconfigurable to enable concurrent module implementation by independent invocations of the standard FPGA tools running on separate cores or hosts.<br>Master of Science

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Almohanadi, A. H. "Application of analytical placement techniques for floorplanning in VLSI design." Thesis, University of Kent, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233396.

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Iyer, Krishnakumar R. "Tabu search algorithm for a thermal aware VLSI floorplanning application." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384426610.

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Healy, Michael Benjamin. "Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures." Thesis, Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10562.

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The main objective of this thesis is to develop a physical design tool that is capable of being used by microarchitects to evaluate the impact of their design decisions on the physical design aspects of future microprocessor development. For deep submicron technology wire delay will scale increasingly badly compared to gate delay and so will become a major bottleneck to performance improvement. Three dimensional integrated circuits (3D ICs) offer a new method of dealing with non-linear wire latency by allowing shorter interconnects that act within their linear region. Thermal considerations in 3D ICs will be more important than traditional designs however, so this problem must also be addressed. This thesis presents a microarchitectural floorplanning tool that will help computer architects to attack the wire delay problem early in the design stages of higher performance microprocessors by including consideration of design for 3D ICs. Consideration of the new problems that occur due to the move to 3D and inherent difficulties with deep submicron design is included. Experiments demonstrate that this tool can generate microprocessor floorplans that include many objectives and continue to enhance performance into the next generation of high performance design.

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Primo, João Janduy Brasileiro. "PadsTool: uma Ferramenta Gráfica para Mapeamento e Posicionamento dos Pads." Universidade Federal da Paraíba, 2013. http://tede.biblioteca.ufpb.br:8080/handle/tede/6126.

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Made available in DSpace on 2015-05-14T12:36:50Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 1579166 bytes, checksum: d3ba80babda5e722f7dbc5aaf9f3a941 (MD5) Previous issue date: 2013-08-30<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior<br>EDA Tools (Electronic Design Automation) are used to facilitate the project and layout of Integrated Circuits (IC). Floorplanning is an important step in the layout design phase of the development of an IC. In this step the macroblocks are positioned on the chip, and the following properties are determined: the location of input and output pads, the location of the power pads and the strategies of distribution of the power and clock signal by the core. Commonly a wrapper in HDL that maps the input and output ports of the project in instances of pads is done, with the different types, defined by the developer and a file that indicates the position of each pad on the circuit. Thus, both the mapping and positioning are usually manually done through scripts, generating a great difficulty for developers, because an IC with a reasonable amount of inputs and outputs becomes extremely susceptible to human failure. These files are generally used by all EDA tools as well as by the Design kits suppliers, moreover, the tools have different syntaxes for the files. This work shows a tool with a GUI (Graphical User Interface) able to provide to the developers an easy and intuitive way to manage both the mapping and positioning of the pads, making the process faster and less susceptive to human failure. To validate the work, the tool is tested on some IC projects<br>As ferramentas EDA (Electronic Design Automation) são utilizadas para facilitar o projeto e desenho de circuitos integrados (CI). O Floorplaning é uma importante etapa na fase de design do layout no desenvolvimento de um CI. Nesta etapa, os macroblocos são posicionados no chip, além de serem decididas: a localização dos pads de entrada e saída, a localização dos pads de alimentação e as estratégias de distribuição da alimentação e do sinal de clock pelo núcleo. Comumente, é feito um wrapper em HDL que mapeia as portas de entrada e saída do projeto em instâncias de Pads, com seus diferentes tipos, definidos pelo desenvolvedor e um arquivo que indica a posição de cada Pad no circuito. Dessa maneira, tanto esse mapeamento quanto tal posicionamento, em geral, são feitos manualmente por meio de scripts, gerando uma dificuldade para os desenvolvedores, pois para um CI com uma quantidade razoável de entradas e saídas esses procedimentos são susceptíveis a falhas. Esses arquivos, em geral, são utilizados em todas as ferramentas EDA e também pelos fornecedores de Design Kits, além disso, as ferramentas possuem sintaxes diferentes para os arquivos. Este trabalho propõe a construção de uma ferramenta com interface gráfica capaz de fornecer aos desenvolvedores uma maneira mais fácil e intuitiva de gerenciar tanto o mapeamento quanto o posicionamento dos pads, tornando o processo mais rápido e menos susceptível a falhas humanas. Para validar o trabalho, a ferramenta é testada em projetos de CI s.

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Books on the topic "Floorplaning"

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Jabri, Marwan A. An Artificial Intelligence Approach to Integrated Circuit Floorplanning. Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-84489-8.

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Jabri, Marwan A. Artificial Intelligence Approach to Integrated Circuit Floorplanning. Springer London, Limited, 2012.

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An Artificial Intelligence Approach to Integrated Circuit Floorplanning. Springer, 2011.

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An artificial intelligence approach to integrated circuit floorplanning. Springer-Verlag, 1991.

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Book chapters on the topic "Floorplaning"

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Lienig, Jens. "Floorplanning." In Layoutsynthese elektronischer Schaltungen. Springer Berlin Heidelberg, 2016. http://dx.doi.org/10.1007/978-3-662-49815-6_3.

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Lee, Seungjun, and Jan Rabaey. "Interactive Floorplanning." In The Kluwer International Series in Engineering and Computer Science. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3570-6_9.

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Jabri, Marwan A. "Integrated Circuit Floorplanning." In Lecture Notes in Engineering. Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-84489-8_2.

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Lengauer, Thomas. "Placement, Assignment, and Floorplanning." In Combinatorial Algorithms for Integrated Circuit Layout. Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_7.

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Emmert, John M., Akash Randhar, and Dinesh Bhatia. "Fast floorplanning for FPGAs." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0055240.

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Sherwani, Naveed A. "Placement, Floorplanning and Pin Assignment." In Algorithms for VLSI Physical Design Automation. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2219-2_5.

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Chen, Hung-Ming, Martin D. F. Wong, Hai Zhou, Fung-Yu Young, Hannah H. Yang, and Naveed Sherwani. "Integrated Floorplanning and Interconnect Planning." In Network Theory and Applications. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3415-7_1.

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Sherwani, Naveed. "Placement, Floorplanning and Pin Assignment." In Algorithms for VLSI Physical Design Automation. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2351-2_5.

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Deng, Yangdong Steve, and Wojciech P. Maly. "Floorplanning for 2.5-D Integration." In 3-Dimensional VLSI. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-04157-0_5.

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Koranne, Sandeep. "Floorplanning: VLSI and other Applications." In Practical Computing on the Cell Broadband Engine. Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_21.

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Conference papers on the topic "Floorplaning"

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Changwen Zhuang and Kajitani. "A new floorplaning by HPG: Hamilton path-based graph representation." In 2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03. IEEE, 2003. http://dx.doi.org/10.1109/icasic.2003.1277517.

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Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki. "High-level synthesis algorithms with floorplaning for distributed/shared-register architectures." In 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2008. http://dx.doi.org/10.1109/vdat.2008.4542438.

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Berezin, Alexander, Maria Shakhmanova, and Vladimir Ivanov. "APPLYING NEURAL COMBINATORIAL OPTIMIZATION TO THE OPTIMAL RETICLE FLOORPLANNING PROBLEM." In International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1642.silicon-2020/335-338.

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This work considers the application of recursive neural combinatorial optimization to the problem of optimal reticle floorplanning. It also proposes the use of reinforcement learning from human preferences as an optimization criterion.

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Hua Xiang, Xiaoping Tang, and M. D. F. Wong. "Bus-Driven Floorplanning." In ICCAD-2003. International Conference on Computer Aided Design. IEEE, 2003. http://dx.doi.org/10.1109/iccad.2003.159672.

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Feng, Yan, Dinesh P. Mehta, and Hannah Yang. "Constrained "Modern" Floorplanning." In the 2003 international symposium. ACM Press, 2003. http://dx.doi.org/10.1145/640000.640030.

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Kahng, Andrew B. "Classical floorplanning harmful?" In the 2000 international symposium. ACM Press, 2000. http://dx.doi.org/10.1145/332357.332401.

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Casu, Mario R., and Luca Macchiarulo. "Floorplanning for throughput." In the 2004 international symposium. ACM Press, 2004. http://dx.doi.org/10.1145/981066.981081.

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Xu, Gang, Ruiqi Tian, Martin D. Wong, and Alfred J. Reich. "Shuttle mask floorplanning." In Photomask Technology, edited by Kurt R. Kimmel and Wolfgang Staud. SPIE, 2003. http://dx.doi.org/10.1117/12.517568.

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Browning, David, Ayman El Ansary, and Mohamed Shalaby. "System floorplanning optimization." In 2011 International Conference on Energy Aware Computing (ICEAC 2011). IEEE, 2011. http://dx.doi.org/10.1109/iceac.2011.6403631.

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Browning, David W., Ayman M. El Ansary, and Mohamed Shalaby. "System floorplanning optimization." In 2012 International Conference on Energy Aware Computing (ICEAC). IEEE, 2012. http://dx.doi.org/10.1109/iceac.2012.6471007.

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Reports on the topic "Floorplaning"

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Sankaranarayanan, Karthik, Sivakumar Velusamy, Kevin Skadron, and Mircea Stan. Microarchitectural Floorplanning for Thermal Management: A Technical Report. Defense Technical Information Center, 2005. http://dx.doi.org/10.21236/ada436653.

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Mohapatra, Sucheta. Dynamic Through-Silicon Via Clustering in 3D IC Floorplanning for Early Performance Optimization. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.7437.

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