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1
Perumalla, Anvesh Kumar. "A Genetic Algorithm for ASIC Floorplanning." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.
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Quiring, Artur [Verfasser]. "Routing-driven Multiobjective 3D Floorplanning / Artur Quiring." München : Verlag Dr. Hut, 2016. http://d-nb.info/1120763010/34.
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Chow, Chee-Seng. "Phoenix : an interactive hierarchical topological floorplanning placer." Thesis, Massachusetts Institute of Technology, 1985. http://hdl.handle.net/1721.1/77677.
Full textAbstract:
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, (B.S.)--Massachusetts Institute of Technology, Dept. of Physics; and, (B.S.)--Massachusetts Institute of Technology, Dept. of Mathematics, 1985.Bibliography: leaf 141.
by Chee-Seng Chow.
M.S.
B.S.
4
Pang, Yingxin. "Floorplanning algorithms for VLSI physical design automation /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970677.
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Chandrasekharan, Athira. "Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34499.
Full textAbstract:
FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The PATIS floorplanner enables dynamic modular design, which accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. We focus in this work on incremental and speculative floorplanning in PATIS, to accommodate minor design changes and to proactively generate possible floorplan variants. Current floorplan topology is preserved to minimize ripple effects and maintain reasonable module aspect ratios. The design modules are run-time reconfigurable to enable concurrent module implementation by independent invocations of the standard FPGA tools running on separate cores or hosts.Master of Science
6
Raja, Gopalan Sureshwar. "Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34993.
Full textAbstract:
FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address the implementation problem using a divide-and-conquer approach. The PATIS automatic floorplanner enables dynamic modular design, which sacrifices some design speed and area optimization for faster implementation of layout changes, including addition of debug logic. Automatic generation of a timing-driven floorplan for a partially reconfigurable design aims to remove the need for implementation iterations to meet all constraints. Floorplan speculation may anticipate small changes to a design. Although PATIS supports incremental design, complete re-implementation is still rapid because the partial bitstream for each block is generated by independent concurrent invocations of the standard Xilinx tools.Master of Science
7
Almohanadi, A. H. "Application of analytical placement techniques for floorplanning in VLSI design." Thesis, University of Kent, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233396.
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Iyer, Krishnakumar R. "Tabu search algorithm for a thermal aware VLSI floorplanning application." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384426610.
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Healy, Michael Benjamin. "Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures." Thesis, Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10562.
Full textAbstract:
The main objective of this thesis is to develop a physical design tool that is capable of being used by microarchitects to evaluate the impact of their design decisions on the physical design aspects of future microprocessor development. For deep submicron technology wire delay will scale increasingly badly compared to gate delay and so will become a major bottleneck to performance improvement. Three dimensional integrated circuits (3D ICs) offer a new method of dealing with non-linear wire latency by allowing shorter interconnects that act within their linear region. Thermal considerations in 3D ICs will be more important than traditional designs however, so this problem must also be addressed.
This thesis presents a microarchitectural floorplanning tool that will help computer architects to attack the wire delay problem early in the design stages of higher performance microprocessors by including consideration of design for 3D ICs. Consideration of the new problems that occur due to the move to 3D and inherent difficulties with deep submicron design is included. Experiments demonstrate that this tool can generate microprocessor floorplans that include many objectives and continue to enhance performance into the next generation of high performance design.
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Fernando, Pradeep R. "Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001549.
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"Interconnect-driven floorplanning." 2002. http://library.cuhk.edu.hk/record=b5891078.
Full textAbstract:
Sham Chiu Wing.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 107-113).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivations --- p.1
Chapter 1.2 --- Progress on the Problem --- p.2
Chapter 1.3 --- Our Contributions --- p.3
Chapter 1.4 --- Thesis Organization --- p.5
Chapter 2 --- Preliminaries --- p.6
Chapter 2.1 --- Introduction --- p.6
Chapter 2.1.1 --- The Role of Floorplanning --- p.6
Chapter 2.1.2 --- Wirelength Estimation --- p.7
Chapter 2.1.3 --- Different Types of Floorplan --- p.8
Chapter 2.2 --- Representations of Floorplan --- p.10
Chapter 2.2.1 --- Polish Expressions --- p.10
Chapter 2.2.2 --- Sequence Pair --- p.11
Chapter 2.2.3 --- Bounded-Sliceline Grid (BSG) Structure --- p.13
Chapter 2.2.4 --- O-Tree --- p.14
Chapter 2.2.5 --- B*-Tree --- p.16
Chapter 2.2.6 --- Corner Block List --- p.18
Chapter 2.2.7 --- Twin Binary Tree --- p.19
Chapter 2.2.8 --- Comparisons between Different Representations --- p.20
Chapter 2.3 --- Algorithms of Floorplan Design --- p.20
Chapter 2.3.1 --- Constraint Based Floorplanning --- p.21
Chapter 2.3.2 --- Integer Programming Based Floorplanning --- p.21
Chapter 2.3.3 --- Neural Learning Based Floorplanning --- p.22
Chapter 2.3.4 --- Rectangular Dualization --- p.22
Chapter 2.3.5 --- Simulated Annealing --- p.23
Chapter 2.3.6 --- Genetic Algorithm --- p.23
Chapter 2.4 --- Summary --- p.24
Chapter 3 --- Literature Review on Interconnect-Driven Floorplanning --- p.25
Chapter 3.1 --- Introduction --- p.25
Chapter 3.2 --- Simulated Annealing Approach --- p.25
Chapter 3.2.1 --- """Pepper - A Timing Driven Early Floorplanner""" --- p.25
Chapter 3.2.2 --- """A Timing Driven Block Placer Based on Sequence Pair Model""" --- p.26
Chapter 3.2.3 --- """Integrated Floorplanning and Interconnect Planning""" --- p.27
Chapter 3.2.4 --- """Interconnect Driven Floorplanning with Fast Global Wiring Planning and Optimization""" --- p.27
Chapter 3.3 --- Genetic Algorithm Approach --- p.28
Chapter 3.3.1 --- "“Timing Influenced General-cell Genetic Floorplanning""" --- p.28
Chapter 3.4 --- Force Directed Approach --- p.29
Chapter 3.4.1 --- """Timing Influenced Force Directed Floorplanning""" --- p.29
Chapter 3.5 --- Congestion Planning --- p.30
Chapter 3.5.1 --- """On the Behavior of Congestion Minimization During Placement""" --- p.30
Chapter 3.5.2 --- """Congestion Minimization During Placement""" --- p.31
Chapter 3.5.3 --- "“Estimating Routing Congestion Using Probabilistic Anal- ysis""" --- p.31
Chapter 3.6 --- Buffer Planning --- p.32
Chapter 3.6.1 --- """Buffer Block Planning for Interconnect Driven Floor- planning""" --- p.32
Chapter 3.6.2 --- """Routability Driven Repeater Block Planning for Interconnect- centric Floorplanning""" --- p.33
Chapter 3.6.3 --- """Provably Good Global Buffering Using an Available Block Plan""" --- p.34
Chapter 3.6.4 --- "“Planning Buffer Locations by Network Flows""" --- p.34
Chapter 3.6.5 --- """A Practical Methodology for Early Buffer and Wire Re- source Allocation""" --- p.35
Chapter 3.7 --- Summary --- p.36
Chapter 4 --- Floorplanner with Fixed Buffer Planning [34] --- p.37
Chapter 4.1 --- Introduction --- p.37
Chapter 4.2 --- Overview of the Floorplanner --- p.38
Chapter 4.3 --- Congestion Model --- p.38
Chapter 4.3.1 --- Construction of Grid Structure --- p.39
Chapter 4.3.2 --- Counting the Number of Routes at a Grid --- p.40
Chapter 4.3.3 --- Buffer Location Computation --- p.41
Chapter 4.3.4 --- Counting Routes with Blocked Grids --- p.42
Chapter 4.3.5 --- Computing the Probability of Net Crossing --- p.43
Chapter 4.4 --- Time Complexity --- p.44
Chapter 4.5 --- Simulated Annealing --- p.45
Chapter 4.6 --- Wirelength Estimation --- p.46
Chapter 4.6.1 --- Center-to-center Estimation --- p.47
Chapter 4.6.2 --- Corner-to-corner Estimation --- p.47
Chapter 4.6.3 --- Intersection-to-intersection Estimation --- p.48
Chapter 4.7 --- Multi-pin Nets Handling --- p.49
Chapter 4.8 --- Experimental Results --- p.50
Chapter 4.9 --- Summary --- p.51
Chapter 5 --- Floorplanner with Flexible Buffer Planning [35] --- p.53
Chapter 5.1 --- Introduction --- p.53
Chapter 5.2 --- Overview of the Floorplanner --- p.54
Chapter 5.3 --- Congestion Model --- p.55
Chapter 5.3.1 --- Probabilistic Model with Variable Interval Buffer Inser- tion Constraint --- p.57
Chapter 5.3.2 --- Time Complexity --- p.61
Chapter 5.4 --- Buffer Planning --- p.62
Chapter 5.4.1 --- Estimation of Buffer Usage --- p.62
Chapter 5.4.2 --- Estimation of Buffer Resources --- p.69
Chapter 5.5 --- Two-phases Simulated Annealing --- p.70
Chapter 5.6 --- Wirelength Estimation --- p.72
Chapter 5.7 --- Multi-pin Nets Handling --- p.73
Chapter 5.8 --- Experimental Results --- p.73
Chapter 5.9 --- Remarks --- p.76
Chapter 5.10 --- Summary --- p.76
Chapter 6 --- Global Router --- p.77
Chapter 6.1 --- Introduction --- p.77
Chapter 6.2 --- Overview of the Global Router --- p.77
Chapter 6.3 --- Buffer Insertion Constraint and Congestion Constraint --- p.78
Chapter 6.4 --- Multi-pin Nets Handling --- p.79
Chapter 6.5 --- Routing Methodology --- p.79
Chapter 6.6 --- Implementation --- p.80
Chapter 6.7 --- Summary --- p.86
Chapter 7 --- Interconnect-Driven Floorplanning by Alternative Packings --- p.87
Chapter 7.1 --- Introduction --- p.87
Chapter 7.2 --- Overview of the Method --- p.87
Chapter 7.3 --- Searching Alternative Packings --- p.89
Chapter 7.3.1 --- Rectangular Supermodules in Sequence Pair --- p.89
Chapter 7.3.2 --- Finding rearrangable module sets --- p.90
Chapter 7.3.3 --- Alternative Sequence Pairs --- p.94
Chapter 7.4 --- Implementation --- p.97
Chapter 7.4.1 --- Re-calculation of Interconnect Cost --- p.98
Chapter 7.4.2 --- Cost Function --- p.101
Chapter 7.4.3 --- Time Complexity --- p.101
Chapter 7.5 --- Experimental Results --- p.101
Chapter 7.6 --- Summary --- p.103
Chapter 8 --- Conclusion --- p.105
Bibliography --- p.107
12
"Bus-driven floorplanning." 2005. http://library.cuhk.edu.hk/record=b5892576.
Full textAbstract:
Law Hoi Ying.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.
Includes bibliographical references (leaves 101-106).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- VLSI Design Cycle --- p.2
Chapter 1.2 --- Physical Design Cycle --- p.6
Chapter 1.3 --- Floorplanning --- p.10
Chapter 1.3.1 --- Floorplanning Objectives --- p.11
Chapter 1.3.2 --- Common Approaches --- p.12
Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14
Chapter 1.4 --- Motivations and Contributions --- p.15
Chapter 1.5 --- Organization of the Thesis --- p.17
Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18
Chapter 2.1 --- Types of Floorplans --- p.18
Chapter 2.2 --- Floorplan Representations --- p.20
Chapter 2.2.1 --- Slicing Floorplan --- p.21
Chapter 2.2.2 --- Non-slicing Floorplan --- p.22
Chapter 2.2.3 --- Mosaic Floorplan --- p.30
Chapter 2.3 --- Summary --- p.35
Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37
Chapter 3.1 --- Introduction --- p.37
Chapter 3.2 --- Problem Formulation --- p.38
Chapter 3.3 --- Previous Work --- p.38
Chapter 3.4 --- Summary --- p.42
Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44
Chapter 4.1 --- Problem Formulation --- p.44
Chapter 4.2 --- Previous Work --- p.45
Chapter 4.2.1 --- Abutment Constraint --- p.45
Chapter 4.2.2 --- Alignment Constraint --- p.49
Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52
Chapter 4.3 --- Summary --- p.53
Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55
Chapter 5.1 --- Introduction --- p.55
Chapter 5.2 --- Problem Formulation --- p.56
Chapter 5.3 --- Methodology --- p.57
Chapter 5.3.1 --- Shape Validation --- p.58
Chapter 5.3.2 --- Bus Ordering --- p.65
Chapter 5.3.3 --- Floorplan Realization --- p.72
Chapter 5.3.4 --- Simulated Annealing --- p.73
Chapter 5.3.5 --- Soft Block Adjustment --- p.75
Chapter 5.4 --- Experimental Results --- p.75
Chapter 5.5 --- Summary --- p.77
Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80
Chapter 6.1 --- Introduction --- p.80
Chapter 6.2 --- Problem Formulation --- p.81
Chapter 6.3 --- The Representation --- p.82
Chapter 6.3.1 --- Overview --- p.82
Chapter 6.3.2 --- Review of TCG --- p.83
Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84
Chapter 6.3.4 --- Aligning Blocks --- p.85
Chapter 6.3.5 --- Solution Perturbation --- p.87
Chapter 6.4 --- Simulated Annealing --- p.92
Chapter 6.5 --- Soft Block Adjustment --- p.92
Chapter 6.6 --- Experimental Results --- p.93
Chapter 6.7 --- Summary --- p.94
Chapter 6.8 --- Acknowledgement --- p.95
Chapter 7 --- Conclusion --- p.99
Bibliography --- p.101
13
Wang, Tai-Lung, and 王泰隆. "3D VLSI Floorplanning." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/mq547q.
Full textAbstract:
碩士國立臺北科技大學
電機工程系所
101
As the complexity of integrated circuits have grown rapidly in recent years, the interconnect delay, cost, heat and yield rate became the bottleneck of traditional 2D architecture. The emerging 3D architecture used the technique of Through-Silicon-Via (TSV), by stacking the circuits and connecting each layer with TSVs. It can improve interconnect density, reduce form factor, increase speed and reduce power consumption. In this thesis, we propose an efficient methodology of 3D floorplanning. Firstly, we use a greedy merging approach to work with relax Polish expression based on simulated annealing algorithm. Secondly, we apply a matching method to choose the TSVs. Finally, we use constrained longest common subsequence (CLCS) to perform full-compact or half-compact on the modules and then calculate the total wire length. GSRC and MCNC Benchmark are used as test circuits in out experiments. The experimental results show that our approach works efficiently and it can further reduce the total wire length.
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Feng, Kuan-Chung, and 馮冠中. "Floorplanning,TSVAssignmentandPinAssignmentfor3D-ICDesigns." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/79273593373474596412.
Full textAbstract:
碩士國立清華大學
資訊工程學系
98
由於製程越做越小導致晶片上之連線問題複雜化，三維立體積體電路視為一種可以消除連線問題複雜化的方法。然而，直通矽晶穿孔用來連接不同層的技術在三維立體積體電路設計下是設計的問題之一。這篇論文主要探討在三維立體積體電路設計下之平面規劃、分派直通矽晶穿孔及分派腳位之方法。首先，為了找到一個好的平面規劃，我們利用一種延後決定最後平面規劃結果的方法來產生一個不錯的解。接著透過重新規劃可用空間的方法讓直通矽晶穿孔能放在不錯的位置上。另外值得一提的是直通矽晶穿孔的位置是絕對位置；也就是說，我們準確地找到直通矽晶穿孔在該平面規劃下的座標。最後，考慮腳位在三維立體積體電路下的位置。不同於傳統的考量，我們將考慮腳位可以放置在每一個區塊範圍內的任意位置上。透過實驗結果得知，我們除了有效找到直通矽晶穿孔的絕對位置之外，不同於傳統的分派腳位位置，我們能夠獲得更好的總線長；同時，我們的方法也透過有效的整合，讓執行時間能在短時間內完成。
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Chang, Chung-Chiao, and 張仲喬. "Congestion-Driven Floorplanning." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/57yyd3.
Full textAbstract:
碩士中原大學
資訊工程研究所
92
Floorplanning plays an important role in physical design of VLSI circuits. It plans the shapes and locations of the modules on the chip, and the result of which will greatly affect the performance of the final circuit. As technology continues to scale down, the number of transistors and interconnections increasing rapidly, chip performance degradation caused by interconnection becomes more and more obvious. Therefore the related problems for interconnection optimization have been processed as early as possible in physical design of VLSI circuits design flow. Area minimization becomes less important while the minimization of interconnection length, the reduction on congestion, and the satisfaction at delay constraints become the major concern in floorplanning. In this study, we analyze the distribution of wire congestion in a floorplan and propose the wire congestion model in response to the optimization problem relating to congestion in a floorplan. The advantages of our new model are listed as follows: (1) The results of the estimated wire congestion in soft module floorplanning by the model is more accurate than those determining position of the I/O pins by intersection-to-intersection method. (2) Different from the probability analysis based congestion model with fixed-size estimating grid, the new model has no shortcoming in how to determine the size of the grid. (3) Time complexity of the new model is O(n^2), where n is the number of modules, such that the time used in estimating the wire congestion is effectively reduced. Furthermore, combining the concept of reshaping and sizing of modules and the new congestion model, the nonlinear mathematical programming model is formulated to solve the congestion minimization problem according to the distribution of wire congestion. We test our new congestion model and mathematical programming based floorplanning algorithm with module partition by three experimental methods: (1) We implement three floorplanning algorithms: embedded the new congestion model; without considering congestion; probability analysis based congestion model with fixed-size estimating grid. Experimental results show that our new model improves the floorplan solution on congestion. (2) We compare our new model with the probabilistic model with different size of fixed-size grid. Experimental results show that congestion can be better optimized using the new model with little penalty in area and wirelength. (3) Furthermore, by partitioning the module based on mathematical programming, we can obviously reduce the congestion of a given floorplan.
16
Fu, Wen-Yu, and 傅文佑. "Multistage Hierarchical Floorplanning." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/79581687971127212149.
Full textAbstract:
碩士中原大學
資訊工程研究所
90
As the process technology enter the deep sub-micron era, the delay effect caused by the interconnection is more and more obvious. Today, how to reduce the interconnection delay effectively has become an important subject when we consider the performance and stability of circuits. Because the position of each module is decided during floorplanning, the overall interconnection delay among modules can be calculated from the result of floorplanning. To solve floorplanning and module placement problems, most of the previous researches attempted to provide placement representations and used the single stage approach based on the simulated annealing algorithm. During the annealing process, the solution will be accepted or not is decided by the objective functions such as where A is the final chip size and W is the total wirelength. The one stage approach based on SA is powerful and can find satisfied solutions for the single optimized objective. However, when we consider the multiple optimization goals on both area and total wirelength at the same time, it is very difficult to find the balanced point for deciding the weighted cofactors , …and so on. We propose a project to develop a multiple stage floorplanning algorithm that can minimize not only the total interconnection wirelength but also the chip area. In the first stage, we propose an algorithm to find an initial floorplan according the interconnection relation of signals among modules. In the second stage, we will develop a hierarchical area minimization algorithm that can premise the module topology generated by the first stage will not be modified violently. And we will introduce the module partition concept of in the second stage to further improve the solution for the area minimization.
17
"Voltage island-driven floorplanning." 2008. http://library.cuhk.edu.hk/record=b5893629.
Full textAbstract:
Ma, Qiang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.
Includes bibliographical references (leaves 78-80).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Background --- p.1
Chapter 1.2 --- Floorplanning --- p.2
Chapter 1.3 --- Motivations --- p.4
Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5
Chapter 1.5 --- Problem Formulation --- p.8
Chapter 1.6 --- Progress on the Problem --- p.10
Chapter 1.7 --- Contributions --- p.12
Chapter 1.8 --- Thesis Organization --- p.14
Chapter 2 --- Literature Review on MSV --- p.15
Chapter 2.1 --- Introduction --- p.15
Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16
Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16
Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18
Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19
Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20
Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21
Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22
Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22
Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23
Chapter 2.4 --- Summary --- p.27
Chapter 3 --- MSV Driven Floorplanning --- p.29
Chapter 3.1 --- Introduction --- p.29
Chapter 3.2 --- Problem Formulation --- p.32
Chapter 3.3 --- Algorithm Overview --- p.33
Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33
Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35
Chapter 3.4.2 --- Proof of Optimality --- p.36
Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37
Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38
Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39
Chapter 3.5 --- Simulated Annealing --- p.39
Chapter 3.5.1 --- Moves --- p.39
Chapter 3.5.2 --- Cost Function --- p.40
Chapter 3.6 --- Experimental Results --- p.40
Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45
Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46
Chapter 3.7 --- Summary --- p.46
Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49
Chapter 4.1 --- Introduction --- p.49
Chapter 4.2 --- Problem Formulation --- p.52
Chapter 4.3 --- Algorithm Overview --- p.56
Chapter 4.4 --- Voltage Assignment Problem --- p.56
Chapter 4.4.1 --- Lagrangian Relaxation --- p.58
Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60
Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64
Chapter 4.4.4 --- Solution Transformation --- p.66
Chapter 4.5 --- Simulated Annealing --- p.69
Chapter 4.5.1 --- Moves --- p.69
Chapter 4.5.2 --- Speeding up heuristic --- p.69
Chapter 4.5.3 --- Cost Function --- p.70
Chapter 4.5.4 --- Annealing Schedule --- p.71
Chapter 4.6 --- Experimental Results --- p.71
Chapter 4.7 --- Summary --- p.72
Chapter 5 --- Conclusion --- p.76
Bibliography --- p.80
18
Shiue, Wen-Hau, and 薛文皓. "Sequence-Pair Based Floorplanning." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/82790537506480837635.
Full textAbstract:
碩士國立交通大學
資訊科學系
87
Floorplanning is an essential step in physical design. Most existing methods consider only the slicing structure, i.e., the structure can be bipartitioned into two slicing structures with a horizontal or vertical cutline, which is often too restricted to model real logic modules accurately. To precisely model real modules, it is desirable to use the non-slicing structure for floorplanning. Among the non-slicing formulations, the sequence pair formulation is getting very popular since its first introduction in 1995 due to its advantageous properties for handling module floorplanning. Most existing work on sequence pair based floorplanning only deal with hard modules, i.e. the modules with fixed width and height, resulting in inefficient area utilization. Approaches that can handle soft modules whose shapes can be adjusted are important to achieve better performance design. In this thesis, we address a new heuristic for soft modules floorplanning based on sequence pairs. We first represent logic modules by using the sequence pair structure, then we define a new type of perturbations of moves during simulated annealing to search for a good floorplanning. We also incorporate a timing estimation into the sequence pair representation for early timing planning. Experimental results show that our new perturbation scheme significantly outperforms the traditional perturbations of moves. For example, our new approach results in respective average reductions of 2.06\% and 23.18\% in chip size and dead space based on the sequence pair formulation, compared with the traditional perturbations of moves. Experimental results also show averages of 7.3\% and 14\% improvements in chip size and critical net length, compared with the version of NSC'98 microprocessor floorplanning released in April 1999.
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Lee, Chih-Hung, and 李志宏. "Optimization Problems in Floorplanning." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/pq3dqa.
Full textAbstract:
博士中原大學
電子工程研究所
92
In this thesis, we study several floorplan optimization problems. First, we study the area minimization problem by introducing the module partition technique into the mathematical programming formulation for rectilinear shape modules. Under the proposed formulation, soft modules are no longer limited on rectangular shape. Both of hard type and soft type general rectilinear modules can be described in the same model such that our formulation can meet the design trend requirement of System-on-Chip (SOC). Besides, rectilinear soft module is no longer shape-predetermined and the contour is globally decided by the objective function of the optimization problem. Due to the revolution on IC process technology, the delay effect of interconnection becomes more and more critical. To solve the timing closure problem in physical design such that designs can meet the timing constraints is a very important topic. Besides, as the increasing on design complexity, the number of module on a chip becomes more and more. To design a fast and effective floorplanner is necessary and urgent. Thus, for the interconnection driven soft module floorplanning problem, we present a new multistage hierarchical floorplanning algorithm for soft modules. This algorithm is integrated with a fast and effective interconnect-driven module placement and hierarchical chip area minimization method. As the progress of both design and manufacturing technology, the clock planning in earlier design stage becomes a necessary and important topic. Finally, we study the problem of clock tree distribution planning in the floorplanning stage and propose a sequence pair based two-stage simulated annealing algorithm that is integrated with a fast zero-skew clock tree generation engine.
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Lin, Yi-Kuang, and 林益廣. "Orthogonal Simulated Annealing for Floorplanning." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/ngwedr.
Full textAbstract:
碩士逢甲大學
資訊工程所
90
Abstract Floorplanning is an essential step in physical design of VLSI. The floorplanning is how to place a set of circuit modules on a chip such that the resulting area is minimized. The best solutions are obtained using simulated annealing based on sequence pair representing the planning of modules. The used simulated annealing conducts a random perturbation operation on the current to generate a candidate solution for each iteration. This paper proposes an orthogonal simulated annealing algorithm which systematically generate a set of candidates containing a number of perturbation operations and consequently reason a good solution bases on orthogonal experimental design. Between experimental factors have lower interaction in an orthogonal experimental design, that have higher perform to consequently reason. So we analyze perturbation operations and design the appropriate perturbation operation for using an orthogonal simulated annealing algorithm. Results of experiments in the MCNC and GSRC benchmark show that our method can effective improve efficacy of current methods, especially in the lager floorplaning.
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Kai-Fu, Tang. "Pipeline-Driven Floorplanning Using TCG." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0108200502260800.
Full text
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"Fixed-outline bus-driven floorplanning." 2011. http://library.cuhk.edu.hk/record=b5894764.
Full textAbstract:
Jiang, Yan.Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.
Includes bibliographical references (p. 87-92).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Physical Design --- p.2
Chapter 1.2 --- Floorplanning --- p.6
Chapter 1.2.1 --- Floorplanning Objectives --- p.7
Chapter 1.2.2 --- Common Approaches --- p.8
Chapter 1.3 --- Motivations and Contributions --- p.14
Chapter 1.4 --- Organization of the Thesis --- p.15
Chapter 2 --- Literature Review on BDF --- p.17
Chapter 2.1 --- Zero-Bend BDF --- p.17
Chapter 2.1.1 --- BDF Using the Sequence-Pair Representation --- p.17
Chapter 2.1.2 --- Using B*-Tree and Fast SA --- p.20
Chapter 2.2 --- Two-Bend BDF --- p.22
Chapter 2.3 --- TCG-Based Multi-Bend BDF --- p.25
Chapter 2.3.1 --- Placement Constraints for Bus --- p.26
Chapter 2.3.2 --- Bus Ordering --- p.28
Chapter 2.4 --- Bus-Pin-Aware BDF --- p.30
Chapter 2.5 --- Summary --- p.33
Chapter 3 --- Fixed-Outline BDF --- p.35
Chapter 3.1 --- Introduction --- p.35
Chapter 3.2 --- Problem Formulation --- p.36
Chapter 3.3 --- The Overview of Our Approach --- p.36
Chapter 3.4 --- Partitioning --- p.37
Chapter 3.4.1. --- The Overview of Partitioning --- p.38
Chapter 3.4.2 --- Building a Hypergraph G --- p.39
Chapter 3.5 --- Floorplaiining with Bus Routing --- p.43
Chapter 3.5.1 --- Find Bus Routes --- p.43
Chapter 3.5.2 --- Realization of Bus Routes --- p.48
Chapter 3.5.3 --- Details of the Annealing Process --- p.50
Chapter 3.6 --- Handle Fixed-Outline Constraints --- p.52
Chapter 3.7 --- Bus Layout --- p.52
Chapter 3.8 --- Experimental Results --- p.56
Chapter 3.9 --- Summary --- p.61
Chapter 4 --- Fixed-Outline BDF with L-shape bus --- p.63
Chapter 4.1 --- Introduction --- p.63
Chapter 4.2 --- Problem Formulation --- p.64
Chapter 4.3 --- Our Approach --- p.65
Chapter 4.3.1 --- Bus Routability Checking --- p.67
Chapter 4.3.2 --- Details of the Annealing Process --- p.79
Chapter 4.4 --- Experimental Results --- p.79
Chapter 4.5 --- Summary --- p.82
Chapter 5 --- Conclusion --- p.85
Bibliography --- p.92
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Tang, Kai-Fu, and 湯凱富. "Pipeline-Driven Floorplanning Using TCG." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/23072439797256097541.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
93
To reduce clock period and facilitate sequential data transfer, it is desired to abut pipeline blocks one by one without predefined directions. In this thesis, we handle the floorplanning with pipeline constraints using the TCG representation. The TCG representation has been shown a flexible and efficient representation. We first explore the necessary conditions with pipeline constraints, and then propose algorithms that can guarantee a feasible floorplan with pipeline constraints during each operation. The experimental results have shown that our algorithm can obtain superior results compared to the method using the sequence-pair representation.
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Chen, HsinLung, and 陳信隆. "Temporal Floorplanning Using 3D-subTCG." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/84276405734736677204.
Full textAbstract:
碩士國立交通大學
資訊科學系
90
A Field programmabe gate array (FPGA) is a (re)programmable logic devices that implements multi-level logic. FPGA's can be configured by designers at their sites, eliminating the time-consuming fabrication step, and thus result in low prototyping cost and short manufacturing times. Currently, FPGA logic cores are widely used as stand-alone devices or parts of system-on-a-chip solutions. As technology advances, FPGA logic capacity are getting higher. To handle the high logic complexity, dynamically reconfigurable FPGAs apply the time-sharing technique to improve logic capacity. In this thesis, we deal with the 3-dimension floorplanning/placement problems in the general reconfigurable device by using a novel floorplan representation, named {\em3D-subTCG} (3-Dimensional sub-Transitive Closure Graph). The 3D-subTCG extends from the recently published Transitive Closure Graph (TCG) representation, by introducing an additional graph to describe the temporal relations between modules. The 3D-subTCG is very simple and can be implemented easily. We derive the feasibility conditions for the precedence constraints induced by the execution of the dynamically reconfigurable FPGAs. Inherited the nice property from the TCG that the geometric relationship are transparent to its representation and its induced operations, we can easily maintain the precedence constraints in 3D-subTCGs. We also derive some properties of the 3D-subTCG to reduce the solution space and shorten the running time for the 3-dimensional foorplanning/placement. Experimental results show that our 3D-subTCG based algorithm can obtain significantly better floorplans than the previous work using reasonable running time.
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Chen, Chien-Chang, and 陳建璋. "Multi-Project Wafer Floorplanning and Dicing." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/26429079828533307247.
Full textAbstract:
碩士國立清華大學
資訊工程學系
93
As the VLSI manufacturing technology advances into the deep sub-micron (DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which puts different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers (1P4M), or 1 poly with 5 metal layers (1P5M). Dies with different desired manufacturing processes cannot be produced from the same wafer, but they can be put onto the same set of masks in order to reduce the total cost of used masks and wafers. In this thesis, we propose a novel integer linear programming (ILP)-based floorplanner for shuttle runs consisting of projects requiring different desired processes. A simulated annealing-based side-to-side wafer dicing planner which takes into account the circular shape of the wafer is also presented. This problem formulation was not considered and discussed before. Experimental results show that our approach achieves 28% wafer reduction on average compared to a previous simulated annealing-based reticle floorplanner.
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"Predictive floorplanning with fixed outline constraint." 2008. http://library.cuhk.edu.hk/record=b5893452.
Full textAbstract:
Leung, Chi Kwan.Thesis submitted in: December 2007.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.
Includes bibliographical references (leaves 66-68).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iii
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Literature Review on Fixed-outline Floorplanning --- p.5
Chapter 2.1 --- General Floorplanning --- p.5
Chapter 2.1.1 --- Simulated Annealing --- p.6
Example - Normalized Polish Expression --- p.9
Example - Sequence Pair Representation --- p.15
Example - Corner Block List --- p.19
Chapter 2.1.2 --- Genetic Algorithm --- p.24
Chapter 2.1.3 --- Mixed Integer Linear Programming --- p.25
Chapter 2.1.4 --- Geometric Programming --- p.25
Chapter 2.1.5 --- Discussion --- p.26
Advantages of using Simulated Annealing --- p.26
Disadvantages of using Simulated Annealing --- p.27
Chapter 2.2 --- Fixed-outline Floorplanning --- p.28
Chapter 2.2.1 --- Motivation --- p.28
Chapter 2.2.2 --- Dimension Based Cost Function --- p.30
Chapter 2.2.3 --- Aspect Ratio Based Cost Function --- p.32
Chapter 2.2.4 --- Evolutionary Search --- p.33
Chapter 2.2.5 --- Instance Augmentation --- p.35
Chapter 3 --- Predictive Rating with Fixed Outline Constraints --- p.39
Chapter 3.1 --- Introduction --- p.39
Chapter 3.2 --- Motivation --- p.40
Chapter 3.3 --- Predictive Rating Scheme --- p.44
Chapter 3.3.1 --- Area --- p.45
Chapter 3.3.2 --- Dimensions --- p.46
Chapter 3.3.3 --- Aspect Ratio --- p.47
Chapter 3.3.4 --- Overall Equation for Predictive Rating --- p.48
Chapter 3.4 --- Integration into the Floorplanner --- p.49
Chapter 3.5 --- Experimental Results --- p.50
Chapter 3.5.1 --- Accuracy of Predictive Rating --- p.50
Chapter 3.5.2 --- Test One --- p.52
Chapter 3.5.3 --- Test Two --- p.57
Chapter 3.6 --- Conclusion --- p.61
Chapter 4 --- Conclusion --- p.64
Bibliography --- p.66
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"Efficient approaches in interconnect-driven floorplanning." 2003. http://library.cuhk.edu.hk/record=b5891548.
Full textAbstract:
Lai Tsz Wai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.
Includes bibliographical references (leaves 123-129).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- VLSI Design Cycle --- p.2
Chapter 1.2 --- Physical Design Cycle --- p.4
Chapter 1.3 --- Floorplanning --- p.7
Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11
Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13
Chapter 1.4 --- Motivations and Contributions --- p.17
Chapter 1.5 --- Organization of this Thesis --- p.18
Chapter 2 --- Literature Review on Floorplan Representation --- p.20
Chapter 2.1 --- Slicing Floorplan Representation --- p.20
Chapter 2.1.1 --- Normalized Polish Expression --- p.20
Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21
Chapter 2.2.1 --- Sequence Pair (SP) --- p.21
Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23
Chapter 2.2.3 --- O-tree --- p.25
Chapter 2.2.4 --- B*-tree --- p.26
Chapter 2.3 --- Mosaic Floorplan Representations --- p.28
Chapter 2.3.1 --- Corner Block List (CBL) --- p.28
Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31
Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32
Chapter 2.4 --- Summary --- p.34
Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37
Chapter 3.1 --- Wirelength Estimation --- p.37
Chapter 3.2 --- Congestion Optimization --- p.38
Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41
Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43
Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44
Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46
Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48
Chapter 3.3 --- Buffer Planning --- p.49
Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51
Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55
Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58
Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60
Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60
Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62
Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63
Chapter 3.4 --- Summary --- p.66
Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68
Chapter 4.1 --- Introduction --- p.68
Chapter 4.2 --- Overview of Our Floorplanner --- p.70
Chapter 4.3 --- Wire Density Model --- p.71
Chapter 4.3.1 --- Computation of Ni --- p.72
Chapter 4.3.2 --- Computation of Pi --- p.74
Chapter 4.3.3 --- Usage of Mirror TBT --- p.76
Chapter 4.4 --- Implementation --- p.76
Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76
Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81
Chapter 4.4.3 --- Cost Function --- p.81
Chapter 4.4.4 --- Complexity --- p.81
Chapter 4.5 --- Experimental Results --- p.82
Chapter 4.6 --- Conclusion --- p.83
Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85
Chapter 5.1 --- Introduction --- p.85
Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87
Chapter 5.3 --- Overview of Our Floorplanner --- p.88
Chapter 5.4 --- Buffer Planning --- p.89
Chapter 5.4.1 --- Feasible Grids --- p.89
Chapter 5.4.2 --- Table Look-up Approach --- p.89
Chapter 5.5 --- Implementation --- p.91
Chapter 5.5.1 --- Building the Look-up Tables --- p.91
Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94
Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101
Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105
Chapter 5.5.5 --- I/O Pin Locations --- p.106
Chapter 5.5.6 --- Cost Function --- p.110
Chapter 5.5.7 --- Complexity --- p.111
Chapter 5.6 --- Experimental Results --- p.112
Chapter 5.6.1 --- Selected Value for A --- p.112
Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113
Chapter 5.7 --- Conclusion --- p.116
Chapter 6 --- Conclusion --- p.118
Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120
Bibliography --- p.123
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"Reticle floorplanning and voltage island partitioning." 2006. http://library.cuhk.edu.hk/record=b5892947.
Full textAbstract:
Ching Lap Sze.Thesis (M.Phil.)--Chinese University of Hong Kong, 2006.
Includes bibliographical references (leaves 69-71).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Shuttle Mask --- p.2
Chapter 1.2 --- Voltage Island --- p.6
Chapter 1.3 --- Structure of the Thesis --- p.8
Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9
Chapter 2.1 --- Introduction --- p.9
Chapter 2.1.1 --- Problem formulation --- p.10
Chapter 2.2 --- Slicing Floorplan --- p.10
Chapter 2.3 --- General Floorplan --- p.11
Chapter 2.3.1 --- Conflict Graph Approaches --- p.11
Chapter 2.3.2 --- Integer Linear Programming Approaches --- p.14
Chapter 2.4 --- Grid Packing --- p.15
Chapter 2.4.1 --- "(α,β,γ)-restricted Grid Approach" --- p.15
Chapter 2.4.2 --- Branch and Bound Searching Approach --- p.17
Chapter 3 --- Shuttle Mask Floorplanning --- p.18
Chapter 3.1 --- Problem Description --- p.18
Chapter 3.2 --- An Overview --- p.20
Chapter 3.3 --- Modified α-Restricted Grid --- p.21
Chapter 3.4 --- Branch and Bound Algorithm --- p.23
Chapter 3.4.1 --- Feasibility Check --- p.25
Chapter 3.5 --- Dicing Plan --- p.30
Chapter 3.6 --- Experimental Result --- p.30
Chapter 4 --- Literature Review on Voltage Island Partitioning --- p.36
Chapter 4.1 --- Introduction --- p.36
Chapter 4.1.1 --- Problem Definition --- p.36
Chapter 4.2 --- Dynamic Programming --- p.38
Chapter 4.2.1 --- Problem Definition --- p.38
Chapter 4.2.2 --- Algorithm Overview --- p.38
Chapter 4.2.3 --- Size Reduction --- p.39
Chapter 4.2.4 --- Approximate Voltage-Partitioning --- p.40
Chapter 4.3 --- Quad-tree Approach --- p.41
Chapter 5 --- Voltage Island Partitioning --- p.44
Chapter 5.1 --- Introduction --- p.44
Chapter 5.2 --- Problem Formulation --- p.45
Chapter 5.3 --- Methodology --- p.46
Chapter 5.3.1 --- Coarsening and Graph Construction --- p.47
Chapter 5.3.2 --- Tree Construction --- p.49
Chapter 5.3.3 --- Optimal Tree Partitioning --- p.50
Chapter 5.3.4 --- Tree Refinement --- p.52
Chapter 5.3.5 --- Solution Legalization --- p.53
Chapter 5.3.6 --- Time Complexity --- p.54
Chapter 5.4 --- Direct Method --- p.55
Chapter 5.4.1 --- Dual Grid-partitioning Problem (DGPP) --- p.56
Chapter 5.4.2 --- Time Complexity --- p.58
Chapter 5.5 --- Experimental Results --- p.59
Chapter 6 --- Conclusion --- p.66
Bibliography --- p.69
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Po-HsunWu and 吳柏勳. "Bus-Pin-Aware Bus-Driven Floorplanning." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/96807242933914073986.
Full textAbstract:
碩士國立成功大學
資訊工程學系碩博士班
98
As the number of buses increase substantially in multi-core SoC designs, the bus planning problem has become the dominant factor in determining the performance and power consumption of SoC designs. To cope with the bus planning problem, it is desirable to consider this issue in early floorplanning stage. Recently, bus-driven floorplanning problem has attracted much attention in the literature. However, current algorithms adopt an over-simplified formulation ignoring the position and orientation of the bus pins, the chip performance may be deteriorated. In this paper, we propose the bus-driven floorplanning algorithm that fully considers the impacts of the bus pins. By fully utilizing the position and orientation of the bus pins, bus bendings are not restricted to occur at the modules on the bus, then it has more flexibility during bus routing. With more flexibility on the bus shape, the size of the solution space is increased and a better bus-driven floorplanning solution can be obtained. Compared with the bus-driven floorplanner [6], the experimental results show that our algorithm performs better in runtime by 3.5X, success rate by 1.2X, wirelength by 1.8X, and reduced the deadspace by 1.2X.
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Yang, Chih-Sheng, and 楊志昇. "Multilayer Floorplanning Using 3D Slicing trees." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/27648088927241654856.
Full text
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Lee, Hsun-Cheng, and 李訓政. "Multilevel Large-scale Module Placement/Floorplanning." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/03188328582449737118.
Full textAbstract:
碩士國立交通大學
資訊科學系
89
We present in this thesis a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage applies quadratic programming (Lagrangian relaxation) to iteratively groups a set of hard (soft) modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the placement/floorplanning solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree scales very well as the circuit size increases while the famous previous works, sequence pair, O-tree, and B*-tree, do not. For circuit sizes ranging from 49 to 9,800 modules and from 408 to 81,600 nets, the MB*-tree consistently obtains high-quality floorplans with dead spaces of less than 3.72% in empirically linear runtime, while standalone sequence pair, O-tree, and B*-tree can handle only up to 196, 196, and 1,960 modules in the same amount of runtime and result in the dead spaces of as large as 27.33%.
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Liu, Ying-Hsiang, and 劉盈享. "Timing-Driven Three-Dimensional IC Floorplanning." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/09181999548837234573.
Full textAbstract:
碩士國立交通大學
電信工程研究所
102
The improvement in the semiconductor technology seems unable to maintain the Moore’s law. Therefore, three-dimensional (3-D) IC is imported to extend this limit. 3-D IC is to stack several 2-D ICs and use through silicon via (TSV) as iter-layer connection. In this thesis, a timing-driven 3-D floorplanner is proposed, and a two-stage timing analysis method is applied to estimate circuit delay. In the first stage, a simple yet efficient look-up table method is adopted, while an accurate timing analysis algorithm is used in second stage. The proposed method can provide a reliable floorplanning result for later steps in physical design flow. Comparing with traditional min-wirelength floorplanner, the proposed algorithm can improve timing slack a lot. ii
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Chen, Wisely, and 陳順隆. "Boundary Constrained Floorplanning Using Sequence Pair." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/90185414972191622453.
Full textAbstract:
碩士國立清華大學
資訊工程學系
88
In this thesis, we will study the boundary constrained floorplanning problem. A floorplan can be classified as slicing or non-slicing structure based on the placement of modules. The floorplan based on non-slicing structure packs modules tighter than floorplan based on slicing structure. Recently, some non-structure representations were proposed. One of these representations is Sequence Pair. Sequence Pair is a very compact representation and can represent all possible floorplan strucutres. In floorplanning, if modules with input/output connections are placed at boundary of the chip, it will save routing area and routing time. Besides, floorplanning is usually done hierarchically in which modules are grouped into different units. It will help if some modules are packed along the boundary of the unit so that they can be put in the neighboring. Therefore, we will focus on the boundary constrained modules placement problem using Sequence Pair representation. First, we will find some rules for Sequence Pair when boundary constraints are given. Based on these rules, we propose a algorithm that will always search solution in legal solution space. In this way, a lot of time is saved due to the pruning of search space. Our algorithm proceeds in two phases: Pos and Neg. Pos permutes the positive sequence using Simulated Annealing and Neg permutes the negative sequence exhaustively.At last, we will show our experimental results.
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Chih-YaoHu and 胡智堯. "3D Floorplanning Methodology Considering Stacked Modules." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/37886256390262725369.
Full textAbstract:
碩士國立成功大學
電機工程學系
103
Floorplanning is a crucial stage in the physical design flow. As semiconductor industry advances, the design of integrated circuits (ICs) is moving toward three-dimensional integrated circuits (3D ICs). Compared to traditional 2D ICs, 3D ICs are able to provide higher device density, smaller chip area, shorter wirelength, etc. It is believed that power consumption can be further reduced if some modules are partitioned and are placed in adjacent dies. The sub-blocks partitioned from a module must be placed at the same coordinate in different dies, and they can be regarded as a stacked module. Stacked memory is one of the important applications in the 3D stacking field, which not only can save power but also can increase its access speed. Hence, it is indeed to have a 3D floorplanner to consider stacked modules under the fixed-outline constraint. This thesis proposes a two-stage methodology to handle this problem. In the first stage, we use an analytical approach to spread modules in the fixed-outline region with the consideration of wirelength. In the second stage, we use the integer linear programming (ILP) to determine the exact locations and shapes of modules to remove overlaps. Moreover, the area constraint of a soft module is transformed to a polyline. This speeds up the process of solving the ILP problem. Experimental results show that our approach not only can obtain better wirelength than Co-place without stacked modules but also can place all stacked modules at identical coordinates under the fixed-outline constraint in 3D ICs. Also, our runtime is faster than applying convex optimization.
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Tsai, Tu-Hsiung, and 蔡篤雄. "Power Switch Allocation Aware Re-Floorplanning." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8nfwqf.
Full textAbstract:
碩士國立交通大學
電子研究所
106
Multi-threshold CMOS (MTCMOS) is currently the most popular methodology in industry for implementing low power designs, which can e ectively reduce the leakage power by turning o inactive circuit power domains. However, power switch allocation needs enough space around macros or SRAM, and the common method of macro place- ment is not applicable. Moreover, people has a habit to place marco manually. With the increasing number of macros in ASIC design, macro placement with distributing minimal space for power switches is a tedious work for designer and costs much time. In this thesis, we propose an e cient and automatic macro re- oorplan framework, which can honor the initial macro oorplan made by designer and generate a ooplan to keep enough space for power switch. In addition, our methedology could judge which macros could be shared power switch ring to save design area. The approach includes a patteren based al- gorithm to overcome non-square-shaped design area and a macro legalization methodolgy with directed acyclic grpah and linear programing. The proposed framework is compli- ant to commercial APR tools and has been integrated into physical design ow in major design-service companies.
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Luo, Chaomin. "Novel Convex Optimization Approaches for VLSI Floorplanning." Thesis, 2008. http://hdl.handle.net/10012/3678.
Full textAbstract:
The floorplanning problem aims to arrange a set of rectangular modules on a rectangular chip area so as to optimize an appropriate
measure of performance. This problem is known to be NP-hard, and is particularly challenging if the chip dimensions are fixed. Fixed-outline floorplanning is becoming increasingly important as a
tool to design flows in the hierarchical design of Application Specific Integrated Circuits and System-On-Chip. Therefore, it has recently received much attention.
A two-stage convex optimization methodology is proposed to solve the fixed-outline floorplanning problem. It is a global optimization problem for wirelength minimization. In the first stage, an
attractor-repeller convex optimization model provides the relative positions of the modules on the floorplan. The second stage places and sizes the modules using convex optimization. Given the relative positions of the modules from the first stage, a Voronoi diagram and Delaunay triangulation method is used to obtain
a planar graph and hence a relative position matrix connecting the two stages. An efficient method for generating sparse relative position matrices and an interchange-free algorithm for local
improvement of the floorplan are also presented.
Experimental results on the standard benchmarks MCNC and GSRC demonstrate that we obtain significant improvements on the best results in the literature. Overlap-free and deadspace-free floorplans are achieved in a fixed outline and floorplans with any specified percentage of whitespace can be produced. Most important, our method provides a greater improvement as the number of modules increases. A very important feature of our methodology is that not only do the dimensions of the floorplans in our experiments comply with the original ones provided in the GSRC
benchmark, but also zero-deadspace floorplans can be obtained. Thus, our approach is able to guarantee complete area utilization in a fixed-outline situation. Our method is also applicable to area minimization in classical floorplanning.
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Chien-Chih, Liao. "Design and Analysis of Compact Floorplanning Algorithms." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1907200611363700.
Full text
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Wu, Kuo-Sheng, and 吳國勝. "Power Distribution with Placement Constraints in Floorplanning." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/20997386010379410916.
Full text
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Hu, Ching-Chung, and 胡競中. "Fast Multilevel Floorplanning for Large Scale Modules." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/53485110456703914509.
Full textAbstract:
碩士逢甲大學
資訊工程所
92
With the advance of deep sub-micron, current methods are not effective to obtain acceptable layout for large scale modules. Hence, it is important to provide designers of SOC with a powerful floorplanner. In traditional pproaches, it is common to simultaneously utilize clustering and declustering technologies, i.e. multiple phases to refine the solution quality. In this thesis, we propose a top-down multilevel floorplanning algorithm to handle the floorplanning and packing for large scale modules. The algorithm is simple and only needs the clustering phase. Experimental results show significantly better running time and promising solutions in comparison with other state-of-the-art research works.
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"TCG-based multi-bend bus driven floorplanning." 2007. http://library.cuhk.edu.hk/record=b5893453.
Full textAbstract:
Ma, Tilen.Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.
Includes bibliographical references (leaves 98-100).
Abstracts in English and Chinese.
Abstract --- p.i
Chapter 0.1 --- Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Physical Design Cycle --- p.2
Chapter 1.2 --- Floorplanning --- p.6
Chapter 1.2.1 --- Floorplanning Objectives --- p.7
Chapter 1.2.2 --- Common Approaches --- p.8
Chapter 1.3 --- Motivations and Contributions --- p.11
Chapter 1.4 --- Organization of the Thesis --- p.13
Chapter 2 --- Literature Review on Placement Constraints in Floorplanning --- p.15
Chapter 2.1 --- Introduction --- p.15
Chapter 2.2 --- Algorithms for Abutment Constraint --- p.16
Chapter 2.3 --- Algorithms for Alignment Constraint --- p.18
Chapter 2.4 --- Algorithms for Boundary Constraint --- p.20
Chapter 2.5 --- Unified Approach for Placement Constraints --- p.23
Chapter 2.5.1 --- Representation of Placement Constraints --- p.23
Chapter 2.5.2 --- Handling Relative Placement Constraints --- p.24
Chapter 2.5.3 --- Examples for Handling Placement Constraints --- p.25
Chapter 3 --- Literature Review on Bus-Driven Floorplanning --- p.28
Chapter 3.1 --- Introduction --- p.28
Chapter 3.2 --- Previous Work --- p.28
Chapter 3.2.1 --- Zero-Bend Bus-Driven Floorplanning [3] --- p.28
Chapter 3.2.2 --- Two-Bend Bus-Driven Floorplanning [1] --- p.32
Chapter 4 --- Placement Constraints for Multi-Bend Bus in TCGs --- p.38
Chapter 4.1 --- Introduction --- p.38
Chapter 4.2 --- Transitive Closure Graph [6] --- p.39
Chapter 4.3 --- Placement Constraints for Zero-Bend Bus --- p.41
Chapter 4.4 --- Placement Constraints for Multi-Bend Bus --- p.44
Chapter 4.5 --- Placement Constraints for Bus Ordering --- p.45
Chapter 4.5.1 --- Natural Bus Ordering in TCGs --- p.45
Chapter 4.5.2 --- Explicit Bus Ordering in TCGs --- p.46
Chapter 5 --- TCG-Based Bus-Driven Floorplanning --- p.48
Chapter 5.1 --- Motivation --- p.48
Chapter 5.2 --- Problem Formulation --- p.49
Chapter 5.3 --- Methodology --- p.50
Chapter 5.3.1 --- Construction of Reduced Graphs --- p.51
Chapter 5.3.2 --- Construction of Common Graph --- p.52
Chapter 5.3.3 --- Spanning Tree for Bus Assignment --- p.53
Chapter 5.3.4 --- Formation of Bus Components --- p.55
Chapter 5.3.5 --- Bus Feasibility Check --- p.56
Chapter 5.3.6 --- Overlap Removal --- p.57
Chapter 5.3.7 --- Floorplan Realization --- p.58
Chapter 5.3.8 --- Simulated Annealing --- p.58
Chapter 5.3.9 --- Soft Module Adjustment --- p.60
Chapter 5.4 --- Experimental Results --- p.60
Chapter 5.5 --- Summary --- p.65
Chapter 6 --- Conclusion --- p.67
Chapter A --- Appendix --- p.69
Chapter A.1 --- Well-Known Algorithms --- p.69
Chapter A.1.1 --- Kruskal's Algorithm --- p.69
Chapter A.1.2 --- Bellman-Ford Algorithm --- p.69
Chapter A.2 --- Figures of Resulting Floorplans --- p.71
Chapter A.2.1 --- Data Set One --- p.71
Chapter A.2.2 --- Data Set Two --- p.80
Chapter A.2.3 --- Data Set Three --- p.85
Chapter A.2.4 --- Data Set Four --- p.92
Bibliography --- p.98
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Lin, Chih-Yuan, and 林志遠. "Floorplanning with consideration of Buffer Resource Allocation." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/3h3xng.
Full textAbstract:
碩士中原大學
資訊工程研究所
93
Abstract Floorplanning is the first stage of the physical design and has significant effect on the performance of the chip. In the past, area was the major concern while interconnect and routability play an important role due to the increasing of the numbers of transistors and wires. Therefore, we should consider interconnect delay, buffer planning and routability as early as possible. In this paper, we propose a floorplanning with consideration of buffer resource allocation. It is a two-stage approach which is based on the simulated annealing. In the first stage, we obtain an initial floorplan with the cost function of area, wire length, and buffer congestion. In the second stage, we allocate space by the estimated buffer congestion information obtained from the first stage. For a floorplan, we take the total buffer congestion on the probabilistic analysis as a metric at the second stage. Experimental results show that our algorithm can estimate the distribution of buffer in advance, and allocate space for the congested region to simultaneously increase the successful rate of buffer insertion and reduce the wire congestion.
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Su, Je-Yan, and 蘇哲彥. "Realization of Multilevel-floorplanning on 3D-VLSI." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/wzrtsf.
Full textAbstract:
碩士國立臺北科技大學
電機工程系研究所
101
Technology is updated continuously. The number of the modules on the chip was complicated. It intends to influence the wirelength and make the design fail. Thus, the 2D planar architecture gradually moved into 3D stack architecture in recent years. Most of the existing floorplanner formulated each layer in the 3D stack into a flat plane and floorplan each layer independently. It would lose the information between layers, and let the relation modules be placed on different corners. Instead, we used an improved layer-aware multilevel floorplanning approach. It partitioned the modules into different layers by K-L algorithm, then used the same algorithm to perform uncorsening for the each layer. During uncorsening phase, modules of the same TSV’s matching will be put closely, even if they belongs to different layers. Then floorplan each partition is floorplanned independently. In our approach, corsening is not necessary. After floorplanning, we use an incremental scanning method to scan possible blank area to decide candidate TSVs, and then apply a TSV’s matching approach retain suitable TSVs from candidate TSVs. Experimental results show that multi-level floorplan with incremental scanning method and TSV’s matching can effectively speed up the calculation and shorten the wirelength.
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Tang, Chih-Chieh, and 唐志傑. "Voltage Island-aware Floorplanning for SoC design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/32082571594069564724.
Full textAbstract:
碩士國立清華大學
資訊工程學系
97
Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for applying MSV's design. Previous works have addressed the MSV's design problem at floorplanning stage by solving the voltage assignment problem and the floorplanning problem separately. In this thesis, we propose a simulated annealing (SA) based voltage island-aware floorplanning algorithm to solve the two problems simultaneously. Our algorithm is based on corner block list [1] which is efficient for integrating the evaluation process of power costs function into SA. Experimental results show that our algorithm could save 31.63\% total power consumption by forming three voltage islands in average. We could obtain better deadspace, total wirelength and power consumption than the previous work [2] as well.
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Jhang, Jia-Ming, and 張家銘. "Incremental Floorplanning by Using Corner Stitching Representation." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51574618795889861247.
Full textAbstract:
碩士大葉大學
電機工程學系
97
Floorplanning is a very important step of physical design in the backend of IC design. As VLSI/SOC systems become more complex, it is probably necessary to reperform floorplanning process for obtaining a better solution if the initial result is unsatisfied. However, it is extremely time consuming to repeatedly perform floorplanning process. For this reason, the idea of incremental floorplanning is adopted to shorten the time and achieve quick physical design closure. In this thesis, we must obtain an initial floorplanning result on any floorplanning representation and record the relative positions among modules by Corner Stitching. To preserve the original positions relationship among modules, a floorplanning will not be reperformed. In fact, a series of incremental operations, including insertion and modification will be performed to derive a floorplanning solution in which chip area is not changed and total routing length is optimal. Experimental results show that the proposed incremental floorplanning algorithm has good performance especially in dealing with instances with small changes.
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Liao, Chien-Chih, and 廖建智. "Design and Analysis of Compact Floorplanning Algorithms." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/56312925361098903396.
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Jan-Yang, Chang, and 張建陽. "Algorithms for VLSI Circuit Partitioning and Floorplanning." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/97011692329395515469.
Full textAbstract:
碩士中原大學
資訊工程研究所
86
In this thesis, we study two important problems arising in VLSI physical design, which are circuit partitioning and floorplanning. For circuit partitioning, the multi-way ratio-cut circuit partitioning problem is addressed, and five efficient spectral algorithms are presented. The common key idea of the first three algorithms is to add a preprocessing step, which effectively groups the vertices into clusters, into one of the currently best spectral algorithms called MELO+DP-RP. The experiment results show that all of the three algorithms can reduce the run time of MELO+DP-RP while maintaining comparable partitioning results. As for the fourth and fifth algorithms, their common key idea is to first treat all the vertices as a cluster, and then repeatedly select a cluster, which gives the maximum cost improvement after being partitioned, and partition it into two new clusters. The bi-partitioning process is continued until the number of clusters equals the number of partitions. The experimental results indicate that the last two algorithm generate much better partitioning results in much less run time than MELO+DP-RP. For floorplanning, the floorplanning problem with routability considerations is formulated, and a new routability-driven floorplanner is presented. The key idea of the new floorplanner is to measure the chip routability in terms of the utilization of each soft block. Based on the idea, the floorplanner is designed by combining the binary search technique and a modified version of the well-known simulated annealing based floorplanner. The experimental results are provided to demonstrate the effectiveness of the new floorplanner.
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Chen, Chi-Ying, and 陳紀穎. "Microarchitecture-Aware Floorplanning for Processor Performance Optimization." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/26005285494600749339.
Full textAbstract:
碩士國立交通大學
電子工程系所
95
In the past, floorplanner used objective functions focused on reducing wire length and area. These objective functions were considered efficient before since the latencies of interconnects were within single clock cycle or even could be neglected. However, as semiconductor technology advances, feature size continues to shrink. The communication of signals on interconnects becomes multi-cycle, therefore the latencies can not be ignored now. These latencies have impact on the performance, and most of current floorplanning frameworks do not consider these issues. We proposed a methodology based on a heuristic for better performance in terms of microarchitecture and floorplanning achieving microarchitecture-aware floorplanning for processor performance optimization. The result from experiments shows the validity of our methodology.
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楊士賢. "Simultaneous Floorplanning and Power/Ground Network Synthesis." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/57432269908596784837.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
91
Signal integrity is emerging as an important issue as very large scale integration (VLSI) technology advances to nanoscale regime. In today's deep submicron (DSM) technology, metal width tends to decrease with length increasing due to the complex system integration. Large current due to a large number of cells switching may cause unacceptable current-resistance (IR) drop. Faster switching frequencies and thinner wires with a lower supply voltage will increase the possibility of functional failures due to the excessive IR drops. Traditionally power distribution network analysis is performed during the transistor-level and post-layout verification. Iteration cost is high at the end of the design flow. In this thesis, in order to achieve the single-pass design methodology, we incorporate a power analysis algorithm into floorplanning stage for early power planning. To ensure the IR drop acceptable at post floorplan. Experimental results based on five MCNC benchmark circuits and a 0.25-um technology show that the predicted IR drop is reduced during the floorplanning stage. With the power analysis considered at the floorplanning stage, we can reduce the IR drop error at the post-layout verification stage.
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Chen, Chun-Yu, and 陳俊宇. "Post-floorplanning Power Optimization in 3D IC." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/06097200949261985934.
Full textAbstract:
碩士國立清華大學
資訊工程學系
99
Multiple Power Domain (MPD) is a technique to optimize power and speed by providing multiple supply voltages to modules. Although there are many research on MPD in 2D IC, less research pay attention to MPD in 3D IC. In Lin’s thesis, an algorithm was applied to MPD in 3D IC to take into account issues such as 3D floorplan, IR drop, temperature, area, etc. based on an integrated architecture of stacked-TSV (Through-Silicon-Via) and power distributed network (STDN-Stacked TSV Distributed Network) proposed by Chen. In this thesis, we propose a post-floorplanning power optimization algorithm to further reduce power given a floorplan of MPD design produced by Lin’s algorithm. Experimental result show that our algorithm achieves more power reduction, less area of footprint and less total wirelength of signal interconnections.
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Wang, Chien-Yen, and 王建延. "A Novel Methodology for VLSI Floorplanning Optimization Problems." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/38311981596693810845.
Full textAbstract:
碩士國立臺北大學
電機工程研究所
97
The explosive growth in technology for very large scale integration (VLSI) circuit design and manufacturing has led to entire systems with millions of components being placed on a single chip. Due to the increasingly high complexity of modern chip design, VLSI CAD tools are vital for delivering high VLSI system performance and there is a requirement for design automation tools for area minimization. Therefore, it is necessary to develop faster floorplan algorithms to minimize floorplan area. Among various approaches to solve the floorplanning problem, Simulated Annealing (SA) algorithm is widely employed. It can achieve the optimal solution using random search methods for the floorplanning problem. However, the drawback of the SA approach is that it is very time-consuming and thus it is difficult handling large scale floorplanning problems. In this thesis, a new and efficient heuristic algorithm is proposed, which is inspired by the game, Tetris ®. The modules are selected one at a time and placed to the partial floorplan, while attempting to grow on upper, in a row-by-row manner, until all the modules are arranged to the floorplan. In one row, modules are tried to be placed without deadspace. Experimental results on the standard MCNC and GSRC benchmarks demonstrate that we obtain significant improvements on the area and runtime. Particularly, our methodology provides greater improvement over the other floorplanners as the number of modules increases, which is a feature of scalability. With such advantage, randomly generated circuits with up to 1100-module are employed to demonstrate the scalability of the proposed model, by choosing 100 test circuits as samples. The area utilization for the 1100-module case is 96.6%, completed within 3.2 minutes. The area utilization of the proposed model show the superiority for solution quality, scalability and robustness. Consequently, it is very suitable to handle large scale floorplanning problems.