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Journal articles on the topic 'Floorplanning'

Author: Grafiati

Published: 4 June 2021

Last updated: 8 June 2024

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1

Shanavas, I. Hameem, and Ramaswamy Kannan Gnanamurthy. "Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms." VLSI Design 2011 (October 12, 2011): 1–9. http://dx.doi.org/10.1155/2011/896241.

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Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

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2

Yu, Shenglu, Shimin Du, and Chang Yang. "A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence Pairs." Applied Sciences 14, no. 7 (March 29, 2024): 2905. http://dx.doi.org/10.3390/app14072905.

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In integrated circuit (IC) design, floorplanning is an important stage in obtaining the floorplan of the circuit to be designed. Floorplanning determines the performance, size, yield, and reliability of very large-scale integration circuit (VLSI) ICs. The results obtained in this step are necessary for the subsequent continuous processes of chip design. From a computational perspective, VLSI floorplanning is an NP-hard problem, making it difficult to be efficiently solved by classical optimization techniques. In this paper, we propose a deep reinforcement learning floorplanning algorithm based on sequence pairs (SP) to address the placement problem. Reinforcement learning utilizes an agent to explore the search space in sequence pairs to find the optimal solution. Experimental results on the international standard test circuit benchmarks, MCNC and GSRC, demonstrate that the proposed deep reinforcement learning floorplanning algorithm based on sequence pairs can produce a superior solution.

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3

HE, RUINING, GUOQIANG LIANG, YUCHUN MA, YU WANG, and JINIAN BIAN. "UNIFICATION OF PR REGION FLOORPLANNING AND FINE-GRAINED PLACEMENT FOR DYNAMIC PARTIALLY RECONFIGURABLE FPGAS." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350020. http://dx.doi.org/10.1142/s0218126613500205.

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Dynamic Partially Reconfiguration (DPR) designs provide additional benefits compared to traditional FPGA application. However, due to the lack of support from automatic design tools in current design flow, designers have to manually define the dimensions and positions of Partially Reconfigurable Regions (PR Regions). The following fine-grained placement for system modules is also limited because it takes the floorplanning result as a rigid region constraint. Therefore, the manual floorplanning is laborious and may lead to inferior fine-grained placement results. In this paper, we propose to integrate PR Region floorplanning with fine-grained placement to achieve the global optimization of the whole DPR system. Effective strategies for tuning PR Region floorplanning and apposite analytical evaluation models are customized for DPR designs to handle the co-optimization for both PR Regions and static region. Not only practical reconfiguration cost and specific reconfiguration constraints for DPR system are considered, but also the congestion estimation can be relaxed by our approach. Especially, we established a two-stage stochastic optimization framework which handles different objectives in different optimization stages so that automated floorplanning and global optimization can be achieved in reasonable time. Experimental results demonstrate that due to the flexibility benefit from the unification of PR Region floorplanning and fine-grained placement, our approach can improve 20.9% on critical path delay, 24% on reconfiguration delay, 12% on congestion, and 8.7% on wire length compared to current DPR design method.

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4

PEDRAM, MASSOUD, and ERNEST S. KUH. "BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING." International Journal of High Speed Electronics and Systems 03, no. 01 (March 1992): 137–70. http://dx.doi.org/10.1142/s0129156492000060.

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This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top-down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques for satisfying a wide range of constraints (physical, topological, timing) and is, therefore, able to generate floorplans for a number of different layout styles. A systematic and efficient optimization procedure during the selection of suitable floorplan patterns that integrates floorplanning, global routing and pin assignment, a new pin assignment technique based on linear assignment and driven by the global routing solution and floorplan topology, and an effective timing-driven floorplanning scheme are among the other novel features of the floorplanner. These techniques have been incorporated in BEAR-FP, a macrocell layout system developed at the University of California, Berkeley. Results on various placement and floorplanning benchmarks are quite good.

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5

Jiang, Zhongjie, Zhiqiang Li, and Zhenjie Yao. "Multi-Objective Optimization in 3D Floorplanning." Electronics 13, no. 9 (April 27, 2024): 1696. http://dx.doi.org/10.3390/electronics13091696.

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Three-dimensional integrated circuits can significantly mitigate the challenges posed by shrinking feature sizes and enable heterogeneous integration. This paper focuses on the 3D floorplanning problem. We formulate it as a multi-objective optimization issue and employ multi-objective simulated annealing to simultaneously optimize area, wirelength and number of vias. During the optimization process, neighboring solutions are explored in the design space through inter-layer or intra-layer perturbations, and decision criteria for the exploration process are formulated based on the dominance relationship of solutions. Test results on the GSRC benchmark demonstrate that our approach delivers superior performance in optimizing area and wirelength. Compared to 2D floorplanning, our method reduces the area by approximately 49% and the wirelength by 21%. Compared to other similar 3D floorplanning methods, we raise the success rate in satisfying the fixed-outline constraint to 100% and improve the wirelength by 3%. The multi-objective simulated annealing method proposed in this paper can effectively address the 3D floorplanning problem.

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6

Xiang, H., X. Tang, and M. D. F. Wong. "Bus-Driven Floorplanning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 11 (November 2004): 1522–30. http://dx.doi.org/10.1109/tcad.2004.836728.

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7

Ma, Qiang, Zaichen Qian, Evangeline F. Y. Young, and Hai Zhou. "MSV-Driven Floorplanning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 8 (August 2011): 1152–62. http://dx.doi.org/10.1109/tcad.2011.2131890.

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8

WANG, LIN. "FAST ALGORITHMS FOR THERMAL-AWARE FLOORPLANNING." Journal of Circuits, Systems and Computers 23, no. 07 (June 2, 2014): 1450098. http://dx.doi.org/10.1142/s0218126614500984.

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Thermal-aware floorplanning is an effective way to solve the thermal problem in modern integrated circuit (IC) designs. Existing thermal-aware floorplanning methods are all based on simulated annealing (SA), genetic algorithms (GAs) or linear programming (LP), which are quite time-consuming. In this paper, we propose two fast algorithms for thermal-aware floorplanning, a greedy algorithm based on the less-flexibility-first (LFF) principle and a hybrid algorithm combining the greedy algorithm and an SA-based refinement. The greedy algorithm can fast obtain a locally optimized floorplan with reduced area and temperature. The hybrid method can get similar results compared with pure SA-based approaches but it is still much faster.

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9

Laudis, Lalin L., and Amit Kumar Sinha. "Metaheuristic Approach for VLSI 3D-Floorplanning." International Journal of Scientific Research 2, no. 12 (June 1, 2012): 202–3. http://dx.doi.org/10.15373/22778179/dec2013/62.

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10

Balasubramanian, Srinath, Arunapriya Panchanathan, Bharatiraja Chokkalingam, Sanjeevikumar Padmanaban, and Zbigniew Leonowicz. "Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints." Electronics 7, no. 11 (November 15, 2018): 325. http://dx.doi.org/10.3390/electronics7110325.

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Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

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11

Yoshikawa, Masaya, and Hidekazu Terai. "Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation." Journal of Advanced Computational Intelligence and Intelligent Informatics 10, no. 1 (January 20, 2006): 112–20. http://dx.doi.org/10.20965/jaciii.2006.p0112.

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The floorplanning problem, a basic design step in layout design of very large-scale integrated circuit (VLSI), deals with placing rectangular modules at maximum density. Many studies have dealt with conducted this problem using sequence pairs based on genetic algorithms (GAs), but this generally requires much calculation time. We propose an architecture for high-speed floorplanning using a sequence pair based on GA. The proposed architecture, implemented on the field-programmable gate array (FPGA), achieves high-speed processing. Measurement evaluating the proposed architecture demonstrated speeds 37.1 times greater than software processing.

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12

LIN, CHANG-TZU, DE-SHENG CHEN, and YI-WEN WANG. "MODERN FLOORPLANNING WITH BOUNDARY AND FIXED-OUTLINE CONSTRAINTS VIA GENETIC CLUSTERING ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 01 (February 2006): 107–27. http://dx.doi.org/10.1142/s0218126606002940.

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Typical floorplanning problem concerns a series of objectives, such as area, wirelength and routability, etc., without any specific constraint in a free-outline style. Entering SOC era; however, modern floorplanning takes more care of providing extra options, such as boundary constraint for I/O connections and fixed-outline constraint for hierarchical designs. It has been empirically shown that one of the modern constraints extremely restricts the solution space; that is, a large number of randomly generated floorplans might be infeasible. This paper tackles modern floorplanning with both boundary and fixed-outline constraints. A novel genetic clustering algorithm was proposed to guarantee to produce slicing floorplans with satisfying boundary constraint. By analyzing the properties of the slicing floorplan, the algorithm is effective to cluster the boundary-constrained modules into four constrained sub-floorplans. Afterward, the four sub-floorplans were combined to satisfy the boundary constraint. We then extend the algorithm with minor modification to enable the slicing floorplans with boundary constraint to be gradually fit into the desirable fixed outline. The methods were verified by using the MCNC and GSRC benchmarks, and the empirical results show that our methods can obtain promising solutions using short time.

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13

Pei-Ning Guo, T. Takahashi, Chung-Kuan Cheng, and T. Yoshimura. "Floorplanning using a tree representation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 2 (2001): 281–89. http://dx.doi.org/10.1109/43.908471.

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14

Nakatake, S., Y. Kubo, and Y. Kajitani. "Consistent floorplanning with hierarchical superconstraints." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, no. 1 (2002): 42–49. http://dx.doi.org/10.1109/43.974136.

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15

Feng, Y., D. P. Mehta, and H. Yang. "Constrained Floorplanning Using Network Flows." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 4 (April 2004): 572–80. http://dx.doi.org/10.1109/tcad.2004.825877.

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16

Xiaoping Tang, Ruiqi Tian, and M. D. F. Wong. "Minimizing wire length in floorplanning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 9 (September 2006): 1744–53. http://dx.doi.org/10.1109/tcad.2005.858266.

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17

Banerjee, P., M. Sangtani, and S. Sur-Kolay. "Floorplanning for Partially Reconfigurable FPGAs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 1 (January 2011): 8–17. http://dx.doi.org/10.1109/tcad.2010.2079390.

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18

Law, Jill H. Y., and Evangeline F. Y. Young. "Multi-bend bus driven floorplanning." Integration 41, no. 2 (February 2008): 306–16. http://dx.doi.org/10.1016/j.vlsi.2007.09.002.

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19

Yeap, Gary K. H., and Majid Sarrafzadeh. "Sliceable Floorplanning by Graph Dualization." SIAM Journal on Discrete Mathematics 8, no. 2 (May 1995): 258–80. http://dx.doi.org/10.1137/s0895480191266700.

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20

FANG, J. P. "An Enhanced BSA for Floorplanning." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 2 (February 1, 2006): 528–34. http://dx.doi.org/10.1093/ietfec/e89-a.2.528.

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21

SUN, YACHYANG, and KOK-HOO YEAP. "EDGE COVERING OF COMPLEX TRIANGLES IN RECTANGULAR DUAL FLOORPLANNING." Journal of Circuits, Systems and Computers 03, no. 03 (September 1993): 721–31. http://dx.doi.org/10.1142/s0218126693000435.

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Rectangular dual graph approach to floorplanning is based on the adjacency graph of the modules in a floorplan. If the input adjacency graph contains a cycle of length three which is not a face (complex triangle), a rectangular floorplan does not exist. Thus, complex triangles have to be eliminated before applying any floorplanning algorithm. This paper shows that the weighted complex triangle elimination problem is NP-complete, even when the input graphs are restricted to 1-level containment. For adjacency graph with 0-level containment, the unweighted problem is optimally solvable in O(c1.5 + n) time where c is the number of complex triangles and n is the number of vertices of the input graph.

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22

Yang, Hai Yan, and Hua An Zhao. "A Floorplanning Algorithm with Minimum Total Length Wires." Advanced Materials Research 705 (June 2013): 630–35. http://dx.doi.org/10.4028/www.scientific.net/amr.705.630.

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A floorplan is employed to represent the placement of modules in VLSI design. Floorplanning is a key step in the design of VLSI systems because it provides the first estimates of performance and cost including placement and routing. In this paper, we show an algorithm1 for initial global routing by the single-sequence (SS). The aim of our algorithm is to get a minimum chip area and the shortest total length of wires where the longest (critical) wire in every net is reduced to a minimum. The experimental results show that the design of placement and routing in floorplanning can be considered simultaneously by our algorithm, the efficiency of automatic layout in VLSI can be raised.

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23

B, Srinath, P. Aruna priya, and Chirag Kasliwal. "Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 496. http://dx.doi.org/10.14419/ijet.v7i2.24.12145.

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In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.

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24

Kim, Jae-Hwan, and Jong-Wha Chong. "Voltage Island Partitioning Based Floorplanning Algorithm." Journal of IKEEE 16, no. 3 (September 30, 2012): 197–202. http://dx.doi.org/10.7471/ikeee.2012.16.3.197.

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25

Xu, Ning, Zhoughua Jiang, and Feng Huang. "Performance and Low Power Driven Floorplanning." Journal of Algorithms & Computational Technology 1, no. 2 (June 2007): 161–69. http://dx.doi.org/10.1260/174830107781389058.

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26

Varatharajan, R., Muthu Senthil, and Perumal sankar. "Memetic Programming Approach for Floorplanning Applications." International Journal of Information Engineering and Electronic Business 4, no. 4 (August 10, 2012): 39–45. http://dx.doi.org/10.5815/ijieeb.2012.04.06.

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27

Adya, S. N., and I. L. Markov. "Fixed-outline floorplanning: enabling hierarchical design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 6 (December 2003): 1120–35. http://dx.doi.org/10.1109/tvlsi.2003.817546.

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28

Casu, M. R., and L. Macchiaru. "Throughput-driven floorplanning with wire pipelining." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 5 (May 2005): 663–75. http://dx.doi.org/10.1109/tcad.2005.846371.

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29

Dai, W. W. M. "Hierarchical placement and floorplanning in BEAR." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, no. 12 (1989): 1335–49. http://dx.doi.org/10.1109/43.44514.

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30

Tang, Maolin, and Xin Yao. "A Memetic Algorithm for VLSI Floorplanning." IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics) 37, no. 1 (February 2007): 62–69. http://dx.doi.org/10.1109/tsmcb.2006.883268.

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31

Chen, Ying-Chieh, and Yiming Li. "Temperature-aware floorplanning via geometric programming." Mathematical and Computer Modelling 51, no. 7-8 (April 2010): 927–34. http://dx.doi.org/10.1016/j.mcm.2009.08.026.

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32

Tabbara, Abdallah, Bassam Tabbara, Robert K. Brayton, and A. Richard Newton. "Integration of retiming with architectural floorplanning." Integration 29, no. 1 (March 2000): 25–43. http://dx.doi.org/10.1016/s0167-9260(99)00021-8.

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33

Wu, Po-Hsun, and Tsung-Yi Ho. "Bus-driven floorplanning with thermal consideration." Integration 46, no. 4 (September 2013): 369–81. http://dx.doi.org/10.1016/j.vlsi.2012.11.002.

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34

Anjos, Miguel F., and Anthony Vannelli. "An Attractor-Repeller approach to floorplanning." Mathematical Methods of Operations Research (ZOR) 56, no. 1 (August 1, 2002): 3–27. http://dx.doi.org/10.1007/s001860200197.

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35

Qi, X., Z. Feng, and X. Yan. "Timing driven floorplanning for general cells." Electronics Letters 30, no. 14 (July 7, 1994): 1112–13. http://dx.doi.org/10.1049/el:19940769.

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36

Liao, Swanwa, Mario A. Lopez, and Dinesh Mehta. "Constrained polygon transformations for incremental floorplanning." ACM Transactions on Design Automation of Electronic Systems 6, no. 3 (July 2001): 322–42. http://dx.doi.org/10.1145/383251.383255.

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37

Changbo Long, L. J. Simonson, Weiping Liao, and Lei He. "Microarchitecture Configurations and Floorplanning Co-Optimization." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 7 (July 2007): 830–41. http://dx.doi.org/10.1109/tvlsi.2007.899240.

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38

Han, Yongkui, and Israel Koren. "Simulated Annealing Based Temperature Aware Floorplanning." Journal of Low Power Electronics 3, no. 2 (August 1, 2007): 141–55. http://dx.doi.org/10.1166/jolpe.2007.128.

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39

Singhal, L., and E. Bozorgzadeh. "Multi-layer floorplanning for reconfigurable designs." IET Computers & Digital Techniques 1, no. 4 (2007): 276. http://dx.doi.org/10.1049/iet-cdt:20070012.

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40

Jabri, Marwan A. "Building Rectangular Floorplans–A Graph Theoretical Approach." VLSI Design 1, no. 2 (January 1, 1994): 99–111. http://dx.doi.org/10.1155/1994/46871.

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Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down floorplanning of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph that is a path.

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41

Srinath, B., Rajesh Verma, Abdulwasa Bakr Barnawi, Ramkumar Raja, Mohammed Abdul Muqeet, Neeraj Kumar Shukla, A. Ananthi Christy, C. Bharatiraja, and Josiah Lange Munda. "An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts." Electronics 10, no. 22 (November 15, 2021): 2795. http://dx.doi.org/10.3390/electronics10222795.

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Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

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42

MA, YUCHUN, QIANG ZHOU, PINGQIANG ZHOU, and XIANLONG HONG. "THERMAL IMPACTS OF LEAKAGE POWER IN 2D/3D FLOORPLANNING." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1483–95. http://dx.doi.org/10.1142/s0218126610006773.

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Leakage power is becoming a key design challenge in current and future CMOS designs. Due to technology scaling, the leakage power is rising so quickly that it largely elevates the die temperature. In this paper, we deeply investigate the impact of leakage power on thermal profile in both 2D and 3D floorplanning. Our results show that chip temperature can increase by about 11°C in 2D design and 68°C for 3D case with leakage power considered. Then we propose a thermal-driven floorplanning flow integrated with an iterative leakage-aware thermal analysis process to optimize chip temperature and save leakage power consumption. Experimental results show that for 2D design, the max chip temperature can be reduced by about 8°C and the proportion of leakage power to total power can be reduced from 19.17% to 11.12%. The corresponding results for 3D are 60°C temperature reduction and 16.3% less leakage power proportion.

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43

YU, Bei, Sheqin DONG, Song CHEN, and Satoshi GOTO. "Voltage and Level-Shifter Assignment Driven Floorplanning." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 12 (2009): 2990–97. http://dx.doi.org/10.1587/transfun.e92.a.2990.

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44

Li Yiming, Li Yi, and Zhou Mingtian. "Area Optimization in Floorplanning Using AP-TCG." Journal of Convergence Information Technology 5, no. 10 (December 31, 2010): 216–22. http://dx.doi.org/10.4156/jcit.vol5.issue10.28.

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45

LIU, Nan, Song CHEN, and Takeshi YOSHIMURA. "Floorplanning for High Utilization of Heterogeneous FPGAs." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95.A, no. 9 (2012): 1529–37. http://dx.doi.org/10.1587/transfun.e95.a.1529.

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46

Teng-Sheng Moh, Tsu-Shuan Chang, and S. L. Hakimi. "Globally optimal floorplanning for a layout problem." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 43, no. 9 (1996): 713–20. http://dx.doi.org/10.1109/81.536741.

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47

Montone, Alessio, Marco D. Santambrogio, Donatella Sciuto, and Seda Ogrenci Memik. "Placement and Floorplanning in Dynamically Reconfigurable FPGAs." ACM Transactions on Reconfigurable Technology and Systems 3, no. 4 (November 2010): 1–34. http://dx.doi.org/10.1145/1862648.1862654.

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48

Takahashi, T., P. N. Guo, C. K. Cheng, and T. Yoshimura. "Floorplanning using a tree representation a summary." IEEE Circuits and Systems Magazine 3, no. 2 (2003): 26–29. http://dx.doi.org/10.1109/mcas.2003.1242834.

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