Dissertations / Theses on the topic 'Flying Capacitor Multilevel Inverters'

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior
Diante da necessidade em aperfeiÃoar as tecnologias existentes para a conversÃo de energia elÃtrica em sistemas de alta potÃncia, este trabalho tem por finalidade projetar, analisar e implementar experimentalmente uma tÃcnica de modulaÃÃo com o intuito de reduzir o conteÃdo harmÃnico da tensÃo de saÃda em um inversor multinÃvel com capacitor flutuante de trÃs nÃveis. Algumas das diversas tÃcnicas de modulaÃÃo (PSPWM, LSPWM, HE-PWM e CSV-PWM) foram analisadas e implementadas no controlador digital FPGA a fim de comparar suas caracterÃsticas de desempenho com a tÃcnica de modulaÃÃo proposta. AlÃm disso, foi realizado o estudo de perdas da topologia de inversor multinÃvel com capacitor flutuante de trÃs nÃveis e a anÃlise teÃrica da distorÃÃo harmÃnica total da modulaÃÃo proposta. Finalmente, o desenvolvimento digital das tÃcnicas mostrou resultados coerentes, com formas de onda obtidas experimentalmente com alta qualidade de resoluÃÃo. A comparaÃÃo entre as estratÃgias de modulaÃÃo em termos de DHT resultou positivamente à modulaÃÃo proposta, cujos resultados experimentais de DHT nas tensÃes de linha na saÃda apresentaram o melhor desempenho para toda a faixa de Ãndices de modulaÃÃo comparadas Ãs tÃcnicas PSPWM, LSPWM-POD e CSV-PWM e uma reduÃÃo de atà 4,5% em relaÃÃo à HE-PWM. Isto comprova o estudo teÃrico realizado e sua aplicaÃÃo no inversor multinÃvel com capacitor flutuante de trÃs nÃveis.
Given the need to improve the existing technologies for electrical energy conversion into high power systems, this works purpose to design, analyze and implement a modulation technique that aims to reduce the output voltage harmonic content on the three-level flying capacitor multilevel inverter. Some of the various conventional modulation techniques (PSPWM, LSPWM, HE-PWM e CSV-PWM) have been analyzed and implemented in FPGA controller in order to compare their performance features with the proposed modulation technique. Furthermore, the losses study of the three-level flying capacitor multilevel inverter topology and the total harmonic distortion theoretical analysis of the proposed modulation technique have been made. Finally, the digital implementation of the techniques showed consistent results with experimentally obtained waveforms with high quality resolution. The comparison between the modulation strategies in the THD rates resulted positively for the proposed modulation, which THD experimental results in the line output voltage showed the best performance for all range of modulation indexes compared to techniques PSPWM, LSPWM-POD and CSV-PWM and the reduction of up to 4.5% better than HE-PWM. This proved the theoretical study done and its application in three-level flying capacitor multilevel inverter.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005.
A switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.

Thesis (M.S.)--Missouri University of Science and Technology, 2010.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed July 26, 2010) Includes bibliographical references (p. 96-102).

Voltage and current unbalance are major problems in distribution networks, particularly with the integration of distributed generation systems. One way of mitigating these issues is by injecting negative sequence current into the distribution network using a Static Synchronous Compensator (STATCOM) which normally also regulates the voltage and power factor. The benefits of modularity and scalability offered by Modular Multilevel Cascaded Converters (MMCC) make them suitable for STATCOM application. A number of different types of MMCC may be used, classified according to the sub-module circuit topology used. Their performance features and operational ranges for unbalanced load compensation are evaluated and quantified in this research. This thesis investigates the use of both single star and single delta configured five-level Flying Capacitor (FC) converter MMCC based STATCOMs for unbalanced load compensation. A detailed study is carried out to compare this type of sub-module with several other types namely: half bridge, 3-L H-bridge and 3-L FC half bridge, and reveals the one best suited to STATCOM operation. With the choice of 5-L FC H-bridge as the sub-module for STATCOM operation, a detailed investigation is also performed to decide which pulse width modulation technique is the best. This was based on the assessment of total harmonic distortion, power loss, sub-module switch utilization and natural balancing of inner flying capacitors. Two new modulation techniques of swapped-carrier PWM (SC-PWM) along with phase disposed and phase shifted PWM (PS-PWM) are analyzed under these four performance metrics. A novel contribution of this research is the development of a new space vector modulation technique using an overlapping hexagon technique. This space vector strategy offers benefits of eliminating control complexity and improving waveform quality, unlike the case of multilevel space vector technique. The simulation and experimental results show that this method provides superior performance and is applicable for other MMCC sub-modules. Another contribution is the analysis and quantification of operating ranges of both single star and delta MMCCs in rating the cluster dc-link voltage (star) and current (delta) for unbalanced load compensation. A novel method of extending the operating capabilities of both configurations uses a third harmonic injection method. An experimental investigation validates the operating range extension compared to the pure sinusoidal zero sequence voltage and current injection. Also, the superiority of the single delta configured MMCC for unbalanced loading compensation is validated.

Voltage fluctuation and power losses in the distribution line are problems in distribution networks. One method to mitigate these problems is by injecting reactive power into the network using a Static Synchronous Compensator (STATCOM). This can be used both for regulating the voltage and reducing the losses. A STATCOM is critically dependent on a grid synchronisation scheme that can accurately track the changes occurring in the grid phase and frequency. The Modular Multilevel Converter (MMC) is a promising topology for STATCOM applications because of its simple modular circuit structure that allows for higher voltage ratings, and conventionally uses a stack of sub-modules which are either two-level half or H-bridge converters. As a novel alternative, the thesis investigates the practicality of a STATCOM based on a three-level flying capacitor (FC) converter. Two variants of this topology are presented; the FC Half-bridge and FC H-bridge. A comprehensive study is undertaken to compare these with the Half and H-bridge sub-module under STATCOM operation. Most importantly, an FC H-bridge-based STATCOM is investigated for reactive power compensation. The challenges of multilevel, multi-module PWM control schemes achieving good waveforms at low switching frequency, whilst maintaining module capacitor voltage balance, are thoroughly addressed. Simulation results validate the operation for both line voltage regulation and power factor correction. An experimental power system with an FC-based STATCOM rig is designed and built, and validates the simulation results for power factor correction. It demonstrates correct operation of a control scheme that includes a system for maintaining capacitor voltage balance. Another new contribution is the investigation of a phase locking technique based on the Energy Operator (EO). The method, combining two different EO computations, is shown to achieve fast and accurate detection of frequency and phase angle when combined with an appropriate filter, and crucially operates well under unbalanced voltage conditions. The technique is compared with two other well-known phase locked loop (PLL) schemes, showing that it outperforms the others in terms of speed and accuracy. A hardware implementation of the EO-PLL validates the principle, showing the simplicity of the method.

Die vorliegende Arbeit befasst sich mit einem detaillierten Vergleich von Mehrpunkt-Schaltungstopologien mit zentralem Gleichspannungszwischenkreis für den Einsatz in Mittelspannungsanwendungen. Im Rahmen dieser Untersuchungen wird die 3-Level Neutral Point Clamped Spannungswechselrichter Schaltungstopologie (3L-NPC VSC) sowohl mit Multilevel Flying Capacitor (FLC) als auch mit Multilevel Stacked Multicell (SMC) Schaltungstopologien verglichen, wobei unter Verwendung von aktuell verfügbaren IGBT-Modulen Stromrichterausgangsspannungen von 2.3 kV, 4.16 kV und 6.6 kV betrachtet werden. Neben der grundlegenden Funktionsweise wird die Auslegung der aktiven Leistungshalbleiter und der passiven Energiespeicher (Zwischenkreiskondensatoren, Flying Capacitors) für die untersuchten Stromrichtertopologien dargestellt. Unter Berücksichtigung verschiedener Modulationsverfahren und Schaltfrequenzen werden Kennwerte für den Oberschwingungsgehalt in der Ausgangsspannung und dem Ausgangsstrom vergleichend evaluiert. Die installierte Schalterleistungen, die Halbleiterausnutzungsfaktoren, die Stromrichterverlustleistungen sowie die Verlustleistungsverteilungen werden für die betrachteten Stromrichtertopologien detailliert gegenübergestellt und bewertet
The thesis deals with a detailed comparison of voltage source converter topologies with a central dc-link energy storage device for medium voltage applications. The Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is compared with multilevel Flying Capacitor (FLC) and Stacked Multicell (SMC) Voltage Source Converters (VSC) for output voltages of 2.3 kV, 4.16 kV and 6.6 kV by using state-of-the-art 6.5 kV, 3.3 kV, 4.5 kV and 1.7kV IGBTs. The fundamental functionality of the investigated converter topologies as well as the design of the power semiconductors and of the energy storage devices (Flying Capacitors and Dc-Link capacitors) is described. The installed switch power, converter losses, the semiconductor loss distribution, modulation strategies and the harmonic spectra are compared in detail

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2011.
ENGLISH ABSTRACT: This thesis investigates the viability of constructing a solid-state transformer (SST) with a series-input, parallel-output connection of full-bridge, three-level ying-capacitor converters. It focusses on the active recti er front-end of the SST which is used to control the input current to be sinusoidal and in-phase with the sinusoidal input voltage. A stack of two converters are built and tested. The input current, as well as the ying capacitor voltages of the two active recti ers in the stack, are actively controlled by a nite-state model-based predictive (FS-MPC) controller. The use of multiple ying-capacitor converters poses a problem when using FS-MPC because of the large number of possible switching states to include in the prediction equations. Three FS-MPC control algorithms are proposed to attempt to overcome the problem associated with the large number of switching states. They are implemented on an FPGA digital controller. The algorithms are compared on the bases of voltage and current errors, as well as their responses to disturbances that are introduced into the system. The simulation and experimental results that are presented shows that by interleaving the control actions for the two converters, one can obtain fast and robust responses of the controlled variables. The viability of extending the interleaving control algorithm beyond two converters is also motivated.
AFRIKAANSE OPSOMMING: Hierdie tesis ondersoek die moontlikheid van volbrug, drievlak vlieënde-kapasitoromsetters wat gebruik word om 'n serie-intree, parallel-uittree drywingselektroniese transformator (DET) te bou. Dit fokus op die aktiewe gelykrigter van die DET wat gebruik word om die intreestroom te beheer om sinusvormig en in fase met die sinusvormige intreespanning te wees. 'n Stapel van twee omsetters word gebou en getoets. Die intreestroom, sowel as die vlieënde kapasitorspannings van die twee aktiewe gelykrigters in die stapel, word aktief beheer met behulp van 'n eindige-toestand, model-gebaseerde voorspellende beheerder (ET-MVB). Die gebruik van veelvuldige vlieënde-kapasitoromsetters bemoeilik die implementering van 'n ET-MVB-beheerder as gevolg van die groot aantal skakeltoestande wat in die voorspellende vergelykings in ag geneem moet word. Drie ET-MVB-algoritmes word voorgestel om te poog om die probleme, wat met die groot aantal skakeltoestande geassosieer word, te oorkom. Die algoritmes word in 'n FPGA digitale verwerker geïmplementeer. Die algoritmes word vergelyk op grond van hul stroom- en spanningsfoute, asook hul reaksie op steurings wat op die stelsel ingevoer word. Die simulasie en praktiese resultate toon dat, deur die beheeraksies vir die twee omsetters te laat oorvleuel, die gedrag van die beheerde veranderlikes vinniger en meer robuust is. Die moontlikheid om die oorvleuelende beheeraksies uit te brei tot meer as twee omsetters word ook gemotiveer.

This dissertation presents voltage stabilization techniques for flying capacitors used in soft-switching multilevel active power filters. The proposed active filter has proved to be a solution for power system harmonics produced by static high power converters. However, voltage unbalance of the clamping capacitors in the active filter in practical applications was observed due to its unequal parameters. Thus, the fundamentals of flying capacitors were characterized dealing with voltage balancing between flying capacitors and dc capacitors under practical operation, rather than ideal conditions. The study of voltage balancing provides the fundamental high-level solutions to flying capacitor based multilevel converter and inverter applications without additional passive balancing circuits. The use of proposed voltage balancing techniques made it possible to have a simple structure for solving the problems associated with the conventional bulky passive resistors and capacitor banks. Furthermore, the proposed control algorithms can be implemented with a real time digital signal processor. It can achieve the high performance of the active filter by compensating an adaptive gain to the controller. The effectiveness of the proposed controller was confirmed through various simulations and experiments. The focus of this study is to identify and develop voltage stabilization techniques for flying capacitors used in a proposed active filter. The voltage unbalance is investigated and characterized to provide safe operations. After having defined the problems associated with the voltage unbalance, the most important voltage stabilization techniques are proposed to solve this problem, in conjunction with an instantaneous reactive power (IRP) control of an active filter. In order to reduce the switching losses and improve the efficiency of the active filter, the proposed soft-switching techniques were evaluated through simulation and experimentation. Experimental results indicate that the proposed active filter achieved zero-voltage conditions in all of the main switches and zero-current turn-off conditions to the auxiliary switches during commutation processes. Also, various studies on soft-switching techniques, multilevel inverters, control issues and dynamics of the proposed active filter are discussed and analyzed in depth.
Ph. D.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior
Visando superar os desafios inerentes à conversÃo de energia elÃtrica em sistemas de alta potÃncia, minimizando as perdas e melhorando a qualidade da energia processada, este tra-balho tem por objetivo analisar e implementar uma tÃcnica de modulaÃÃo para ser aplicada nas duas topologias de inversores multinÃveis mais disseminadas - com neutro grampeado (NPC), e com capacitor flutuante (FC) - a fim de reduzir os esforÃos nos semicondutores, bem como melhorar o Ãndice de distorÃÃo harmÃnica da tensÃo de saÃda. Ao longo do trabalho foi evidenciada a necessidade da digitalizaÃÃo da tÃcnica proposta, visto que o desenvolvimento analÃgico da mesma acarretaria em um circuito complexo e de baixa confiabilidade. Dessa forma, escolheu-se como plataforma digital um FPGA, devido à sua facilidade de programa-ÃÃo e reconfiguraÃÃo, alÃm da alta velocidade e quantidade de pinos de entrada e saÃda. AlÃm da tÃcnica proposta, foram tambÃm desenvolvidas outras modulaÃÃes para fins de compara-ÃÃo, apresentando os padrÃes de chaveamento para cada uma delas, bem como o comporta-mento da corrente atravÃs dos semicondutores em cada perÃodo de chaveamento. Foi tambÃm realizada a anÃlise teÃrica das topologias e suas respectivas etapas de operaÃÃo, caracterÃsticas e levantamento das equaÃÃes que ditam a anÃlise das perdas para as diferentes situaÃÃes de tÃcnicas aplicadas a cada uma das estruturas. O desenvolvimento digital das tÃcnicas mostrou-se correta atravÃs da anÃlise das formas-de-onda colhidas por meio de um circuito digital-analÃgico. AlÃm disso, a comparaÃÃo da aplicaÃÃo dessas modulaÃÃes em inversores a trÃs nÃveis NPC e FC de 6 kW mostrou-se favorÃvel à tÃcnica proposta em termos de eficiÃncia e reduÃÃo da distorÃÃo harmÃnica em ambas as topologias, comprovando sua utilidade em con-versores multinÃveis de alta potÃncia. Por fim, foi apresentado o desenvolvimento da tÃcnica proposta em inversores com mais de trÃs nÃveis, onde se pode comprovar sua eficiente aplica-ÃÃo para tais fins, bem como sua expansibilidade para inversores de n nÃveis.
In order to overcome the challenge of processing electric energy in high power systems with minimal losses and high energy quality, this work presents the implementation and anal-ysis of a modulation technique applicable on both most well-known multilevel inverter struc-tures - neutral point-clamped (NPC), and flying capacitors (FC) - to reduce the stresses across the semiconductors devices, and to improve the total harmonic distortion of the output volt-age. Throughout the work, the necessity to digitalize the proposed technique has been evi-denced due to the high complexity and low reliability inherent to the analogical approach. Thus, the digital controller FPGA has been chosen, as it is easy to program and reconfigure, works at high speed, and has a lot of input and output pins. Additionally, other modulation techniques were also implemented to compare their performance with the proposed one, pre-senting the switching patterns and the behavior of the electrical currents through the semicon-ductors for each modulation. A theoretical analysis was also performed for both topologies and their respective operation principle, characteristics, and equations used on the losses anal-ysis for the different combinations of modulation applied to each structure. Finally, the digital development of the various techniques has proved to be correct by observing the waveforms obtained through the digital/analogical circuit. Besides, the comparison of the modulation techniques on 6 kW NPC and FC three-level prototype inverters proved to be favorable to the proposed technique in terms of efficiency and total harmonic distortion reduction on both topologies, confirming its usefulness on high power multilevel converters. At last, it was pre-sented the application of the proposed modulation technique to inverters with more than three levels, where it was observed its eligibility for n-levels topologies.

In recent years, multilevel converters are becoming more popular and attractive than traditional converters in high voltage and high power applications. Multilevel converters are particularly suitable for harmonic reduction in high power applications where semiconductor devices are not able to operate at high switching frequencies or in high voltage applications where multilevel converters reduce the need to connect devices in series to achieve high switch voltage ratings. This thesis investigated two aspects of multilevel converters: structure and control. The first part of this thesis focuses on inductance between a DC supply and inverter components in order to minimise loop inductance, which causes overvoltages and stored energy losses during switching. Three dimensional finite element simulations and experimental tests have been carried out for all sections to verify theoretical developments. The major contributions of this section of the thesis are as follows: The use of a large area thin conductor sheet with a rectangular cross section separated by dielectric sheets (planar busbar) instead of circular cross section wires, contributes to a reduction of the stray inductance. A number of approximate equations exist for calculating the inductance of a rectangular conductor but an assumption was made that the current density was uniform throughout the conductors. This assumption is not valid for an inverter with a point injection of current. A mathematical analysis of a planar bus bar has been performed at low and high frequencies and the inductance and the resistance values between the two points of the planar busbar have been determined. A new physical structure for a voltage source inverter with symmetrical planar bus bar structure called Reduced Layer Planar Bus bar, is proposed in this thesis based on the current point injection theory. This new type of planar busbar minimises the variation in stray inductance for different switching states. The reduced layer planar busbar is a new innovation in planar busbars for high power inverters with minimum separation between busbars, optimum stray inductance and improved thermal performances. This type of the planar busbar is suitable for high power inverters, where the voltage source is supported by several capacitors in parallel in order to provide a low ripple DC voltage during operation. A two layer planar busbar with different materials has been analysed theoretically in order to determine the resistance of bus bars during switching. Increasing the resistance of the planar busbar can gain a damping ratio between stray inductance and capacitance and affects the performance of current loop during switching. The aim of this section is to increase the resistance of the planar bus bar at high frequencies (during switching) and without significantly increasing the planar busbar resistance at low frequency (50 Hz) using the skin effect. This contribution shows a novel structure of busbar suitable for high power applications where high resistance is required at switching times. In multilevel converters there are different loop inductances between busbars and power switches associated with different switching states. The aim of this research is to consider all combinations of the switching states for each multilevel converter topology and identify the loop inductance for each switching state. Results show that the physical layout of the busbars is very important for minimisation of the loop inductance at each switch state. Novel symmetrical busbar structures are proposed for multilevel converters with diode-clamp and flying-capacitor topologies which minimise the worst case in stray inductance for different switching states. Overshoot voltages and thermal problems are considered for each topology to optimise the planar busbar structure. In the second part of the thesis, closed loop current techniques have been investigated for single and three phase multilevel converters. The aims of this section are to investigate and propose suitable current controllers such as hysteresis and predictive techniques for multilevel converters with low harmonic distortion and switching losses. This section of the thesis can be classified into three parts as follows: An optimum space vector modulation technique for a three-phase voltage source inverter based on a minimum-loss strategy is proposed. One of the degrees of freedom for optimisation of the space vector modulation is the selection of the zero vectors in the switching sequence. This new method improves switching transitions per cycle for a given level of distortion as the zero vector does not alternate between each sector. The harmonic spectrum and weighted total harmonic distortion for these strategies are compared and results show up to 7% weighted total harmonic distortion improvement over the previous minimum-loss strategy. The concept of SVM technique is a very convenient representation of a set of three-phase voltages or currents used for current control techniques. A new hysteresis current control technique for a single-phase multilevel converter with flying-capacitor topology is developed. This technique is based on magnitude and time errors to optimise the level change of converter output voltage. This method also considers how to improve unbalanced voltages of capacitors using voltage vectors in order to minimise switching losses. Logic controls require handling a large number of switches and a Programmable Logic Device (PLD) is a natural implementation for state transition description. The simulation and experimental results describe and verify the current control technique for the converter. A novel predictive current control technique is proposed for a three-phase multilevel converter, which controls the capacitors' voltage and load current with minimum current ripple and switching losses. The advantage of this contribution is that the technique can be applied to more voltage levels without significantly changing the control circuit. The three-phase five-level inverter with a pure inductive load has been implemented to track three-phase reference currents using analogue circuits and a programmable logic device.

Les principaux critères de comparaison des convertisseurs sont le rendement, la masse, le volume, le coût et la fiabilité. Le contexte environnemental et économique et le développement des applications nomades ouvrent à l’électronique de puissance un domaine d’application de plus en plus vaste. Mais pour imposer cette technologie, il faut sans cesse améliorer ces performances et les compromis entre celles qui sont antagonistes (augmentation du rendement et diminution de la masse par exemple…) ce qui amène naturellement à la problématique de conception et d’optimisation. Le cas spécifique de l’aéronautique n’échappe pas à la règle et les contraintes y semblent encore plus fortes. La réduction de la masse, du volume et l’augmentation du rendement et de la fiabilité sont parmi les défis principaux actuels, et la transition de systèmes hydrauliques ou pneumatique vers des systèmes électriques laisse espérer à une amélioration des performances globales de l’avion. Les architectures des convertisseurs sont un moyen efficace d’améliorer les convertisseurs parce qu’ils permettent de réduire les contraintes au sein des convertisseurs tout en améliorant les formes d’onde en entrée et/ou en sortie. Parallèlement, les composants classiques en silicium ont bénéficié de larges avancés au cours de ces dernières décennies et approchent de leurs limites théoriques. Pour espérer une amélioration, des technologies en rupture sont désormais nécessaires. Au cours de ces dernières années, les technologies de semi-conducteurs dit « à grand gap », essentiellement à base de Nitrure de Gallium ou de Carbure de Silicium (resp. GaN et SiC) se sont considérablement amélioré et sont d’ores et déjà plus performant que les composants Si dans de nombreux cas. Les semi-conducteurs étant généralement plus performants lorsqu’ils ont une tenue en tension plus faible, on envisage ici de cumuler plusieurs avantages en envisageant la mise en série de composants GaN basse-tension pour améliorer l’intégration des convertisseurs de puissance. Dans un premier temps, un convertisseur multi-niveaux élémentaire de type Flying Capacitor (FlyCap) est mis en oeuvre. Des condensateurs de puissance intégrés sont utilisés, ce qui pourrait permettre de réduire l’empreinte de ces composants et de proposer une dissipation thermique commune par le dessus des composants. L’utilisation de composant au temps de commutation réduit est critique pour la fiabilité des convertisseurs. Une étude de l’influence des paramètres physique du circuit électrique sur les inductances parasites de la maille de puissance et de commande est menée permettant de mettre en évidence des règles de conception dans le but d’améliorer la fiabilité des convertisseurs. Dans un second temps, l’équilibrage dynamique de la topologie FlyCap qui est critique pour les formes d’onde et la sureté de fonctionnement est étudié. La prise en compte des pertes dans les semi-conducteurs permet d’améliorer l’estimation de la dynamique d’équilibrage. Une base de réflexion sur le dimensionnement d’un équilibreur passif est également proposée pour optimiser sa dynamique et les pertes associées. Un prototype expérimental à 5 cellules de commutation est présenté permettant d’atteindre une tension d’entrée de 270 V avec des composants 100V.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

Indiana University-Purdue University Indianapolis (IUPUI)
This research proposes state-of-the-art multilevel converter topologies and their modulation strategies, the implementation of a conventional flying-capacitor converter topology up to four-level, and a new four-level flying-capacitor H-Bridge converter confi guration. The three phase version of this proposed four-level flying-capacitor H-Bridge converter is given as well in this study. The highlighted advantages of the proposed converter are as following: (1) the same blocking voltage for all switches employed in the con figuration, (2) no capacitor midpoint connection is needed, (3) reduced number of passive elements as compared to the conventional solution, (4) reduced total dc source value by comparison with the conventional topology. The proposed four-level capacitor-clamped H-Bridge converter can be utilized as a multilevel inverter application in an electri fied railway system, or in hybrid electric vehicles. In addition to the implementation of the proposed topology in this research, its experimental setup has been designed to validate the simulation results of the given converter topologies.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.

Induction motor drives (IMD) require a DC-AC inverter system to obtain variable frequency operation. Generally, IMD uses conventional 2-level inverters. The conventional 2-level inverter has its pole switching between zero and DC bus voltage. Thus, the switching in 2-level inverter results in high dv/dt in the inverter pole voltage. Also, the switches in the inverter need to block a full DC link voltage which increases the switching losses. These issues with drive scheme using 2-level inverter can be addressed by using multilevel inverters (MLI). Some of the frequently used MLI topologies include 3-level neutral point clamped (NPC), flying capacitor (FC) and cascaded H-bridges (CHB) inverters. But, by using FC inverter to generate more number of levels requires more number of floating capacitors while, using CHB inverter to generate more number of levels requires more number of isolated power supplies. The NPC inverters require more number of clamping diodes as number of level increases and also it suffers from neutral point voltage (NPV) deviations which results in using isolated DC sources or large value of stacked DC-link capacitance. Likewise, stacked MLI also uses stacking of DC-link capacitors to generate more number of levels and suffers from neutral point voltage deviation. In the first work, a method to control the NPV deviation is proposed for stacked MLI. The NPV is balanced instantaneously which enables the single DC-link operation of stacked MLI. The controlling of neutral point (NP) voltages are obtained by using low voltage capacitor fed cascaded H-bridge (CHB) per phase of symmetrical 6-phase induction machine (IM), which ensures zero current drawn from NP (at any given instant). The proposed method of controlling NPV is independent of loading, load power factor and modulation index. The method is validated using 7-level topology consists of 3 series connected DC-link capacitors with two neutral points fed from single DC source. The topology and PWM operation ensures that the NPV fluctuations in the 3 series connected charged capacitors are absent throughout the modulation index range. Further, the concept is extended to obtain common mode eliminated 7-level structure with NPV control. The generalization of this method for any stacked n-level inverter without NPV deviation is also proposed. The open loop V/f operation is performed on IM for various speeds and in transient state to support the above claims. In the second work, a new 7-level inverter topology is proposed. It is realised by cascading a 3-level T-Type inverter with 5-level active neutral point clamped inverter. The proposed topology uses low voltage semiconductor devices and floating capacitors which are balanced in every PWM switching cycle using pole voltage redundancies for every pole voltage levels. The balancing of capacitor voltages are independent of modulation index and load power factor. The topology forms two stacks at the front-end which uses individual symmetrical reduced DC sources. Further, the method proposed in the first part of the work is used to obtain the single DC-link operation with NPV control of two stacked capacitor. The topology is validated first using open loop V/f and then using the closed loop rotor field oriented control for IM. Further, the loss analysis shows that the topology has less switching as well as conduction loss as compared to some of the 7-level MLI reported in various literatures. In the third work, a 15-level (14 concentric) dodecagonal (12-sided) voltage space vector structure using stacked and cascaded MLI is proposed. It is generated by cascading 5-level capacitor fed CHB inverter (secondary inverter) with a 5-level stacked inverter (primary inverter). The active power is sourced only by the primary inverter and the secondary inverter acts as an active harmonic filter. The primary inverter works in a quasi-square mode throughout the modulation and high frequency switchings are shifted to low voltage CHBs, which reduces the switching losses. The proposed scheme has dense dodecagonal space vector structure which gives better harmonic performance as compared to other schemes generating dodecagonal space vector structures. The switching loss analysis is accomplished and shown that the scheme has less switching loss than conventional 2-level, 3-level and 5-level inverters. Due to 12-sided space vector structure the 6n+/-1 (‘n’ is odd) is highly suppressed which results in better performance and reduced low order filter requirements. The scheme is validated for open loop V/f control to obtain the steady and transient state performance.

碩士
國立交通大學
電控工程研究所
106
An asymmetrical (2N+1) level flying-capacitor converter is presented in this thesis to construct a bidirectional AC/DC converter. Compared with conventional double loop control structure, the proposed control structure only requires input voltages and output voltage to achieve power factor correction amd regulate the output voltage. If there is a generated system connected to the dc bus,and the generated power is greater than the dc load, the proposed control structure must return superfluous power to the grid.Otherwise,the flying-capacitor voltage balancing loop is including in the control structure,which can improve the speed of flying-capacitor voltage balancing. At the end,all the algorithms are implemented in a FPGA(Field Programmable Gate Array). The simulation and experimental results will show the well performances of the proposed current sensorless control structure. The simulation and experimental results could also show the well performancesof the ying-capacitor voltage balancing loop,which can improve flying-capacitor natural balancing performance.

碩士
國立交通大學
電控工程研究所
103
In this thesis, we construct a mathematical model and derive the transfer function for the multilevel flying capacitor converter circuit. To derive the (2+1)-level and (3+1)-level flying capacitor converter circuit as an example, we find that no matter what the order of the circuit, the transfer functions can be simplified as second order system through parameter design. Finally, according to the design specifications of the controller, we can implement the control of multilevel flying capacitor converter circuit. All the algorithms and controllers are implemented in Field Programmable Gate Array (FPGA). Experimental results show that this control architecture with the controller is able to maintain stability in the steady-state and transient load waveforms.

Dissertação de mestrado integrado em Engenharia Eletrónica e de Computadores
A exigência na qualidade da forma de onda sintetizada pelos inversores de eletrónica de potência é cada vez maior, estando esta qualidade associada a um melhor funcionamento e a um maior tempo de vida por parte das cargas e sistemas associados aos inversores. A melhoria na qualidade das formas de onda geradas pelos inversores tem sido conseguida maioritariamente através do aumento da frequência de comutação dos semicondutores. Esta estratégia provoca perdas de comutação mais elevadas, maior stress aplicado ao semicondutor e um aumento das interferências eletromagnéticas. Outro método que começa a ser utilizado para melhorar a qualidade das formas de onda dos inversores é o aumento do número de níveis na forma de onda gerada à saída. Este método utiliza inversores com topologias multinível, podendo aumentar a qualidade das formas de onda produzidas sem as desvantagens da utilização de uma frequência de comutação muito alta. Inicialmente o uso dos inversores multinível era limitado a aplicações de tensões muito elevadas, devido ao custo elevado dos semicondutores e ao baixo poder de processamento dos controladores digitais existentes. Com a evolução das tecnologias é cada vez mais viável a utilização deste tipo de topologias em aplicações de baixa tensão que necessitam de uma foram de onda com uma distorção mínima. Esta dissertação de mestrado visa o desenvolvimento de um inversor multinível monofásico para uma aplicação de baixa tensão, atribuindo maior foco à qualidade da forma de onda a sintetizar. Para tal, foi escolhida uma aplicação de Qualidade de Energia Elétrica (QEE) nomeadamente um Filtro Ativo de Potência Paralelo (FAPP). A efetividade da compensação por parte do FAPP depende muito da qualidade das correntes sintetizadas. Sendo assim, o principal objetivo é a sintetização de correntes de compensação com elevada qualidade e com baixo ripple. Para tal, foi utilizada uma topologia de cinco níveis, cuja diferença de tensão entre níveis é menor quando comparada com um inversor convencional de 2 níveis, reduzindo assim o ripple da corrente produzida sem necessidade de aumentar os filtros passivos de saída. No decorrer deste trabalho foi realizado um estudo bibliográfico sobre inversores multinível e filtros ativos de potência. Posteriormente, foram realizadas simulações computacionais para validar a topologia a implementar. Por último, foi desenvolvido um protótipo laboratorial e foram realizados testes práticos com diferentes cargas, para comprovar o funcionamento adequado do FAPP.
The quality requirements of the signals synthesized by power inverters are increasing, being this quality associated to a better performance and longer lifetime of the loads and systems related to the inverters. The improvement in the quality of the inverters signal has been achieved by increasing the switching frequency. This strategy leads to high losses, greater stress applied to semiconductor and an increase of electromagnetic interference. Another method that is beginning to be used to improve the quality of the signals produced by power inverters is the increase in the number of levels of the output signals. This method uses inverters with multilevel topologies, allowing increase the quality of the produced signals without the disadvantages of the very high switching frequency. Initially the use of multilevel inverters was limited to high power applications, due to the high cost of semiconductors and low processing power of digital controllers. With the evolution of technologies, the use of multilevel topologies turns out to be more reliable in low voltage applications requiring signals with very low distortion. This dissertation aims at the development of a single-phase multilevel inverter for low-voltage application, giving greater focus to the quality of the synthesized signals. So, a power quality application was chosen, more precisely a Shunt Active Power Filter (SAPF). The effectiveness of a SAPF depends on the quality of the synthesized high quality and low ripple. To accomplish with this requirements, a five-level topology was selected, whose voltage difference between levels is less when compared to a conventional two level inverter, thus reducing the ripple without increasing the output passive filters. Along the work, a bibliographical study on multilevel inverters and active power filters was done. Later, simulations were performed to validate the topology, in order to proceed to its implementation. Finally, a laboratorial prototype has been developed and practical tests were carried out with different loads, to demonstrate the SAPF proper operation.

Die vorliegende Arbeit befasst sich mit einem detaillierten Vergleich von Mehrpunkt-Schaltungstopologien mit zentralem Gleichspannungszwischenkreis für den Einsatz in Mittelspannungsanwendungen. Im Rahmen dieser Untersuchungen wird die 3-Level Neutral Point Clamped Spannungswechselrichter Schaltungstopologie (3L-NPC VSC) sowohl mit Multilevel Flying Capacitor (FLC) als auch mit Multilevel Stacked Multicell (SMC) Schaltungstopologien verglichen, wobei unter Verwendung von aktuell verfügbaren IGBT-Modulen Stromrichterausgangsspannungen von 2.3 kV, 4.16 kV und 6.6 kV betrachtet werden. Neben der grundlegenden Funktionsweise wird die Auslegung der aktiven Leistungshalbleiter und der passiven Energiespeicher (Zwischenkreiskondensatoren, Flying Capacitors) für die untersuchten Stromrichtertopologien dargestellt. Unter Berücksichtigung verschiedener Modulationsverfahren und Schaltfrequenzen werden Kennwerte für den Oberschwingungsgehalt in der Ausgangsspannung und dem Ausgangsstrom vergleichend evaluiert. Die installierte Schalterleistungen, die Halbleiterausnutzungsfaktoren, die Stromrichterverlustleistungen sowie die Verlustleistungsverteilungen werden für die betrachteten Stromrichtertopologien detailliert gegenübergestellt und bewertet.:Inhaltsverzeichnis Liste der Variablen i Liste der Abkürzungen v 1 Einleitung 1 2 Überblick von Mittelspannungsstromrichtertopologien und Leistungshalbleitern 3 2.1 Mittelspannungsumrichtertopologien 3 2.2 Leistungshalbleiter 8 3 Aufbau und Funktion von Mittelspannungsstromrichtertopologien 10 3.1 Neutral Point Clamped Stromrichter (NPC) 10 3.1.1 3-Level Neutral Point Clamped Stromrichter (3L-NPC) 10 3.1.2 Mehrstufige NPC-Umrichter 21 3.2 Flying Capacitor Stromrichter (FLC) 23 3.2.1 3-Level Flying Capacitor Stromrichter (3L-FLC) 23 3.2.2 4-Level Flying Capacitor-Stromrichter (4L-FLC) 33 3.2.3 Mehrstufige Flying Capacitor-Stromrichter (NL-FLC) 39 3.3 Stacked Multicell Stromrichter (SMC) 43 3.3.1 5L-Stacked Multicell Stromrichter (5L-SMC) 43 3.3.2 N-Level Stacked Multicell Umrichter (NL-SMC) 51 4 Modellierung und Auslegung der Stromrichter 59 4.1 Verlustmodell 59 4.1.1 Sperrschichttemperaturen 64 4.2 Auslegung der Leistungshalbleiter 65 4.2.1 Stromauslegung 67 4.2.2 Worst-Case Arbeitspunkte 69 4.3 Auslegung der Zwischenkreiskondensatoren 75 4.3.1 Spannungszwischenkreis 76 4.3.2 Lastseitige Strombelastung und resultierende Spannungswelligkeit im Spannungszwischenkreis 77 4.3.3 Abhängigkeit der Strombelastung und der Spannungswelligkeit im Spannungszwischenkreis vom Frequenzverhältnis mf 95 4.3.4 Netzseitige Zwischenkreiseinspeisung 97 4.3.4.1 Zwischenkreiseinspeisung mit idealisiertem Transformatormodell 98 4.3.4.2 Zwischenkreiseinspeisung mit erweitertem Transformatormodell 101 4.3.5 Simulation des Gesamtsystems 104 4.4 Auslegung der Flying Capacitors 107 4.4.1 Strombelastung der Flying Capacitors 109 4.4.2 Spannungswelligkeit über den Flying Capacitors 113 4.4.3 Abhängigkeit der Spannungswelligkeit der Flying Capacitors vom Frequenzverhältnis mf 124 4.4.4 Auswirkung der Spannungswelligkeit der Flying Capacitors auf die Ausgangsspannungen 126 5 Vergleich der Stromrichtertopologien 129 5.1 Daten für den Stromrichtervergleich 129 5.2 Basis des Vergleiches 132 5.3 Vergleich für einen 2,3 kV Mittelspannungsstromrichter 134 5.3.1 Vergleich bei verschiedenen Schaltfrequenzen 134 5.3.2 Vergleich bei maximaler Trägerfrequenz 142 5.4 Vergleich für einen 4,16 kV Mittelspannungsstromrichter 146 5.4.1 Vergleich bei verschiedenen Schaltfrequenzen 146 5.4.2 Vergleich bei maximaler Trägerfrequenz 153 5.5 Vergleich für einen 6,6 kV Mittelspannungsstromrichter 156 5.5.1 Vergleich bei verschiedenen Schaltfrequenzen 156 5.5.2 Vergleich bei maximaler Trägerfrequenz 162 5.6 Vergleich von 2,3 kV, 4,16 kV und 6,6 kV Mittelspannungsstromrichtern 165 5.6.1 Vergleich bei identischer installierter Schalterleistung SS 165 5.6.2 Vergleich bei einer identischen Ausgangsleistung 167 6 Zusammenfassung und Bewertung 171 Anhang 175 A. Halbleiterverlustmodell 175 Referenzen 177
The thesis deals with a detailed comparison of voltage source converter topologies with a central dc-link energy storage device for medium voltage applications. The Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is compared with multilevel Flying Capacitor (FLC) and Stacked Multicell (SMC) Voltage Source Converters (VSC) for output voltages of 2.3 kV, 4.16 kV and 6.6 kV by using state-of-the-art 6.5 kV, 3.3 kV, 4.5 kV and 1.7kV IGBTs. The fundamental functionality of the investigated converter topologies as well as the design of the power semiconductors and of the energy storage devices (Flying Capacitors and Dc-Link capacitors) is described. The installed switch power, converter losses, the semiconductor loss distribution, modulation strategies and the harmonic spectra are compared in detail.:Inhaltsverzeichnis Liste der Variablen i Liste der Abkürzungen v 1 Einleitung 1 2 Überblick von Mittelspannungsstromrichtertopologien und Leistungshalbleitern 3 2.1 Mittelspannungsumrichtertopologien 3 2.2 Leistungshalbleiter 8 3 Aufbau und Funktion von Mittelspannungsstromrichtertopologien 10 3.1 Neutral Point Clamped Stromrichter (NPC) 10 3.1.1 3-Level Neutral Point Clamped Stromrichter (3L-NPC) 10 3.1.2 Mehrstufige NPC-Umrichter 21 3.2 Flying Capacitor Stromrichter (FLC) 23 3.2.1 3-Level Flying Capacitor Stromrichter (3L-FLC) 23 3.2.2 4-Level Flying Capacitor-Stromrichter (4L-FLC) 33 3.2.3 Mehrstufige Flying Capacitor-Stromrichter (NL-FLC) 39 3.3 Stacked Multicell Stromrichter (SMC) 43 3.3.1 5L-Stacked Multicell Stromrichter (5L-SMC) 43 3.3.2 N-Level Stacked Multicell Umrichter (NL-SMC) 51 4 Modellierung und Auslegung der Stromrichter 59 4.1 Verlustmodell 59 4.1.1 Sperrschichttemperaturen 64 4.2 Auslegung der Leistungshalbleiter 65 4.2.1 Stromauslegung 67 4.2.2 Worst-Case Arbeitspunkte 69 4.3 Auslegung der Zwischenkreiskondensatoren 75 4.3.1 Spannungszwischenkreis 76 4.3.2 Lastseitige Strombelastung und resultierende Spannungswelligkeit im Spannungszwischenkreis 77 4.3.3 Abhängigkeit der Strombelastung und der Spannungswelligkeit im Spannungszwischenkreis vom Frequenzverhältnis mf 95 4.3.4 Netzseitige Zwischenkreiseinspeisung 97 4.3.4.1 Zwischenkreiseinspeisung mit idealisiertem Transformatormodell 98 4.3.4.2 Zwischenkreiseinspeisung mit erweitertem Transformatormodell 101 4.3.5 Simulation des Gesamtsystems 104 4.4 Auslegung der Flying Capacitors 107 4.4.1 Strombelastung der Flying Capacitors 109 4.4.2 Spannungswelligkeit über den Flying Capacitors 113 4.4.3 Abhängigkeit der Spannungswelligkeit der Flying Capacitors vom Frequenzverhältnis mf 124 4.4.4 Auswirkung der Spannungswelligkeit der Flying Capacitors auf die Ausgangsspannungen 126 5 Vergleich der Stromrichtertopologien 129 5.1 Daten für den Stromrichtervergleich 129 5.2 Basis des Vergleiches 132 5.3 Vergleich für einen 2,3 kV Mittelspannungsstromrichter 134 5.3.1 Vergleich bei verschiedenen Schaltfrequenzen 134 5.3.2 Vergleich bei maximaler Trägerfrequenz 142 5.4 Vergleich für einen 4,16 kV Mittelspannungsstromrichter 146 5.4.1 Vergleich bei verschiedenen Schaltfrequenzen 146 5.4.2 Vergleich bei maximaler Trägerfrequenz 153 5.5 Vergleich für einen 6,6 kV Mittelspannungsstromrichter 156 5.5.1 Vergleich bei verschiedenen Schaltfrequenzen 156 5.5.2 Vergleich bei maximaler Trägerfrequenz 162 5.6 Vergleich von 2,3 kV, 4,16 kV und 6,6 kV Mittelspannungsstromrichtern 165 5.6.1 Vergleich bei identischer installierter Schalterleistung SS 165 5.6.2 Vergleich bei einer identischen Ausgangsleistung 167 6 Zusammenfassung und Bewertung 171 Anhang 175 A. Halbleiterverlustmodell 175 Referenzen 177

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

Multilevel voltage source inverter transformed conversion of DC to AC for medium to high power application. With increasing electric power demand, the multilevel converter allows high power density converters for medium to high voltage high power applications. Motor drives, high voltage DC (HVDC) transmission, renewable energy systems, and electric traction are some applications that employ multilevel converters. Conventional two-level inverters need to switch between full DC link to ground potential and require voltage blocking equal to the supply voltage. In addition, 2-level inverters require harmonic filters for filtering harmonics in the output voltage. The filters are costly and bulky and dissipate power, decreasing the system's overall efficiency. Multilevel inverters overcome the disadvantages of conventional inverters by switching intermediate voltage levels between DC link voltage and zero voltage. The higher resolution in the inverter voltage levels reduces the output voltage error compared to the required sinusoidal waveform and improves the harmonic quality. The converter's switching frequency is reduced to minimise the switching losses, thereby increasing the system efficiency. The dv/dt of the multilevel converter is less, which reduces the switching stress on the device and brings down the conductive and radiative emissions. Multilevel inverters can also utilise time-tested low voltage semiconductor technologies to build the converters, improving the system's reliability and easy component availability. Basic and most popular multilevel topologies are cascaded H-bridge inverter, neutral point clamped inverter and flying capacitor inverter. Another class of hybrid multilevel inverters is obtained by cascading basic multilevel inverter cells, which can generate high-quality output voltage waveforms with greater voltage levels. Hybrid multilevel inverters for induction motor drives are also obtained by configuring the motor as an open-end and feeding on both sides of the induction motor. The conventional voltage source inverter generates a hexagonal space vector structure. The inverters are required to operate in the overmodulation region for maximum utilisation of the available DC-link. Operating in the overmodulation region generates lower-order harmonics in the phase voltage and causes several undesirable problems in the systems. The linear modulation range of the hexagonal space vector structure is 90.7\% of the peak fundamental voltage for the maximum modulation index. Induction motor drives using hexagonal space vector structure suffer from torque pulsations on the motor shaft, which could even lead to total system failure. The harmonics in the system affect the dynamic performance of closed-loop current control of the motor and generate significant power loss. Various techniques have been proposed in the literature to suppress the problems caused by harmonics. Increasing the switching frequency of the converter is one such method to reduce the effect of harmonics by having lowest harmonics only at switching frequency, which is easy to filter out. High switching frequency is not a practical solution for medium and high power applications due to the high magnitude of switching loss in the device, resulting in worse electromagnetic compatibility performance. Also, the increased switching frequency is only effective for operation within the linear modulation range. Another conventional method for harmonic suppression is using passive filters. But, for variable frequency operation like in induction motor drives, filtering out lower order harmonics requires bulky filters, which increases the system's size and cost and adds to the resistive loss. Moreover, the addition of the filter to the system affects the system's dynamic performance and reduces the fundamental voltage at the output. Selective harmonic elimination (SHE) is a special pulse width modulation (PWM) to suppress the harmonics by introducing fixed notches in the output. SHE operates with a low switching frequency but suffers from low DC-link utilisation due to the introduction of the notches. Also, the method becomes complex for the elimination of multiple harmonics and has poor dynamic performance. An elegant method to eliminate harmonics in the output voltage is to realise space vector structures with inherent harmonic elimination. Polygonal space vector structure with a higher number of sides than a hexagon, such as 12-sided polygon and 18-sided polygon, eliminates lower order harmonics. 12-sided polygon eliminates the lower order harmonics of the order 5th and 7th and has harmonics only from 11th and 13th. 18-sided polygon eliminates the harmonics up to the 13th order and only harmonics from the 17th and 19th order. The polygons with a higher number of sides are closer to a circle geometrically and have an increased linear modulation region than hexagon (6-sided) for a given DC-link voltage. Generating higher fundamental voltage inverter operations compare to hexagon for the same DC-link voltage leads to better DC-link utilisation. Schemes generating multilevel polygonal space vector structures have evolved to incorporate the advantages of multilevel converters. There are several challenges to generating multilevel polygonal structures, including the requirement of large capacitance, the complexity of PWM techniques etc. Power circuit topologies with a single DC source to generate polygonal space vector structures have evolved but suffer from the requirement of large capacitor size. This thesis proposes a capacitor size reduction methodology and a simple PWM strategy for multilevel polygonal space vector structure. Chapter 1 introduces various harmonic suppression schemes and topologies for generating multilevel inverter polygonal space vector structures. A multilevel 12-sided polygonal voltage space vector generation scheme for variable-speed drive applications with a single DC-link operation requires an enormous capacitance value for cascaded H-bridge (CHB) filters when operated at lower speeds. The multilevel 12-sided polygonal structure is obtained in existing schemes by cascading a flying capacitor inverter with a CHB. Chapter 2 proposes a new scheme to minimise the capacitance requirement for full-speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimise the selection of vector redundancies among the CHBs to minimise the floating capacitors' voltage ripple. The algorithm computes the optimal vector redundancies by considering the instantaneous capacitor voltages and the phase currents. Chapter 3 proposes a simple unified pulse width modulation (PWM) strategy for multilevel polygonal space vector structure (SVS) partitioned into symmetric triangles for the first time. The algorithm obtains the PWM timing durations for a 2-level polygonal voltage SVS in a sampling duration using only the sampled reference values of voltages. The PWM timings obtained for a 2-level structure are then mapped to multilevel SVS. The matrices used for this mapping remain the same irrespective of the sides of the polygon. The smallest triangle encompassing the reference voltage vector in the multilevel structure is identified using this algorithm along with the PWM timings for which the voltage vectors forming the vertices of this smallest triangle are applied. The algorithm involves only operations like addition, multiplication, and logical comparisons. A general implementation scheme for an N-level, p-sided polygon is presented in this paper. A novel 5-level 18-sided SVS is also proposed in this paper. The scheme incorporates the advantages of harmonic elimination due to an 18-sided polygon and the inherent advantages of a multilevel inverter. A multilevel variable speed induction motor drive scheme using an 18-sided polygon with a very dense voltage space vector structure (SVS) is proposed in chapter 4. The proposed SVS consists of 101 concentric layers of 18-sided polygons. The 18-sided polygonal SVS eliminates lower order harmonics 5th, 7th, 11th and 13th orders from the output voltage for the entire modulation range. The linear modulation range of the 18-sided polygon is extended to 99\% of the base speed compared to 90.7\% of the hexagonal SVS. It also has higher peak phase fundamental voltage at the output and better DC-link utilisation than conventional inverters. The SVS is generated by superposition of 5-level main hexagonal SVS of radius VDC and 5-level auxiliary hexagonal SVS of radius 0.379VDC. The dense voltage space vector structure facilitates the generation of reference by nearest vector switching in the 18-sided polygon, reducing the semiconductor devices' switching. The vector switched to realise the reference voltage in a sampling period is only one polygonal vector throughout the modulation range, drastically reducing switching loss and electromagnetic emissions. Simulation and experimental results of the proposed drive scheme are presented to prove the effectiveness of the drive scheme. The inverter is modelled and extensively simulated using a MATLAB-SIMULINK environment. An experimental setup using inverter modules is set up to test the inverter. The semiconductor switches used are SKM75GB12T4 and IRF260N. Gate drive circuits based on opto-isolated IC M5792L from Mitsubishi and capacitive isolated IC ISO5451 from Texas Instruments are used. TMS320F28335 DSP from Texas Instruments and XC2S200 FPGA from Xilinx were used as the controllers for realising the hardware prototype. A 3-phase open-end induction motor of ratings 15 kW, 415 V, and 4-pole is used for testing the proposed drive schemes.

Grid integration of photovoltaic (PV) energy sources has been mostly governed by conventional two-level voltage source inverters. These topologies have significant switching power losses, dV/dt stress and THD level at lower switching frequencies. The above issues can be solved by introducing more voltage levels through multilevel converters. Conventional multilevel converters have many issues like neutral point voltage drift in neutral point clamped (NPC) topology, floating capacitor charge balance in flying capacitor (FC) topology and large number of isolated DC sources in cascaded half bridge (CHB) topology when scaling them for higher number of voltage levels. Additionally, active power devices and its associated gate drivers, clamping diodes, flying capacitors and DC link capacitors also increase with levels. Hence, it is desirable to generate a multilevel voltage output with a single DC link and with the reduced components count. This thesis proposes a new way of generating multilevel voltage output using a single DC source and with the least components count. The thesis also proposes a new gate driver that can be operated at wide duty cycle ratios and wide band frequency. The thesis presents five major contributions as follows, 1. 16 switch five level inverter for isolated grid tied systems 2. 12 switch five level inverter for isolated grid tied systems 3. Inherent DC link capacitor balancing 4. Extension of five level inverter topologies to higher levels 5. A Wide duty cycle range wide band high frequency isolated gate driver for multilevel power converters First part of the research work, presents a novel five level inverter for high power isolated grid connection, which is powered by a single DC source. The proposed topology employs overall 16 active power devices, two DC link capacitors and a Scott-T transformer. Out of 16 power switches, 8 switches operate at high frequency and remaining 8 operate at the fundamental frequency. The DC link capacitors have an inherent voltage balancing which eliminates the requirement of charge balancing circuit or complex control algorithm. Additionally, necessity of expensive voltage sensors are also mitigated. The five level converter initially generate five level voltages in two phase system, and then they are transformed to three phases by using a Scott-T transformer. Operation of the proposed five level inverter (1 kW) is tested experimentally by connecting it to a three phase grid with unity power factor control. Second part follows the footsteps of the first topology. The second topology presents a grid connected five level inverter with only 12 power devices. This topology is also powered by a single DC source. Eight (8) out of 12 power devices are switched at fundamental frequency (variable) and the remaining devices are switched at high frequency. The proposed inverter is validated experimentally by connecting it to a three phase grid. The performance of capacitor voltage balancing under steady state and transient loading conditions is verified. Third part of the thesis discusses about the inherent charge balancing phenomenon of the DC link capacitors for the proposed inverter topologies. In both the topologies, the DC link capacitors have inherent voltage balancing capability. This feature eliminates the requirement of voltage sensors and complex control schemes which are generally employed in the conventional multilevel inverters. In fourth part of the research work, a wide band frequency and wide duty cycle operated isolated gate driver with only a single auxiliary power supply is proposed. The proposed gate driver is specifically advantageous for multilevel inverters as all the gate drivers can be powered by a single auxiliary power supply. The integrated gate driver has features like, wide duty cycle (0 - 100%) and wide band frequency (ranging from DC to 1 MHz) operation, short circuit/over current, and miller clamp protections. The performance of the gate driver is validated experimentally followed by a LTSPICE software simulations. Finally, a generalized multilevel inverter topology based on the proposed five level inverter topologies with only a single DC source is presented. Multilevel output is obtained by cascading H-bridge modules on either side of the five level converter after the unfolding stage. Connecting `n' number of H-bridge modules per phase to the five level converter leads to [8n+1] levels of the output voltage. Feasibility of the converter is validated by testing a nine level inverter configuration. The proposed concept uses least active power devices, DC link capacitor, flying capacitor, and diodes compared to the existing single DC link fed multilevel inverter topologies. All the above presented topologies and circuits are extensively tested in simulation and in the experimentation in laboratory for three phase grid connected unity power factor operation. A 1 kW, 50 Hz fundamental and 10 kHz switching inverters was developed for the experimental studies. The inverter is used for the grid integration of DC sources with 192 V, 1 kW power rating. The inverter prototype consists of power semiconductor switches of rating 1200 V and 75 A insulated gate bipolar transistor (IGBT) half bridge Semikron modules (SKM75GB12T4). The proposed gate drivers were used to drive the power IGBTs. The Scott-T transformer is realized using two single phase transformers with an appropriate winding turns ratio. The current control and PWM signal generation is carried in a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz. The grid voltage and currents were sensed by using LEM make voltage (LV-25P) and current (LA-55P) sensors. The sensed voltage and current data is fed to the analog to digital converter (ADC) which internally exists in the DSP. All the computations and frame transformations were also carried within the DSP. The dead time for the IGBT modules is generated as 1μs. The testing was done by connecting the proposed inverters to the grid. The inverter performance is validated at various loading conditions. The inherent capacitor balancing was also validated under steady state and transient loading conditions. The proposed inverter topologies exhibits advantages like, reduced components count, single DC link operation, inherent capacitor voltage balancing, fundamental switching devices and inherent isolation. Overall size of the proposed inverters is less compared to the conventional five level inverters for grid connected applications where isolation is mandatory. The inherent capacitor voltage balancing also eliminates the requirement of expensive voltage sensors, complex control circuits and algorithms. The fewer active components count results in simple control architecture and improves reliability of the inverters to a large extent. The experimental validation shows that the proposed inverter topologies can be considered as viable solutions for the high power isolated grid tied photovoltaic systems.