Relevant bibliographies by topics / Folded cascode

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Folded cascode'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 June 2025

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Journal articles on the topic "Folded cascode"

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Song, Ming Xin, Yue Li, and Meng Meng Xu. "Design of High Gain CMOS Folded Cascode Operational Amplifier." Applied Mechanics and Materials 389 (August 2013): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.389.573.

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A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.
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Assaad, Rida S., and Jose Silva-Martinez. "The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier." IEEE Journal of Solid-State Circuits 44, no. 9 (2009): 2535–42. http://dx.doi.org/10.1109/jssc.2009.2024819.

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Kundra, Swati. "Low Power Folded Cascode OTA." International Journal of VLSI Design & Communication Systems 3, no. 1 (2012): 127–36. http://dx.doi.org/10.5121/vlsic.2012.3111.

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Sarin, Mythry, A.Gayathri, Farheen Saieemah, N.Jeenath, M.Sowmya, and P.Sahith. "Design of Low Power Operational Transconductance Amplifier for Biomedical Applications." International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE) 3, no. 2 (2020): 15–21. https://doi.org/10.5281/zenodo.3975519.

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This paper presents the design of folded cascode operational transconductance amplifier (OTA). This design has been implemented in 0.18um CMOS Technology using Cadence. Spectre simulation shows that the OTA has flat gain of 47dB from 1Hz to 100 KHz frequency, indicating stability of OTA, noise ranges as 22.49769nV/ at 10Hz to 66.89128fV/ at 1MHz and average power as 0.770mW. In this paper, we will be studying the design concepts, analysis of operational transconductance amplifier which is used for recording the bio signals. This paper plays a key role in real time applications for equipment designing of ECG, EEG, EMG, ENG devices. It is also used in recording and also for treatment of Paralysis, Epilepsy, Neuro diseases etc.,
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Assaad, Rida, and Jose Silva-Martinez. "Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers." VLSI Design 2009 (July 28, 2009): 1–11. http://dx.doi.org/10.1155/2009/323595.

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Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.
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Rashtian, Mohammad. "Adaptive double recycling folded cascode amplifier." Analog Integrated Circuits and Signal Processing 110, no. 1 (2021): 165–74. http://dx.doi.org/10.1007/s10470-021-01971-3.

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Dan, Song, and Zhang Xiaolin. "Low-voltage CMOS Folded-cascode Mixer." Chinese Journal of Aeronautics 23, no. 2 (2010): 198–203. http://dx.doi.org/10.1016/s1000-9361(09)60205-3.

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Anvekar, Shreya, A. D. Anusha, Goutam Giriraddi, Bhargav Hegde, and Sujata Kotabagi. "Single Stage Folded-Cascode Operational Amplifier." International Journal of Microsystems and IoT 2, no. 4 (2024): 745–52. https://doi.org/10.5281/zenodo.11654752.

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This paper mainly concentrates on designing a single-stage folded cascode op-amp with UMC 180nm technology. The amplifier operates seamlessly within the confines of a 1.8V power supply, shows a DC gain of 55dB, a phase margin of 66.87 degrees, and the amplifier’s bandwidth is reported at 222kHz (-3dB) for a 1pF load. It works with ICMR range from 1.6V-0.8V. The proposed structure yields medium gain and wide output swing ranging from 300mV to 1.4V.
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Yosefi, Ghader. "The high recycling folded cascode (HRFC): A general enhancement of the recycling folded cascode operational amplifier." Microelectronics Journal 89 (July 2019): 70–90. http://dx.doi.org/10.1016/j.mejo.2019.04.016.

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Choi, Gyuri, Hyunwoo Heo, Donggeun You, et al. "A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier." Applied Sciences 11, no. 17 (2021): 7982. http://dx.doi.org/10.3390/app11177982.

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In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.
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Dissertations / Theses on the topic "Folded cascode"

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Marino, Allison Margaret. "A clamped folded cascode amplifier for analog-to-digital converter applications." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35406.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.<br>Includes bibliographical references (leaves 67-68).<br>by Allison Margaret Marino.<br>M.S.
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BHANGAONKAR, AVINASH SUDHAKAR. "OPTIMIZATION OF PERFORMANCE AND SIZING OF TWO STAGE AND FOLDED CASCODE OP AMPS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1029436410.

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Neto, Murillo Fraguas Franco. "Técnica para o projeto de um amplificador operacional folded cascode, classe AB, em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05092006-152855/.

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A tendência mundial em torno de sistemas SoC – System on Chip – baseados em processo CMOS – Complementary Metal Oxide Semiconductor – digital, apresenta cada vez mais desafios aos projetistas de circuitos integrados. Em especial se observa que enquanto os projetistas de circuitos digitais podem contar com bibliotecas cada vez mais completas de células digitais semi-prontas e ferramentas cada vez mais poderosas para o aprimoramento do projeto, os projetistas analógicos não contam com tais facilidades, sendo necessário realizar o projeto de novas células analógicas para cada especificação recebida. Este trabalho apresenta uma contribuição para a automatização do projeto de blocos analógicos e, para isso, foi escolhido um bloco essencial em muitos projetos analógicos: o amplificador operacional – ampOp. A idéia inicial por trás dessa escolha foi um conjunto de especificações fornecido pela empresa Freescale Semiconductors, para o projeto um préamplificador de áudio realizado no âmbito do Programa Nacional de Microeletrônica – PNM. A topologia escolhida para o amplificador operacional, retirada de [1], foi analisada e utilizada para projeto do amplificador para áudio. Além disso, um software de auxílio ao projeto para este amplificador foi escrito em linguagem C, e seu objetivo é auxiliar no reprojeto do ampOp para atender à especificações diversas. Para isso o software recebe como entradas as próprias especificações e um primeiro projeto do ampOp, realizado com equações simplificadas de projeto. O software então, em conjunto com um simulador elétrico, reprojeta o amplificador, retirando alguns parâmetros relevantes dos arquivos de simulação e utilizando equações de projeto mais completas. Ao final do trabalho, um exemplo de ampOp foi fabricado e caracterizado, sendo os resultados obtidos analisados.<br>The world trend towards SoC – System on Chip – based on digital CMOS – Complementary Metal Oxide Semiconductor – process presents more and more challenges to the IC designer. One can observe that while digital designers may rely on digital core libraries that are more and more complete, and design tools that are increasingly powerful and capable of optimizing the digital design, analog designers do not have such privileges available, becoming necessary to design such analog cores each time a new set of specifications is received. This work presents a contribution to the automatization of the design of analog cores and, in order to do that, an essential core was chosen: the operational amplifier. The choice for the operational amplifier was made in order to attend to a set of specifications provided by Freescale Semiconductors. This set was applied in the design of an audio pre-amplifier performed in the scope of the National Microelectronics Program – PNM. A topology chosen for the amplifier, extracted from [1], was analysed and applied to design the audio pre-amplifier. Additionaliy, a software for this specific amplifier was written, and its goal is to aid the redesign of the amplifier to comply with a set of specifications. In order to do this, the software receives, as input parameters, the set of specifications and the results of a first amplifier design, done by the analog designer using simplified equations. Then, together with an electrical simulator, the software redesigns the amplifier, reading some relevant information from the output file of the simulation and using more complete relations. At the end of this work, an example of amplifier was manufactured and characterized, and the final results were analyzed.
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Johansson, Jimmy. "Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-138446.

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Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.
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Kollarits, Matthew David. "Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application." University of Akron / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=akron1279036924.

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Puppala, Ajith kumar. "Design of a Low Power Cyclic/Algorithmic Analog-to-Digital Converter in a 130nm CMOS Process." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80132.

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Analog-to-digital converters are inevitable in the modern communication systems and there is always a need for the design of low-power converters. There are different A/D architectures to achieve medium resolution at medium speeds and among all those Cyclic/Algorithmic structure stands out due to its low hardware complexity and less die area costs. This thesis aims at discussing the ongoing trend in Cyclic/Algorithmic ADCs and their functionality. Some design techniques are studied on how to implement low power high resolution A/D converters. Also, non-ideal effects of SC implementation for Cyclic A/D converters are explored. Two kinds of Cyclic A/D architectures are compared. One is the conventional Cyclic ADC with RSD technique and the other is Cyclic ADC with Correlated Level Shift (CLS) technique. This ADC is a part of IMST Design + Systems International GmbH project work and was designed and simulated at IMST GmbH. This thesis presents the design of a 12-bit, 1 Msps, Cyclic/Algorithmic Analog-to-Digital Converter (ADC) using the “Redundant Signed Digit (RSD)” algorithm or 1.5-bit/stage architecture with switched-capacitor (SC) implementation. The design was carried out in 130nm CMOS process with a 1.5 V power supply. This ADC dissipates a power of 1.6  mW when run at full speed and works for full-scale input dynamic range. The op-amp used in the Cyclic ADC is a two-stage folded cascode structure with Class A output stage. This op-amp in typical corner dissipates 631 uW power at 1.5 V power supply and achieves a gain of 77 dB with a phase margin of 64° and a GBW of 54 MHz at 2 pF load.
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Baskaran, Balakumaar, and Hari Shankar Elumalai. "High-Speed Hybrid Current mode Sigma-Delta Modulator." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060.

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The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.
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Navrátil, Jakub. "Návrh operačního zesilovače CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217898.

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The present work deals with issues of a design of operational transconductance amplifier in technology CMOS AMIS 0,7 um. The aim of the work is to design a accurate operational amplifier with a low input differential voltage.
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DUTRA, Odilon de Oliveira. "Um amplificador neural de baixo ruído e baixa potência utilizando uma Topologia Folded Cascode OTA com malha de realimentação PID e ganho ajustável para EEG SoC Arrays." reponame:Repositório Institucional da UNIFEI, 2012. http://repositorio.unifei.edu.br/xmlui/handle/123456789/1283.

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Submitted by repositorio repositorio (repositorio@unifei.edu.br) on 2018-05-21T18:32:14Z No. of bitstreams: 1 dissertacao_0039010.pdf: 2221663 bytes, checksum: 58bc21f0e5973e73018cd49f36c833ec (MD5)<br>Made available in DSpace on 2018-05-21T18:32:14Z (GMT). No. of bitstreams: 1 dissertacao_0039010.pdf: 2221663 bytes, checksum: 58bc21f0e5973e73018cd49f36c833ec (MD5) Previous issue date: 2012-03<br>Este presente trabalho descreve uma implementação CMOS em tecnologia ON 0.5 µm de um amplificador operacional de transcondutância (OTA) Folded Cascode projetado para gerar ruído referenciado à entrada (Input Referred Noise) mínimo para aplicações em arrays de sistemas integrados em chip (SoC) destinados a medições em eletroencefalogramas. É também descrita uma rede de realimentação proporcional, integral e derivativa (PID), imple_ mentada em pequena área de Silício, utilizando-se de um pseudo-resistor pMOS de alta resistência e pequenas capacitâncias de integração para controle de ganho em malha fechada através de chaves nMOS insensíveis a parasitas. Resultados de simulações pos layout mostram que o amplificador neural desenvolvido atinge em torno de 2.2 µVrms de ruído referenciado à entrada para 6 µA de corrente drenada total para uma tensão de alimentação de ± 1.8 V, obtendo assim um fator de eficiência à ruído (NEF) de 4.55 para uma largura de banda de 1.96 kHz e ganho central de 40.22 dB.
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Mácha, Petr. "Návrh převodníku DA s plně diferenčním výstupem v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316964.

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This diploma thesis deals with the design of eight-bit digital to analog coverter with fully differential outputs in technology I3T25 of ON Semiconductor company. The work contains the description of basic structures and characteristics of digital to analog converters. The main focus of the work is to design a converter and auxiliary circuits at the transistor level. The functionality of designed circuits is verified by simulation environment Cadence.
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Books on the topic "Folded cascode"

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Abu-Dayeh, Mahmoud A. A fast-settling folded-cascode CMOS operational amplifier. 1988.

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Abu-Dayeh, Mahmoud A. A fast-settling folded-cascode CMOS operational amplifier. 1988.

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Mannion, John. Cascades Fiction Folder 10-13: Supplement A (Cascade). HarperCollins Publishers, 1990.

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Jackson, Adrian. Cascade Coursework Folder 14-16: Supplement B (Collins Cascades). HarperCollins Publishers, 1991.

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Cascades Fiction Folder 10-13 (Collins Cascades). HarperCollins Publishers, 1990.

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Folded Map-Shasta & Cascade (Rand McNally City Maps). 3rd ed. Rand McNally & Company, 2001.

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Cascades Coursework Folder 14-16: Supplement A (Collins Cascades). HarperCollins Publishers, 1990.

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Book chapters on the topic "Folded cascode"

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Soni, Praveen, and Shweta Gautam. "An Enhanced Recycling Folded Cascode Amplifier." In Advances in Intelligent Systems and Computing. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0339-9_3.

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Santin, Edinei, Michael Figueiredo, João Goes, and Luís B. Oliveira. "CMOS Fully Differential Feedforward-Regulated Folded Cascode Amplifier." In Technological Innovation for Sustainability. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19170-1_62.

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Kalkote, Mayur T., and S. Ananiah Durai. "Enhancement of Transconductance Using Multi-Recycle Folded Cascode Amplifier." In Nanoelectronic Materials and Devices. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7191-1_11.

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Sharma, Anil, and Tripti Sharma. "Small–Signal Gain Investigation of Folded Cascode Op-Amps." In Communications in Computer and Information Science. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-3143-5_1.

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Saranya, M. N., Sriadibhatla Sridevi, and Rajasekhar Nagulapalli. "Gain Enhanced Single-Stage Split Folded Cascode Operational Transconductance Amplifier." In Soft Computing and Signal Processing. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8669-7_50.

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Islam, Mir Bintul, and M. Nizamuddin. "CNTFET Folded Cascode Operational Transconductance Amplifier: Design and Comparative Analysis." In Springer Proceedings in Materials. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-4685-3_45.

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Patra, Pravanjan, S. Kumaravel, and B. Venkatramani. "Design of Low Power Enhanced Fully Differential Recyclic Folded Cascode OTA." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-35615-5_30.

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Bhuvaneshwari, S., and S. Kanthamani. "A High-Gain Improved Linearity Folded Cascode LNA for Wireless Applicatıons." In Intelligent Sustainable Systems. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2894-9_47.

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Aggarwal, Bhawna, and Vaishali Sharma. "Analysis and Comparison of Various High Performance Folded Cascode OTA Topologies." In Lecture Notes in Mechanical Engineering. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-2794-1_3.

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Li, Simon C., C. H. Syu, and Kuan-Yu Chen. "Dual Gain Mode Folded-Cascode (DGMFC) Front-End for LTE 4G Handset Receiver." In Lecture Notes in Electrical Engineering. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-27323-0_91.

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Conference papers on the topic "Folded cascode"

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Anushree, Rupali Singh, and Jasdeep Kaur. "Performance Improvement of Folded Cascode and Recyclic Folded Cascode Operational Amplifier." In 2024 IEEE Region 10 Symposium (TENSYMP). IEEE, 2024. http://dx.doi.org/10.1109/tensymp61132.2024.10752191.

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Yang, Xiao, Yongqiang Chen, Hongrui Liao, and Jiangping He. "A Gain and Slew Rate Enhanced Recycling Folded Cascode Operational Amplifier." In 2024 4th International Symposium on Artificial Intelligence and Intelligent Manufacturing (AIIM). IEEE, 2024. https://doi.org/10.1109/aiim64537.2024.10934431.

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S, Rangeetha, Ganesh Babu C, Bavana K B, Devadharshini M, and Dharanya C. "Low Power CMOS Folded Electro Cascode Amplifier Design for Electrocardiogram Applications." In 2025 Fourth International Conference on Smart Technologies, Communication and Robotics (STCR). IEEE, 2025. https://doi.org/10.1109/stcr62650.2025.11019942.

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Máximo, Miguel, Mauro Santos, João Oliveira, Pedro Toledo, Ricardo Machado, and Luís Oliveira. "Implementation of NMOS-based LDO Using Recycling Folded-Cascode in 16 nm FinFET." In 2024 8th International Young Engineers Forum on Electrical and Computer Engineering (YEF-ECE). IEEE, 2024. http://dx.doi.org/10.1109/yef-ece62614.2024.10625344.

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Sergeenko, Marsel A., Vladislav E. Chumakov, and Nikolay N. Prokopenko. "Gallium Arsenide Operational Amplifier Based on a “Folded” Cascode Containing No Current Mirrors." In 2024 IEEE 25th International Conference of Young Professionals in Electron Devices and Materials (EDM). IEEE, 2024. http://dx.doi.org/10.1109/edm61683.2024.10615026.

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Arzate Palma, V. H., and F. Sandoval-Ibarra. "Slew-rate Comparison of single-ended amplifiers-the Folded Cascode and the Recycling Folded Cascode." In 2023 20th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE). IEEE, 2023. http://dx.doi.org/10.1109/cce60043.2023.10332866.

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Dillep, P., and Gaurav Saini. "Enhanced cascode node impedance to the improved recyclic folded cascode OTA." In 2014 International Conference on Advanced Communication, Control and Computing Technologies (ICACCCT). IEEE, 2014. http://dx.doi.org/10.1109/icaccct.2014.7019483.

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Kuo, Po-Yu, Gang-Jhih Fan, and Sheng-Da Tsai. "The enhancement of recycling folded cascode amplifier." In 2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW). IEEE, 2016. http://dx.doi.org/10.1109/icce-tw.2016.7520945.

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Iqbal, Usama M., Lubna S. Mahmood, Lim Nguyen, and Lutfi Albasha. "Folded Cascode Current Mirror Design using Cadence." In 2019 International Conference on Communications, Signal Processing, and their Applications (ICCSPA). IEEE, 2019. http://dx.doi.org/10.1109/iccspa.2019.8713755.

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Scanlan, A. "Fast settling gain boosted folded cascode amplifiers." In IET Irish Signals and Systems Conference (ISSC 2006). IEE, 2006. http://dx.doi.org/10.1049/cp:20060459.

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