Relevant bibliographies by topics / Folded cascode amplifier

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Folded cascode amplifier'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 February 2022

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Journal articles on the topic "Folded cascode amplifier"

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Song, Ming Xin, Yue Li, and Meng Meng Xu. "Design of High Gain CMOS Folded Cascode Operational Amplifier." Applied Mechanics and Materials 389 (August 2013): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.389.573.

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A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.
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Assaad, Rida S., and Jose Silva-Martinez. "The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier." IEEE Journal of Solid-State Circuits 44, no. 9 (September 2009): 2535–42. http://dx.doi.org/10.1109/jssc.2009.2024819.

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Wang, Zhe Fei, Yi Jiang Cao, and Ju Meng Feng. "A Design of High Performance CMOS Folded Cascode Operational Amplifier." Advanced Materials Research 981 (July 2014): 31–35. http://dx.doi.org/10.4028/www.scientific.net/amr.981.31.

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This paper describes a kind of folded cascode amplifier, which not only has high gain, large output swing characteristics, and its outputs can be self-compensation, it has a strong suppression capability with voltage noise. Based on a 0.5μm CMOS process uses two operational amplifiers. Through software emulation corrected the error which was caused by theoretical calculation. Has good performance in gain, noise, swing, phase margin, common mode rejection ratio and other parameters.
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Yavari, Mohammad. "A new class AB folded-cascode operational amplifier." IEICE Electronics Express 6, no. 7 (2009): 395–402. http://dx.doi.org/10.1587/elex.6.395.

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Koonapalli, Harish, and V. N. Ramakrishnan. "Design of Radiation Hardened Complementary Folded Cascode Amplifier." Materials Today: Proceedings 24 (2020): 1766–76. http://dx.doi.org/10.1016/j.matpr.2020.03.601.

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Zhao, Xiao, Huajun Fang, and Jun Xu. "A power-efficient improved recycling folded cascode amplifier." International Journal of Electronics 100, no. 12 (December 2013): 1660–66. http://dx.doi.org/10.1080/00207217.2012.752040.

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Raman, J., P. Rombouts, and L. Weyten. "Folded-cascode amplifier with efficient feedforward gain-boosting." Electronics Letters 46, no. 21 (2010): 1425. http://dx.doi.org/10.1049/el.2010.2543.

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Yosefi, Ghader. "The high recycling folded cascode (HRFC): A general enhancement of the recycling folded cascode operational amplifier." Microelectronics Journal 89 (July 2019): 70–90. http://dx.doi.org/10.1016/j.mejo.2019.04.016.

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Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (March 4, 2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.
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Zhao, Xiao, Huajun Fang, and Jun Xu. "Phase-margin enhancement technique for recycling folded cascode amplifier." Analog Integrated Circuits and Signal Processing 74, no. 2 (December 18, 2012): 479–83. http://dx.doi.org/10.1007/s10470-012-0011-9.

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Dissertations / Theses on the topic "Folded cascode amplifier"

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Marino, Allison Margaret. "A clamped folded cascode amplifier for analog-to-digital converter applications." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35406.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (leaves 67-68).
by Allison Margaret Marino.
M.S.
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Johansson, Jimmy. "Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-138446.

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Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.
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Navrátil, Jakub. "Návrh operačního zesilovače CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217898.

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The present work deals with issues of a design of operational transconductance amplifier in technology CMOS AMIS 0,7 um. The aim of the work is to design a accurate operational amplifier with a low input differential voltage.
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Säll, Erik. "Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1353.

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This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter.

A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type.

The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase.

The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.

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Neto, Murillo Fraguas Franco. "Técnica para o projeto de um amplificador operacional folded cascode, classe AB, em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05092006-152855/.

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A tendência mundial em torno de sistemas SoC – System on Chip – baseados em processo CMOS – Complementary Metal Oxide Semiconductor – digital, apresenta cada vez mais desafios aos projetistas de circuitos integrados. Em especial se observa que enquanto os projetistas de circuitos digitais podem contar com bibliotecas cada vez mais completas de células digitais semi-prontas e ferramentas cada vez mais poderosas para o aprimoramento do projeto, os projetistas analógicos não contam com tais facilidades, sendo necessário realizar o projeto de novas células analógicas para cada especificação recebida. Este trabalho apresenta uma contribuição para a automatização do projeto de blocos analógicos e, para isso, foi escolhido um bloco essencial em muitos projetos analógicos: o amplificador operacional – ampOp. A idéia inicial por trás dessa escolha foi um conjunto de especificações fornecido pela empresa Freescale Semiconductors, para o projeto um préamplificador de áudio realizado no âmbito do Programa Nacional de Microeletrônica – PNM. A topologia escolhida para o amplificador operacional, retirada de [1], foi analisada e utilizada para projeto do amplificador para áudio. Além disso, um software de auxílio ao projeto para este amplificador foi escrito em linguagem C, e seu objetivo é auxiliar no reprojeto do ampOp para atender à especificações diversas. Para isso o software recebe como entradas as próprias especificações e um primeiro projeto do ampOp, realizado com equações simplificadas de projeto. O software então, em conjunto com um simulador elétrico, reprojeta o amplificador, retirando alguns parâmetros relevantes dos arquivos de simulação e utilizando equações de projeto mais completas. Ao final do trabalho, um exemplo de ampOp foi fabricado e caracterizado, sendo os resultados obtidos analisados.
The world trend towards SoC – System on Chip – based on digital CMOS – Complementary Metal Oxide Semiconductor – process presents more and more challenges to the IC designer. One can observe that while digital designers may rely on digital core libraries that are more and more complete, and design tools that are increasingly powerful and capable of optimizing the digital design, analog designers do not have such privileges available, becoming necessary to design such analog cores each time a new set of specifications is received. This work presents a contribution to the automatization of the design of analog cores and, in order to do that, an essential core was chosen: the operational amplifier. The choice for the operational amplifier was made in order to attend to a set of specifications provided by Freescale Semiconductors. This set was applied in the design of an audio pre-amplifier performed in the scope of the National Microelectronics Program – PNM. A topology chosen for the amplifier, extracted from [1], was analysed and applied to design the audio pre-amplifier. Additionaliy, a software for this specific amplifier was written, and its goal is to aid the redesign of the amplifier to comply with a set of specifications. In order to do this, the software receives, as input parameters, the set of specifications and the results of a first amplifier design, done by the analog designer using simplified equations. Then, together with an electrical simulator, the software redesigns the amplifier, reading some relevant information from the output file of the simulation and using more complete relations. At the end of this work, an example of amplifier was manufactured and characterized, and the final results were analyzed.
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Fan, Gang Jhih, and 范綱智. "An Improved Recycling Folded Cascode Amplifier Design." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/47851782347207274400.

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碩士
國立雲林科技大學
電子工程系
104
This study presented an improved recycling folded cascode amplifier and it significantly improves the DC gain and gain bandwidth of traditional recycling folded cascode amplifier. To enhance the circuit performance, the nested Miller compensation technique has been applied to improve the traditional recycling folded cascode amplifier. The proposed circuit has been implemented and verified using TSMC 0.18um 1P6M CMOS process with 1.8V power supply and 5.6pF capacitor load. From the simulation results, the propose amplifier can achieve 135dB DC gain, 〖65〗^° phase margin, and 12MHz gain bandwidth.
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Hung, Hen-Cho, and 洪亨籌. "Low Voltage Folded Cascode Low Noise Amplifier Study and Application." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/66588538260430400296.

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碩士
國立雲林科技大學
電子與資訊工程研究所
93
In this dissertation, we discuss general low-voltage low noise amplifier principle and design. It includes nowadays dual band and ultra wideband low noise amplifier principle and design. Finally, we compare simulation results with measurement values. We adopt a low-voltage folded cascode topology to design the circuits of low noise amplifier for the receiver path of WLAN and WPAN. The circuits of low noise amplifier are based on 0.18um TSMC CMOS technology. In WLAN application, measurement data shows that the amplifier achieves maximum power gain of 9.2 dB, input return loss of -9.6 dB, output return loss of -21.5 dB, and minimal noise figure of 3.1 dB on the 5.7 GHz while consuming 7 mW, For the dual-band LNA, simulation results get a power gain of 18.24 dB and 14.2 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure is less than 3 dB at both 2.4 GHz and 5.2 GHz bands. In WPAN application, the maximum and minimum power gain of ultra wideband LNA are 13.16 dB and 10.44 dB, respectively. The -3dB bandwidth ranges between 3 GHz to 10 GHz in the circuit of the ultra wideband LNA. The minimum noise figure is also 2.67 dB owing to folded cascode technique. Hence, the noise figure is less than 3.9 dB within the range between 3 GHz to 10 GHz. In these circuits, the relatively high linearity was achieved without compromising power dissipation, gain and noise figure. The simulation is performed by the Agilent Advance Design System (ADS) sofeware. The circuit layout and verification is fished by Cadance.
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Chen, Chang Yi, and 陳章益. "The Design of A Fully Differential CMOS Folded Cascode Operation Amplifier and Its Applications." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/04558796499989113096.

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碩士
義守大學
電子工程學系
89
In this thesis, a fully differential folded cascode amplifier which can be implemented by standard digital CMOS process is presented.The design of the circuit’s architecture and it’s characteristic, is for the circuit architecture, the effects of different circuit architectures is analyzed, and the effect of the bias circuit is also analyzed. For circuit characteristics one section looks at a fully differential characteristic and the other at single ended output characteristic. To prevent noise capability of fully differential circuit is better than the single ended output circuit. A fully differential folded cascode amplifier, a single ended output amplifier, feedback network amplifiers, a fully differential non-reset switch-capacitor sample and hold circuit, a single ended output non-reset switch-capacitor sample and hold circuit, and a fully differential multiple resistor stage digital-to-analog converter circuit are designed and implemented.
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Books on the topic "Folded cascode amplifier"

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Abu-Dayeh, Mahmoud A. A fast-settling folded-cascode CMOS operational amplifier. 1988.

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Abu-Dayeh, Mahmoud A. A fast-settling folded-cascode CMOS operational amplifier. 1988.

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Book chapters on the topic "Folded cascode amplifier"

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Soni, Praveen, and Shweta Gautam. "An Enhanced Recycling Folded Cascode Amplifier." In Advances in Intelligent Systems and Computing, 25–34. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0339-9_3.

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Santin, Edinei, Michael Figueiredo, João Goes, and Luís B. Oliveira. "CMOS Fully Differential Feedforward-Regulated Folded Cascode Amplifier." In Technological Innovation for Sustainability, 565–72. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19170-1_62.

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Kalkote, Mayur T., and S. Ananiah Durai. "Enhancement of Transconductance Using Multi-Recycle Folded Cascode Amplifier." In Nanoelectronic Materials and Devices, 111–22. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7191-1_11.

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Tyagi, Priyanka, Sanjay Kumar Singh, and Piyush Dua. "Design and simulation of CNTFET-based folded cascode Op-Amp for instrumentation amplifier." In Smart Computing, 684–93. London: CRC Press, 2021. http://dx.doi.org/10.1201/9781003167488-86.

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Soman, Vanitha, and Sudhakar S. Mande. "Design of a Two-Stage Folded Cascode Amplifier Using SCL 180 nm CMOS Technology." In Lecture Notes in Electrical Engineering, 423–30. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2612-1_41.

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Bendre, Varsha, Abdul Kadir Kureshi, and Saurabh Waykole. "A Low Power, High Swing and Robust Folded Cascode Amplifier at Deep Submicron Technology." In Information and Communication Technology for Competitive Strategies, 605–14. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-0586-3_59.

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"Design of high performance folded-cascode operational amplifier." In Information Science and Electronic Engineering, 451–54. CRC Press, 2016. http://dx.doi.org/10.1201/9781315265278-103.

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Marzuki, Arjuna, Mohd Tafir Mustaffa, Norlaili Mohd Noh, and Basir Saibon. "Analog Circuit of Light Detector for CMOS Image Sensor." In Optoelectronics in Machine Vision-Based Theories and Applications, 17–48. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-5751-7.ch002.

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Plant phenotyping studies represent a challenge in agriculture application. The studies normally employ CMOS optical and image sensor. One of the most difficult challenges in designing the CMOS sensor is the need to achieve good sensitivity while achieving low noise and low power simultaneously for the sensor. At low power, the CMOS amplifier in the sensor is normally having a lower gain, and it becomes even worse when the frequency of the interest is in the vicinity of flicker noise region. Using conventional topology such as folded cascode will result in the CMOS amplifier having high gain, but with the drawback of high power. Hence, there is a need for a new approach that improves the sensitivity of the CMOS sensor while achieving low power. The objective of this chapter is to update CMOS sensors and to introduce a modified light integrating circuit which is suitable for CMOS image sensor.
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Conference papers on the topic "Folded cascode amplifier"

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Kuo, Po-Yu, Gang-Jhih Fan, and Sheng-Da Tsai. "The enhancement of recycling folded cascode amplifier." In 2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW). IEEE, 2016. http://dx.doi.org/10.1109/icce-tw.2016.7520945.

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Kuo, Po-Yu, and Sheng-Da Tsai. "A compensation technique for recycling folded-cascode amplifier." In 2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW). IEEE, 2017. http://dx.doi.org/10.1109/icce-china.2017.7991047.

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Lipka, B., U. Kleine, J. C. Scheytt, and K. Schmalz. "Design of a complementary folded-cascode operational amplifier." In 2009 IEEE International SOC Conference (SOCC). IEEE, 2009. http://dx.doi.org/10.1109/soccon.2009.5398081.

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Mal, Ashis Kumar, Rishi Todani, and Om Prakash Hari. "Design of tunable folded cascode differential amplifier using PDM." In Informatics (ISCI). IEEE, 2011. http://dx.doi.org/10.1109/isci.2011.5958930.

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Sun, Jin, and Xiaolin Zhang. "A low power wide bandwidth CMOS folded-cascode amplifier." In International Conference on Space Information Technology 2009, edited by Xingrui Ma, Baohua Yang, and Ming Li. SPIE, 2009. http://dx.doi.org/10.1117/12.855496.

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Vij, Saumya, Anu Gupta, and Alok Mittal. "A Highly Adaptive Operational Amplifier with Recycling Folded Cascode Topology." In Fourth International Conference on Computer Science, Engineering and Applications. Academy & Industry Research Collaboration Center (AIRCC), 2014. http://dx.doi.org/10.5121/csit.2014.4721.

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Cerida, Sammy, Erick Raygada, Carlos Silva, and Manuel Monge. "A low-noise fully differential recycling folded cascode neural amplifier." In 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS 2015). IEEE, 2015. http://dx.doi.org/10.1109/lascas.2015.7250497.

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Lei, Ma, Ding Ying-tao, and Wang Xing-hua. "A folded cascode OTA using current-mode gain-boost amplifier." In 2010 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2010. http://dx.doi.org/10.1109/smelec.2010.5549417.

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Enche Ab Rahim, S. A., Mohd Azmi Ismail, Ahmad Ismat Abdul Rahim, M. R. Yahya, and Abdul Fatah Awang Mat. "A wide gain-bandwidth CMOS fully-differential folded cascode amplifier." In 2010 International Conference on Electronic Devices, Systems and Applications (ICEDSA). IEEE, 2010. http://dx.doi.org/10.1109/icedsa.2010.5503080.

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Raja, V. Sudheer, and S. Kumaravel. "Design of recycling folded cascode amplifier using potential distribution method." In 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS). IEEE, 2017. http://dx.doi.org/10.1109/icmdcs.2017.8211570.

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