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Journal articles on the topic 'Folded cascode amplifier'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 February 2022

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1

Song, Ming Xin, Yue Li, and Meng Meng Xu. "Design of High Gain CMOS Folded Cascode Operational Amplifier." Applied Mechanics and Materials 389 (August 2013): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.389.573.

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A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

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2

Assaad, Rida S., and Jose Silva-Martinez. "The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier." IEEE Journal of Solid-State Circuits 44, no. 9 (September 2009): 2535–42. http://dx.doi.org/10.1109/jssc.2009.2024819.

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3

Wang, Zhe Fei, Yi Jiang Cao, and Ju Meng Feng. "A Design of High Performance CMOS Folded Cascode Operational Amplifier." Advanced Materials Research 981 (July 2014): 31–35. http://dx.doi.org/10.4028/www.scientific.net/amr.981.31.

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This paper describes a kind of folded cascode amplifier, which not only has high gain, large output swing characteristics, and its outputs can be self-compensation, it has a strong suppression capability with voltage noise. Based on a 0.5μm CMOS process uses two operational amplifiers. Through software emulation corrected the error which was caused by theoretical calculation. Has good performance in gain, noise, swing, phase margin, common mode rejection ratio and other parameters.

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4

Yavari, Mohammad. "A new class AB folded-cascode operational amplifier." IEICE Electronics Express 6, no. 7 (2009): 395–402. http://dx.doi.org/10.1587/elex.6.395.

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5

Koonapalli, Harish, and V. N. Ramakrishnan. "Design of Radiation Hardened Complementary Folded Cascode Amplifier." Materials Today: Proceedings 24 (2020): 1766–76. http://dx.doi.org/10.1016/j.matpr.2020.03.601.

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6

Zhao, Xiao, Huajun Fang, and Jun Xu. "A power-efficient improved recycling folded cascode amplifier." International Journal of Electronics 100, no. 12 (December 2013): 1660–66. http://dx.doi.org/10.1080/00207217.2012.752040.

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7

Raman, J., P. Rombouts, and L. Weyten. "Folded-cascode amplifier with efficient feedforward gain-boosting." Electronics Letters 46, no. 21 (2010): 1425. http://dx.doi.org/10.1049/el.2010.2543.

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8

Yosefi, Ghader. "The high recycling folded cascode (HRFC): A general enhancement of the recycling folded cascode operational amplifier." Microelectronics Journal 89 (July 2019): 70–90. http://dx.doi.org/10.1016/j.mejo.2019.04.016.

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9

Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (March 4, 2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

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10

Zhao, Xiao, Huajun Fang, and Jun Xu. "Phase-margin enhancement technique for recycling folded cascode amplifier." Analog Integrated Circuits and Signal Processing 74, no. 2 (December 18, 2012): 479–83. http://dx.doi.org/10.1007/s10470-012-0011-9.

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11

Zhao, Xiao, Huajun Fang, and Jun Xu. "A transconductance enhanced recycling structure for folded cascode amplifier." Analog Integrated Circuits and Signal Processing 72, no. 1 (February 19, 2012): 259–63. http://dx.doi.org/10.1007/s10470-012-9843-6.

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12

Vallee, R. E., and E. I. El-Masry. "A very high-frequency CMOS complementary folded cascode amplifier." IEEE Journal of Solid-State Circuits 29, no. 2 (1994): 130–33. http://dx.doi.org/10.1109/4.272117.

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13

Wang, Lin Feng, Qiao Meng, and Hao Zhi. "Design of a Gain-Boosted Cascode Amplifier with High Unity-Bandwidth." Applied Mechanics and Materials 614 (September 2014): 237–40. http://dx.doi.org/10.4028/www.scientific.net/amm.614.237.

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This paper presents a high unity gain bandwidth fully differential folded-cascode operational amplifier using gain-boosted technique. The amplifier is designed in TSMC 0.18μm 1P6M CMOS technology. The unity-gain bandwidth (GBW) and poles of the gain-boosting amplifiers were carefully designed to improve the stability. The implemented design provides a direct current (DC) gain of around 93 dB with a unity gain frequency of 1.8GHz. It exhibits a DC gain larger than 88dB when the output common-mode voltage between 0.6 V and 1.2V. the overall layout size is 96μm×120μm.

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14

Nagulapalli, R., K. Hayatleh, S. Barker, B. Yassine, S. Zourob, S. Raparthy, and N. Yassine. "A Start-up Assisted Fully Differential Folded Cascode Opamp." Journal of Circuits, Systems and Computers 28, no. 10 (September 2019): 1950164. http://dx.doi.org/10.1142/s0218126619501640.

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This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87[Formula: see text]dB, 250[Formula: see text]MHz unity gain bandwidth amplifier has been developed in 65[Formula: see text]nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126[Formula: see text][Formula: see text]A from a 1.2[Formula: see text]V supply and occupies the 2184[Formula: see text][Formula: see text]m2 area.

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15

Su, C., B. J. Blalock, S. K. Islam, L. Zuo, and L. M. Tolbert. "A High-Temperature Folded-Cascode Operational Transconductance Amplifier in 0.8-μm BCD-on-SOI." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000083–88. http://dx.doi.org/10.4071/hitec-csu-ta26.

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The rapid growth of the hybrid electric vehicles (HEVs) has been driving the demand of high temperature automotive electronics target for the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. An operational transconductance amplifier (OTA) is an essential building block of various analog circuits such as data converters, instrumentation systems, linear regulators, etc. This work presents a high temperature folded cascode operational transconductance amplifier designed and fabricated in a commercially available 0.8-μm BCD-on-SOI process. SOI processes offer several orders of magnitude smaller junction leakage current than bulk-CMOS processes at temperatures beyond 150°C. This amplifier is designed for a high temperature linear voltage regulator; the higher open-loop gain of this amplifier will enhance the overall performance of a linear regulator. In addition, the lower current consumption of the OTA is critical for improving the current efficiency of the linear regulator and reducing the power dissipation at elevated temperature. A PMOS input pair folded cascode OTA topology had been selected in this work, PMOS input pair offers wider ICMR (input common-mode range) and empirically lower flicker noise compared to its NMOS counterpart. By cascoding current mirror load at the output node, the folded cascode OTA obtains higher voltage gain than the symmetrical OTA topology. The PSRR (power supply rejection ratio) is also improved. A on-chip temperature stable current reference is employed to bias the amplifier. The amplifier consumes less than 65μA bias current at 175°C. The core layout area of the amplifier is 0.16mm2 (400 μm × 400 μm).

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16

Kanthi, T., and D. Sharath Babu Rao. "Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 143. http://dx.doi.org/10.11591/ijres.v7.i3.pp143-150.

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This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

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17

Kanthi, T., and D. Sharath Babu Rao. "Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 149. http://dx.doi.org/10.11591/ijres.v7.i3.pp149-156.

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This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

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18

Choi, Gyuri, Hyunwoo Heo, Donggeun You, Hyungseup Kim, Kyeongsik Nam, Mookyoung Yoo, Sangmin Lee, and Hyoungho Ko. "A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier." Applied Sciences 11, no. 17 (August 28, 2021): 7982. http://dx.doi.org/10.3390/app11177982.

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In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

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19

Bendre, Varsha S., A. K. Kureshi, and Saurabh Waykole. "Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier." Journal of Nanotechnology 2018 (December 4, 2018): 1–15. http://dx.doi.org/10.1155/2018/2301421.

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Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

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20

Chan, P. K., L. S. Ng, L. Siek, and K. T. Lau. "Designing CMOS folded-cascode operational amplifier with flicker noise minimisation." Microelectronics Journal 32, no. 1 (January 2001): 69–73. http://dx.doi.org/10.1016/s0026-2692(00)00105-1.

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21

Assaad, R., and J. Silva-Martinez. "Enhancing general performance of folded cascode amplifier by recycling current." Electronics Letters 43, no. 23 (2007): 1243. http://dx.doi.org/10.1049/el:20072031.

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22

Li, Yilei, Kefeng Han, Na Yan, Xi Tan, and Hao Min. "Analysis and implementation of an improved recycling folded cascode amplifier." Journal of Semiconductors 33, no. 2 (February 2012): 025002. http://dx.doi.org/10.1088/1674-4926/33/2/025002.

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23

Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (January 11, 2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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24

Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (January 11, 2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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25

KIHARA, Takao, Hae-Ju PARK, Isao TAKOBE, Fumiaki YAMASHITA, Toshimasa MATSUOKA, and Kenji TANIGUCHI. "A 0.5V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier." IEICE Transactions on Electronics E92-C, no. 4 (2009): 564–75. http://dx.doi.org/10.1587/transele.e92.c.564.

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26

Kaur, Jasbir, and Neha Shukla. "Analysis of Two Stage Folded Cascode Operational Amplifier in 90nm Technology." IJIREEICE 5, no. 6 (June 15, 2017): 149–56. http://dx.doi.org/10.17148/ijireeice.2017.5626.

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27

Zhao, Xiao, Yongqing Wang, and Liyuan Dong. "Super current recycling folded cascode amplifier with ultra-high current efficiency." Integration 62 (June 2018): 322–28. http://dx.doi.org/10.1016/j.vlsi.2018.03.019.

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28

Mallya, S., and J. H. Nevin. "Design procedures for a fully differential folded-cascode CMOS operational amplifier." IEEE Journal of Solid-State Circuits 24, no. 6 (1989): 1737–40. http://dx.doi.org/10.1109/4.45013.

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29

Vij, Saumya, Anu Gupta, and Alok Mittal. "An Operational Amplifier with Recycling Folded Cascode Topology and Adaptive Biasing." International Journal of VLSI Design & Communication Systems 5, no. 4 (August 31, 2014): 33–46. http://dx.doi.org/10.5121/vlsic.2014.5403.

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30

Khade, Amitkumar S., Sandeep Musale, Ravikant Suryawanshi, and Vibha Vyas. "A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier." Analog Integrated Circuits and Signal Processing 107, no. 1 (February 26, 2021): 227–38. http://dx.doi.org/10.1007/s10470-021-01809-y.

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31

Du, Yiheng, Changde He, Guowei Hao, Wendong Zhang, and Chenyang Xue. "Full-Differential Folded-Cascode Front-End Receiver Amplifier Integrated Circuit for Capacitive Micromachined Ultrasonic Transducers." Micromachines 10, no. 2 (January 25, 2019): 88. http://dx.doi.org/10.3390/mi10020088.

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This paper describes the design of a front-end receiver amplifier for capacitive micromachined ultrasonic transducer (CMUT). The proposed operational amplifier (op amp) consists of a full differential folded-cascode amplifier stage followed by a class AB output stage. A feedback resistor is applied between the input and the output of the op amp to make a transimpedance amplifier. We analyzed the equivalent circuit model of the CMUT element operating in the receiving mode and obtained the static output impedance and center frequency characteristics of the CMUT. The op amp gain, bandwidth, noise, and power consumption trade-oﬀs are discussed in detail. The amplifier was fabricated using GlobalFoundries 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The open loop gain of the amplifier is approximately 65 dB, and its gain bandwidth product is approximately 29.5 MHz. The measured input reference noise current was 56 nA/√Hz@3 MHz. The amplifier chip area is 325 μm × 150 μm and the op amp is powered by 3.3 V, the static power consumption is 11 mW. We verified the correct operation of our amplifier with CMUT and echo-pulse shown that the CMUT center frequency is 3 MHz with 92% fractional bandwidth.

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32

Idros, Norhamizah, Zulfiqar Ali Abdul Aziz, and Jagadheswaran Rajendran. "A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier." Microelectronics International 37, no. 4 (September 11, 2020): 205–13. http://dx.doi.org/10.1108/mi-05-2020-0030.

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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33

Zhao, Xiao, Qisheng Zhang, Yongqing Wang, and Ming Deng. "Transconductance and slew rate improvement technique for current recycling folded cascode amplifier." AEU - International Journal of Electronics and Communications 70, no. 3 (March 2016): 326–30. http://dx.doi.org/10.1016/j.aeue.2015.12.015.

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34

Ibarra, F. Sandoval, V. H. Arzate Palma, and S. D. Cárdenas Castellón. "Design of a Fully Differential CMOS OTA Folded Cascode for Modulation." International Journal of Emerging Technology and Advanced Engineering 10, no. 11 (November 30, 2020): 1–6. http://dx.doi.org/10.46338/ijetae1120_01.

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In this paper, the design and experimental results of a fully-differential folded-cascode operational amplifier of transconductance (OTA) is presented. This active circuit is for the use in a  low-pass modulator. The structure of the OTA is for obtaining a transition frequency of 1.0GHz. From the circuit synthesis, the OTA can handle the signals with the peak-to-peak amplitude of 300mV, and consumes 1.5mA from 1.2V supply. The OTA is fabricated in 130nm standard CMOS technology.

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35

Becchetti, Simone, Anna Richelli, Luigi Colalongo, and Zsolt Kovacs-Vajna. "A Comprehensive Comparison of EMI Immunity in CMOS Amplifier Topologies." Electronics 8, no. 10 (October 17, 2019): 1181. http://dx.doi.org/10.3390/electronics8101181.

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This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected interference can indeed directly reach the amplifier pins or can be coupled from the printed circuit board (PCB) ground. This is also a key point for evaluating the susceptibility from EMI coupled to the output pin. All of the amplifiers are re-designed in a United Microelectronics Corporation (UMC) 180 nm CMOS process in order to have a fair comparison. The topologies investigated and compared are basically derived from the Miller and the folded cascode ones, which are well-known and widely used by CMOS analog designers.

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36

Cui, Lin Hai, Rui Xu, Zhan Peng Jiang, and Chang Chun Dong. "Design of a Low-Voltage Low-Power CMOS Operational Amplifier." Applied Mechanics and Materials 380-384 (August 2013): 3283–86. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3283.

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A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

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37

Akbari, Meysam, and Omid Hashemipour. "Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits." Journal of Circuits, Systems and Computers 25, no. 11 (August 14, 2016): 1650144. http://dx.doi.org/10.1142/s0218126616501449.

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In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

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38

Park, Yoonji, and Sung Min Park. "A Dual-feedback Folded-cascode Fully Differential Transimpedance Amplifier in 65-nm CMOS." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 20, no. 3 (June 30, 2020): 281–87. http://dx.doi.org/10.5573/jsts.2020.20.3.281.

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39

Ahmadpour, Arash, and Pooya Torkzadeh. "An Enhanced Bulk-Driven Folded-Cascode Amplifier in 0.18 µm CMOS Technology." Circuits and Systems 03, no. 02 (2012): 187–91. http://dx.doi.org/10.4236/cs.2012.32025.

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40

Oskooei, Mostafa Savadi, Khayrollah Hadidi, and Abdollah Khoei. "A Novel Method for Bandwidth and Phase Margin Enhancement of Folded-Cascode Amplifier." Analog Integrated Circuits and Signal Processing 46, no. 2 (December 30, 2005): 91–98. http://dx.doi.org/10.1007/s10470-005-0652-z.

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41

Tae-Sung Kim and Byung-Sung Kim. "Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker." IEEE Microwave and Wireless Components Letters 16, no. 4 (April 2006): 182–84. http://dx.doi.org/10.1109/lmwc.2006.872131.

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42

Zhao, Xiao, Huajun Fang, and Jun Xu. "DC gain enhancement method for recycling folded cascode amplifier in deep submicron CMOS technology." IEICE Electronics Express 8, no. 17 (2011): 1450–54. http://dx.doi.org/10.1587/elex.8.1450.

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Ou, Jack, and Pietro M. Ferreira. "A $g_{m}/I_{D}$-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 10 (October 2014): 783–87. http://dx.doi.org/10.1109/tcsii.2014.2345297.

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Algueta-Miguel, Jose M., Antonio Lopez-Martin, M. Pilar Garde, Carlos A. De La Cruz, and Jaime Ramirez-Angulo. "±0.5 V 15 $\mu$ W Recycling Folded Cascode Amplifier With 34767 MHz·pF/mA FOM." IEEE Solid-State Circuits Letters 1, no. 7 (July 2018): 170–73. http://dx.doi.org/10.1109/lssc.2019.2896457.

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Gao, Zhiqiang, Bo Luan, Jincai Zhao, and Xiaowei Liu. "An integrated low 1/f noise and high-sensitivity CMOS instrumentation amplifier for TMR sensors." Modern Physics Letters B 31, no. 08 (March 20, 2017): 1750070. http://dx.doi.org/10.1142/s0217984917500701.

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In this paper, a very low 1/f noise integrated Wheatstone bridge magnetoresistive sensor ASIC based on magnetic tunnel junction (MTJ) technology is presented for high sensitivity measurements. The present CMOS instrumentation amplifier employs the gain-boost folded-cascode structure based on the capacitive-feedback chopper-stabilized technique. By chopping both the input and the output of the amplifier, combined with MTJ magnetoresistive sensitive elements, a noise equivalent magnetoresistance 1 nT/Hz[Formula: see text] at 2 Hz, the equivalent input noise spectral density 17 nV/Hz[Formula: see text](@2Hz) is achieved. The chip-scale package of the TMR sensor and the instrumentation amplifier is only about 5 mm × 5 mm × 1 mm, while the whole DC current dissipates only 2 mA.

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Becchetti, Simone, Anna Richelli, Luigi Colalongo, and Zsolt M. Kovacs-Vajna. "Complementary Metal Oxide Semiconductor Amplifier Behaviour Considering Different Points of Electromagnetic Interference Injection." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 361–67. http://dx.doi.org/10.1166/jolpe.2019.1624.

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In this paper the CMOS amplifier behaviour has been further investigated respect to the previous works in the literature. An exhaustive scenario for the EMI pollution has been considered: the injected interferences can indeed directly reach the amplifier pins or can be coupled from the PCB ground. This is a key point for evaluating also the susceptibility from the EMI coupled to the output pin, which is disclosed as a critical point. The investigated topologies are basically derived from the Miller and the Folded Cascode, which are well-known and widely used by the CMOS analog designers; all of them are re-designed in UMC 180 nm CMOS process in order to have a fair comparison.

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Li, Shuoyang, Xiao Zhao, Liyuan Dong, Lanya Yu, and Yongqing Wang. "Design of a capacitor-less adaptively biased low dropout regulator using recycling folded cascode amplifier." AEU - International Journal of Electronics and Communications 135 (June 2021): 153745. http://dx.doi.org/10.1016/j.aeue.2021.153745.

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An, Chang-Ho, and Bai-Sun Kong. "High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications." Electronics 9, no. 12 (November 29, 2020): 2018. http://dx.doi.org/10.3390/electronics9122018.

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A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.

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Khade, Amitkumar S., Vibha Vyas, and Mukul Sutaone. "Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage." Integration 69 (November 2019): 242–50. http://dx.doi.org/10.1016/j.vlsi.2019.04.007.

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Guo, Min, Hong Hui Deng, Bo Wen Ding, and Yong Sheng Yin. "Design of a Second-Order Sigma-Delta Modulator." Applied Mechanics and Materials 644-650 (September 2014): 3797–801. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3797.

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A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of the sigma-delta modulator whose signal-noise rate is 103.9dB and resolution is 16.97bits.

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