Relevant bibliographies by topics / Folded cascode technique

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Folded cascode technique'

Author: Grafiati
Published: 5 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Folded cascode technique"

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Yan, Zushu, Pui-In Mak, and R. P. Martins. "Double recycling technique for folded-cascode OTA." Analog Integrated Circuits and Signal Processing 71, no. 1 (2011): 137–41. http://dx.doi.org/10.1007/s10470-011-9762-y.

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Meysam, Akbari, Biabanifard Sadegh, and Asadi Shahroz. "INPUT REFERRED NOISE REDUCTION TECHNIQUE FOR TRANSCONDUCTANCE AMPLIFIERS." Electrical & Computer Engineering: An International Journal (ECIJ) 4, no. 4 (2015): 11–22. https://doi.org/10.5281/zenodo.3611042.

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In this paper, a useful procedure to design folded cascode (FC) and recycling folded cascode (RFC) OTAs is presented. The proposed procedure is based on a simplified equation of input voltage noise in strong and weak inversion regions. The presented method considerably decreases the input referred noise of amplifiers in weak, moderate and strong inversion. The proposed amplifiers were simulated in 0.18µm CMOS technology, achieving 36% and 25% reduction of input voltage noise @ 1Hz in strong and weak inversion, respectively, compared to the conventional FC, without increasing power consum
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Zhao, Xiao, Huajun Fang, and Jun Xu. "Phase-margin enhancement technique for recycling folded cascode amplifier." Analog Integrated Circuits and Signal Processing 74, no. 2 (2012): 479–83. http://dx.doi.org/10.1007/s10470-012-0011-9.

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Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB
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Atkinson, Blaine, Kauppila, et al. "RHBD Technique for Single-Event Charge Cancellation in Folded-Cascode Amplifiers." IEEE Transactions on Nuclear Science 60, no. 4 (2013): 2756–61. http://dx.doi.org/10.1109/tns.2013.2240316.

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Setty, S., and C. Toumazou. "N-folded cascode technique for high frequency operation of low voltage opamps." Electronics Letters 32, no. 11 (1996): 955. http://dx.doi.org/10.1049/el:19960687.

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Zhao, Xiao, Qisheng Zhang, Yongqing Wang, and Ming Deng. "Transconductance and slew rate improvement technique for current recycling folded cascode amplifier." AEU - International Journal of Electronics and Communications 70, no. 3 (2016): 326–30. http://dx.doi.org/10.1016/j.aeue.2015.12.015.

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LEHMANN, TORSTEN, and MARCO CASSIA. "1 V OTA USING CURRENT DRIVEN BULK CIRCUITS." Journal of Circuits, Systems and Computers 11, no. 01 (2002): 81–91. http://dx.doi.org/10.1142/s0218126602000252.

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We show how the MOST threshold voltage can be reduced simply by forcing a constant current through the transistor bulk terminal. We characterize two versions of the resulting current driven bulk device by simulations, and conclude that this is a good method for improving circuit performance when the voltage supply is very low. Finally we show how the technique can be used to implement a 1 V folded cascode OTA with compatible input and output voltage ranges.
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Wang, Lin Feng, Qiao Meng, and Hao Zhi. "Design of a Gain-Boosted Cascode Amplifier with High Unity-Bandwidth." Applied Mechanics and Materials 614 (September 2014): 237–40. http://dx.doi.org/10.4028/www.scientific.net/amm.614.237.

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This paper presents a high unity gain bandwidth fully differential folded-cascode operational amplifier using gain-boosted technique. The amplifier is designed in TSMC 0.18μm 1P6M CMOS technology. The unity-gain bandwidth (GBW) and poles of the gain-boosting amplifiers were carefully designed to improve the stability. The implemented design provides a direct current (DC) gain of around 93 dB with a unity gain frequency of 1.8GHz. It exhibits a DC gain larger than 88dB when the output common-mode voltage between 0.6 V and 1.2V. the overall layout size is 96μm×120μm.
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Akbari, Meysam, and Omid Hashemipour. "Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits." Journal of Circuits, Systems and Computers 25, no. 11 (2016): 1650144. http://dx.doi.org/10.1142/s0218126616501449.

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In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded.
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Dissertations / Theses on the topic "Folded cascode technique"

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Johansson, Jimmy. "Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-138446.

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Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the se
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Book chapters on the topic "Folded cascode technique"

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Noh, Norlaili Mohd. "LNA Inventions." In Advances in Monolithic Microwave Integrated Circuits for Wireless Systems. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch002.

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The main design goals of an LNA are to achieve low noise figure, high gain, good linearity and good matching and reverse isolation. The choice of the LNA topology is therefore very important to suit the design application. Five LNA topologies were studied, analyzed and compared in this chapter. The topologies are the Simultaneous Noise and Input Matching (SNIM), Power-constrained Simultaneous Noise and Input Matching (PCSNIM), Current-reuse (CR) and Folded-cascode (FC) LNAs. The last topology is the PCSNIM with buffer. The circuits are analyzed in detail in terms of their functionality and compared based on the LNAs typical performance metrics. From the analysis, the PCSNIM technique can improve matching and noise performance of the inductively degenerated cascode. The current-reuse is found to consume less current but maintaining the circuit’s transconductance to achieve the desirable gain. The folded-cascode operates at lower voltage and hence is suitable for low-powered designs. Consequently, it is also resulting in the lowest noise-figure amongst the other designs.
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Conference papers on the topic "Folded cascode technique"

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Kuo, Po-Yu, and Sheng-Da Tsai. "A compensation technique for recycling folded-cascode amplifier." In 2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW). IEEE, 2017. http://dx.doi.org/10.1109/icce-china.2017.7991047.

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Benhala, Bachir. "Artificial Bee Colony Technique for Optimal Design of Folded Cascode OTA." In 2018 International Conference on Applied Mathematics & Computer Science (ICAMCS). IEEE, 2018. http://dx.doi.org/10.1109/icamcs46079.2018.00009.

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Farahmand, Sina, and Hossein Shamsi. "Positive feedback technique for DC-gain enhancement of folded cascode Op-Amps." In 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS). IEEE, 2012. http://dx.doi.org/10.1109/newcas.2012.6329006.

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Rahim, S. A. Enche Ab, and I. M. Azmi. "A CMOS single stage fully differential folded cascode amplifier employing gain boosting technique." In 2011 International Symposium on Integrated Circuits (ISIC). IEEE, 2011. http://dx.doi.org/10.1109/isicir.2011.6131939.

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Yu, Zhang, Zhao Xiao, and Dong Liyuan. "A Local Positive Feedback Loop-Reused Technique for Enhancing Performance of Folded Cascode Amplifier." In 2022 IEEE 4th International Conference on Circuits and Systems (ICCS). IEEE, 2022. http://dx.doi.org/10.1109/iccs56666.2022.9936572.

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Maymandi-Nejad, M., and M. Sachdev. "Using DTMOS technique in the design of common mode feedback in a 0.8 V folded cascode amplifier." In IEEE International Workshop on Biomedical Circuits and Systems, 2004. IEEE, 2004. http://dx.doi.org/10.1109/biocas.2004.1454100.

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Fahmy, Ghazal A., R. K. Pokharel, H. Kanaya, and K. Yoshida. "Indirect compensation technique based two-stage recycling folded cascode amplifier for reconfigurable multi-mode sigma-delta ADC." In 2010 IEEE International Conference of Electron Devices and Solid- State Circuits (EDSSC). IEEE, 2010. http://dx.doi.org/10.1109/edssc.2010.5713690.

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Prokopenko, Nikolay, Alexey Titov, Vladislav Chumakov, and Anna Bugakova. "The Circuit Technique for Reducing the Zero Level of the JFET Op-Amp on the Push-Pull Folded-Cascode." In 2022 IEEE International Multi-Conference on Engineering, Computer and Information Sciences (SIBIRCON). IEEE, 2022. http://dx.doi.org/10.1109/sibircon56155.2022.10016948.

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da Silva, Denis Rogerio, and Nobuo Oki. "An amplifier and capacitor sharing technique using recycling folded cascode operational amplifier with applications in MDAC of CMOS pipelined ADC." In 2015 Conference on Design of Circuits and Integrated Systems (DCIS). IEEE, 2015. http://dx.doi.org/10.1109/dcis.2015.7388613.

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Noh, Norlaili Mohd, Awatif Hashim, Kean Yeong Tan, and Yong Yeap Tan. "Design and analysis of the Current Reuse Technique and Folded Cascode Power Constrained Simultaneous Noise and Input Matching LNAs with distributed and lumped parasitic." In APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2010. http://dx.doi.org/10.1109/apccas.2010.5774902.

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Journal articles
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