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Journal articles on the topic 'Folded cascode technique'

Author: Grafiati

Published: 5 June 2025

Last updated: 15 July 2025

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1

Yan, Zushu, Pui-In Mak, and R. P. Martins. "Double recycling technique for folded-cascode OTA." Analog Integrated Circuits and Signal Processing 71, no. 1 (2011): 137–41. http://dx.doi.org/10.1007/s10470-011-9762-y.

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2

Meysam, Akbari, Biabanifard Sadegh, and Asadi Shahroz. "INPUT REFERRED NOISE REDUCTION TECHNIQUE FOR TRANSCONDUCTANCE AMPLIFIERS." Electrical & Computer Engineering: An International Journal (ECIJ) 4, no. 4 (2015): 11–22. https://doi.org/10.5281/zenodo.3611042.

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In this paper, a useful procedure to design folded cascode (FC) and recycling folded cascode (RFC) OTAs is presented. The proposed procedure is based on a simplified equation of input voltage noise in strong and weak inversion regions. The presented method considerably decreases the input referred noise of amplifiers in weak, moderate and strong inversion. The proposed amplifiers were simulated in 0.18µm CMOS technology, achieving 36% and 25% reduction of input voltage noise @ 1Hz in strong and weak inversion, respectively, compared to the conventional FC, without increasing power consum

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3

Zhao, Xiao, Huajun Fang, and Jun Xu. "Phase-margin enhancement technique for recycling folded cascode amplifier." Analog Integrated Circuits and Signal Processing 74, no. 2 (2012): 479–83. http://dx.doi.org/10.1007/s10470-012-0011-9.

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4

Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB

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5

Atkinson, Blaine, Kauppila, et al. "RHBD Technique for Single-Event Charge Cancellation in Folded-Cascode Amplifiers." IEEE Transactions on Nuclear Science 60, no. 4 (2013): 2756–61. http://dx.doi.org/10.1109/tns.2013.2240316.

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6

Setty, S., and C. Toumazou. "N-folded cascode technique for high frequency operation of low voltage opamps." Electronics Letters 32, no. 11 (1996): 955. http://dx.doi.org/10.1049/el:19960687.

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7

Zhao, Xiao, Qisheng Zhang, Yongqing Wang, and Ming Deng. "Transconductance and slew rate improvement technique for current recycling folded cascode amplifier." AEU - International Journal of Electronics and Communications 70, no. 3 (2016): 326–30. http://dx.doi.org/10.1016/j.aeue.2015.12.015.

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8

LEHMANN, TORSTEN, and MARCO CASSIA. "1 V OTA USING CURRENT DRIVEN BULK CIRCUITS." Journal of Circuits, Systems and Computers 11, no. 01 (2002): 81–91. http://dx.doi.org/10.1142/s0218126602000252.

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We show how the MOST threshold voltage can be reduced simply by forcing a constant current through the transistor bulk terminal. We characterize two versions of the resulting current driven bulk device by simulations, and conclude that this is a good method for improving circuit performance when the voltage supply is very low. Finally we show how the technique can be used to implement a 1 V folded cascode OTA with compatible input and output voltage ranges.

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9

Wang, Lin Feng, Qiao Meng, and Hao Zhi. "Design of a Gain-Boosted Cascode Amplifier with High Unity-Bandwidth." Applied Mechanics and Materials 614 (September 2014): 237–40. http://dx.doi.org/10.4028/www.scientific.net/amm.614.237.

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This paper presents a high unity gain bandwidth fully differential folded-cascode operational amplifier using gain-boosted technique. The amplifier is designed in TSMC 0.18μm 1P6M CMOS technology. The unity-gain bandwidth (GBW) and poles of the gain-boosting amplifiers were carefully designed to improve the stability. The implemented design provides a direct current (DC) gain of around 93 dB with a unity gain frequency of 1.8GHz. It exhibits a DC gain larger than 88dB when the output common-mode voltage between 0.6 V and 1.2V. the overall layout size is 96μm×120μm.

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10

Akbari, Meysam, and Omid Hashemipour. "Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits." Journal of Circuits, Systems and Computers 25, no. 11 (2016): 1650144. http://dx.doi.org/10.1142/s0218126616501449.

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In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded.

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11

Idros, Norhamizah, Zulfiqar Ali Abdul Aziz, and Jagadheswaran Rajendran. "A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier." Microelectronics International 37, no. 4 (2020): 205–13. http://dx.doi.org/10.1108/mi-05-2020-0030.

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process tec

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12

Laskar, Naushad Manzoor, Koushik Guha, Sourav Nath, K. L. Baishnab, and P. K. Paul. "Optimal Sizing of Recycling Folded Cascode Amplifier for Low-Frequency Applications Using New Hybrid Swarm Intelligence-Based Technique." Applied Artificial Intelligence 34, no. 12 (2020): 880–97. http://dx.doi.org/10.1080/08839514.2020.1790163.

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13

Laskar, Naushad Manzoor, Koushik Guha, Sourav Nath, K. L. Baishnab, and P. K. Paul. "Optimal Sizing of Recycling Folded Cascode Amplifier for Low Frequency Applications Using New Hybrid Swarm Intelligence-Based Technique." Applied Artificial Intelligence 34, no. 13 (2020): 994–1010. http://dx.doi.org/10.1080/08839514.2020.1795786.

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14

Hasan, S. M. Rezaul, and Nazmul Ula. "A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier." Electrical Engineering 88, no. 6 (2005): 509–17. http://dx.doi.org/10.1007/s00202-005-0306-2.

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15

Gao, Zhiqiang, Bo Luan, Jincai Zhao, and Xiaowei Liu. "An integrated low 1/f noise and high-sensitivity CMOS instrumentation amplifier for TMR sensors." Modern Physics Letters B 31, no. 08 (2017): 1750070. http://dx.doi.org/10.1142/s0217984917500701.

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In this paper, a very low 1/f noise integrated Wheatstone bridge magnetoresistive sensor ASIC based on magnetic tunnel junction (MTJ) technology is presented for high sensitivity measurements. The present CMOS instrumentation amplifier employs the gain-boost folded-cascode structure based on the capacitive-feedback chopper-stabilized technique. By chopping both the input and the output of the amplifier, combined with MTJ magnetoresistive sensitive elements, a noise equivalent magnetoresistance 1 nT/Hz[Formula: see text] at 2 Hz, the equivalent input noise spectral density 17 nV/Hz[Formula: see

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16

A. Ashok, Kumar, and Narayanam Balaji. "A comparative analysis of different current mirror techniques in 65nm technology." i-manager's Journal on Circuits and Systems 11, no. 1 (2023): 10. http://dx.doi.org/10.26634/jcir.11.1.19778.

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The Current Mirror (CM) technique is widely used in mixed-mode and analog integrated circuits for tasks such as current amplification, biasing, and active loading. The overall effectiveness of these circuits relies heavily on their efficient designs. Current mirrors are primarily employed to accurately replicate currents in a circuit, offering high stability, simplicity, and scalability. They have become indispensable building blocks in analog and mixed-signal circuits, with their significance growing along with the demand for high-performance and low-power designs. Numerous techniques have be

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17

Zhang, Xin, Chunhua Wang, Yichuang Sun, and Haijun Peng. "A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers." Journal of Circuits, Systems and Computers 27, no. 03 (2017): 1850047. http://dx.doi.org/10.1142/s0218126618500470.

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This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxi

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18

Sarkar, Arnab, and Soumya Shatakshi Panda. "Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique." Microsystem Technologies 23, no. 9 (2016): 4255–62. http://dx.doi.org/10.1007/s00542-016-2969-1.

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19

Khade, Amitkumar S., Vibha Vyas, and Mukul Sutaone. "A technique to enhance the transconductance of micro-power improved recycling folded cascode operational transconductance amplifier with reasonable phase margin." AEU - International Journal of Electronics and Communications 108 (August 2019): 148–57. http://dx.doi.org/10.1016/j.aeue.2019.06.026.

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20

Hayder, Khaleel AL-Qaysi, Mohammed Jasim Musaab, and Manhal Hameed Siraj. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 670–79. https://doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICEbased simulation results of very low-voltages (LVs) power supplies and highperformance specifications CMOS gate-driven (GD) operational amplifier (OpAmp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is

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21

Nasir, Ameerul Asyraf, Chu Liang Lee, Kah Yoong Chan, Lini Lee, and Senthilpari Chinnaiyan. "The Design of Low Power Op-amp for Biomedical Application." Journal of Engineering Technology and Applied Physics 6, no. 1 (2024): 25–31. http://dx.doi.org/10.33093/jetap.2024.6.1.4.

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This work presents a low-power operational amplifier (op-amp) circuit design which optimized and tailored specifically for biomedical circuit application in low power environment. The proposed op-amp design incorporates the folded cascode differential amplifier technique with a low voltage supply 1.2 V, utilizing current biasing, current mirrors, and adopted low-power circuit topologies. AC and DC analysis are carried out to analyse the performance of the proposed design. Extensive simulations executed using industrial standard EDA tool have validated the circuit design, and demonstrated a gai

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22

Yosefi, Ghader. "A special technique for Recycling Folded Cascode OTA to improve DC gain, bandwidth, CMRR and PSRR in 90 nm CMOS process." Ain Shams Engineering Journal 11, no. 2 (2020): 329–42. http://dx.doi.org/10.1016/j.asej.2019.08.018.

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23

Lai, Jui-Lin, Ting-You Lin, Cheng-Fang Tai та Rong-Jian Chen. "To Design a Cascode LNA by Using Channel-Length-Split Device with Constant-gm in a 0.35 μm Silicon CMOS Technology". Open Materials Science Journal 10, № 1 (2016): 79–88. http://dx.doi.org/10.2174/1874088x01610010079.

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In the paper, the folded-cascode low-noise operational amplifier (LNA) with constant-gm is proposed and analyzed. The channel-length split technique adopted to expand ratio of W/L of the differential pair transistor to improve the performance of LNA for the gain bandwidth product, noise and offset voltage. The channel-length split method is separated differential input transistor into 2 transistors in series. The area of the transistor (W, L) can be properly increased to effectively decrease the flick noise. The double indirect-frequency compensation technique and the clamping circuit are adop

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24

Sajja, Amrita, and S. Rooban. "Design of Low Power SAR ADC with Novel Regenerative Comparator." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (December 31, 2023): 166–72. http://dx.doi.org/10.37394/23201.2023.22.19.

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This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded c

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25

Panda, Madhusmita, Santosh Kumar Patnaik, Ashis Kumar Mal, and Sumalya Ghosh. "An evolutionary-based design methodology for performance enhancement of a folded-cascode OTA using symbiotic organisms search algorithm and gm/ID technique." Analog Integrated Circuits and Signal Processing 105, no. 2 (2020): 215–27. http://dx.doi.org/10.1007/s10470-020-01668-z.

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26

AL-Qaysi, Hayder Khaleel, Musaab Mohammed Jasim, and Siraj Manhal Hameed. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 670. http://dx.doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing

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27

Li, Xiang, Bo Hou, Chunge Ju, Qi Wei, Bin Zhou, and Rong Zhang. "A Complementary Recycling Operational Transconductance Amplifier with Data-Driven Enhancement of Transconductance." Electronics 8, no. 12 (2019): 1457. http://dx.doi.org/10.3390/electronics8121457.

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An improved operational transconductance amplifier (OTA) is presented in this work. The fully differential OTA adopts the current recycling technique and complementary NMOS and PMOS input branches to enhance the total transconductance. Moreover, in order to achieve higher current efficiency, a data-driven biasing circuit was developed to dynamically adjust the power consumption of the amplifier. Two comparators were added to detect the voltage difference at the input nodes, and when the differential input is large enough to activate either comparator, extra biasing current is activated and pou

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28

Basu, Joydeep, and Pradip Mandal. "Switched-Capacitor Common-Mode Feedback-Based Fully Differential Operational Amplifiers and its Usage in Implementation of Integrators." Journal of Circuits, Systems and Computers 29, no. 14 (2020): 2050223. http://dx.doi.org/10.1142/s0218126620502230.

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For stabilizing the common-mode output voltage of fully differential operational amplifiers, switched-capacitor (SC) type of common-mode feedback (CMFB) is a familiar technique. This is appropriate for implementing high-gain wide-swing low-power op-amps due to its benefits of minimum power consumption, superior linearity across a large amplifier output swing range, and improved feedback loop stability in comparison to continuous-time CMFB. However, the usage of SC-CMFB requires careful attention to some realistic aspects, details of many of which are available in literature. Nonetheless, its a

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29

Chaturvedi, Abhay, Mithilesh Kumar, Ram Swaroop Meena, and Vasireddy Raghu Ram Prasad. "Low-Voltage Low Noise Figure Down-Conversion Mixer for Band #1 of MB-OFDM System in 180 nm Complementary Metal Oxide Semiconductor Technology." Journal of Nanomaterials 2022 (September 24, 2022): 1–11. http://dx.doi.org/10.1155/2022/5617339.

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Low-voltage design is a challenge for Gilbert cell-based mixers due to stacking transconductance and switching stage. This work addresses this issue by proposing a design of a low-voltage down-conversion mixer for band #1 of multiband orthogonal frequency division multiplexing (MB-OFDM) system in 180 nm complementary metal oxide semiconductor (CMOS) technology. The mixer is tuned at band #1 at RF frequency of 3.432 GHz and IF frequency of 264 MHz. The proposed mixer uses folded cascode connection of LO and RF in order to increase headroom and to reduce the DC supply voltage for low-voltage ope

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30

Li, Wenhui, Daishi Tian, Hao Zhu, and Qingqing Sun. "A Programmable Gain Amplifier Featuring a High Power Supply Rejection Ratio for a 20-Bit Sigma-Delta ADC." Electronics 14, no. 4 (2025): 720. https://doi.org/10.3390/electronics14040720.

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A programmable gain amplifier (PGA) is commonly used to optimize the input dynamic range of high-performance systems such as headphones and biomedical sensors. But PGA is rather sensitive to electromagnetic interference (EMI), which limits the precision of these systems. Many capacitor-less low-dropout regulator (LDO) schemes with high power supply rejection have been proposed to act as the independent power supply for PGA, which consumes additional power and area. This paper proposed a PGA with a high power supply rejection ratio (PSRR) and low power consumption, which serves as the analog fr

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31

Jing, Kai, Yuhang Han, Shaoxiong Yuan, Rong Zhao, and Jiabo Cao. "A Piezoresistive-Sensor Nonlinearity Correction on-Chip Method with Highly Robust Class-AB Driving Capability." Sensors 24, no. 19 (2024): 6395. http://dx.doi.org/10.3390/s24196395.

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This paper presents a thorough robust Class-AB power amplifier design and its application in pressure-mode sensor-on-chip nonlinearity correction. Considering its use in piezoresistive sensing applications, a gain-boosting-aided folded cascode structure is utilized to increase the amplifier’s gain by a large amount as well as enhancing the power rejection ability, and a push–pull structure with miller compensation, a floating gate technique, and an adaptive output driving limiting structures are adopted to achieve high-efficiency current driving capability, high stability, and electronic envir

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32

Assaad, Rida, and Jose Silva-Martinez. "Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers." VLSI Design 2009 (July 28, 2009): 1–11. http://dx.doi.org/10.1155/2009/323595.

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Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which u

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33

Hsieh, H. H., J. H. Wang, and L. H. Lu. "Gain-Enhancement Techniques for CMOS Folded Cascode LNAs at Low-Voltage Operations." IEEE Transactions on Microwave Theory and Techniques 56, no. 8 (2008): 1807–16. http://dx.doi.org/10.1109/tmtt.2008.927304.

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34

Vasudeva, G., and Mandar Jatkar. "Design of High Performance Operational Transconductance Amplifier." ACS Journal for Science and Engineering 3, no. 2 (2023): 21–30. http://dx.doi.org/10.34293/acsjse.v3i2.81.

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Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in an analog circuit is the operational amplifier. At large supply voltages, there is a trade off among speed, power, and gain, amongs to ther performance parameters. Often these parameters present contradictory choices for the op-amp architecture. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture folded cascode OTA is used in which all th

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35

AL-Qaysi, Hayder Khaleel, Adham Hadi Saleh, and Tahreer Mahmood. "Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (2022): 4712. http://dx.doi.org/10.11591/ijece.v12i5.pp4712-4721.

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The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load

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36

Hayder, Khaleel AL-Qaysi, Hadi Saleh Adham, and Mahmood Tahreer. "Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (2022): 4712–21. https://doi.org/10.11591/ijece.v12i5.pp4712-4721.

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The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load

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37

Ahmad, Shadab, Mahaveer Singh Naruka, and Lidia Shanti Singavarapu. "UNVEILING THE POTENTIAL OF AN IMPROVED RECYCLING FOLDED CASCODE AMPLIFIER FOR CMOS OPERATIONAL TRANSCONDUCTANCE AMPLIFIER DESIGN AND OPTIMIZATION." ICTACT Journal on Microelectronics 9, no. 2 (2023): 1557–61. https://doi.org/10.21917/ijme.2023.0271.

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This paper presents the investigation and optimization of a Recycling Folded Cascode Amplifier (RFCA) for designing a highly efficient and high-performance CMOS Operational Transconductance Amplifier (OTA). The proposed RFCA architecture leverages recycling techniques to enhance the overall gain, linearity, and power efficiency of the OTA. By analyzing the operational principles of the RFCA and exploring various optimization strategies, this study unveils the significant potential of this improved architecture in the context of CMOS OTA design. Simulation results demonstrate superior performan

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38

Moosaei, Amir, Mohammad Hossein Maghami, Ali Nejati, Parviz Amiri, and Mohamad Sawan. "A Low-Power, Low-Noise Recycling Folded-Cascode Operational Transconductance Amplifier for Neural Recording Applications." Electronics 14, no. 8 (2025): 1543. https://doi.org/10.3390/electronics14081543.

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We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a

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39

Shopova, Ana, Silvia Shopova, Irina Stefanova, and Rumyana Kuzmanova. "Familial hyperinsulinaemic hypoglycaemia with epileptic syndrome, cognitive impairment and detected mutation of the ABCC 8 (SUR1) gene: a case report." Folia Medica 63, no. 5 (2021): 805–8. http://dx.doi.org/10.3897/folmed.63.e55696.

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Hyperinsulinaemic hypoglycaemia (HH) occurs as a consequence of unregulated insulin secretion from pancreatic beta cells. It is the most common cause of severe and prolonged hypoglycemia in newborns. HH is a major risk factor for brain damage and subsequent neurological disability, which is why the identification, rapid diagnosis, and timely treatment of patients with HH are essential for the prevention of brain damage. The present case gives a brief description of a patient with congenital HH with an established mutation in the ABCC8 gene encoding the SUR1 subunit of the K-ATP channel. The ge

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40

Liu, Hengzhi, Fei Xu, Hing Kit Kwan, Zhaohui Wu, and Bin Li. "A 1.5 V 20 kHz 108.07 dB SNR discrete-time dynamic zoom ADC based on ultra low leakage process." Journal of Physics: Conference Series 2810, no. 1 (2024): 012012. http://dx.doi.org/10.1088/1742-6596/2810/1/012012.

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Abstract This study introduces a hybrid discrete-time (DT) dynamic Zoom ADC based on the CanSemi 110-nm Mixed Signal CMOS process. The two-step conversion process, comprising parallel coarse and fine phases, is executed by a 5-bit asynchronous SAR ADC and a third-order ΣΔ modulator. Non-ideal effects present in Zoom ADC were analysed and quantified through modelling, deriving design specifications of circuits. Under the constraints of low power supply and high threshold voltages, boost circuits were implemented to counteract the MOS switch-on-resistance nonlinearity. The Operational Transcondu

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41

Sundaramoorthi, Panneerselvam, and Govindasamy Saravana Venkatesh. "DSTATCOM-BASED 15 LEVEL ASYMMETRICAL MULTILEVEL INVERTER FOR IMPROVING POWER QUALITY." Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska 14, no. 4 (2024): 63–70. https://doi.org/10.35784/iapgos.6355.

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This study suggests an asymmetric multilevel inverter based on DSTATCOM that employs SVPWM techniques to produce higher output levels. There are two steps in the suggested inverter. One full bridge and two half bridges make up the inverter's main stage. A full bridge converter had four switches and a single DC source, while half bridges have separate DC sources with a voltage ratio of 1:3:3. Every cell has a fixed neutral point and is connected in a cascaded fashion. The inverter's performance is not improved by setting the DC source values equally. A folded cascaded H-bridge circuit running a

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ONO, Koichi, Takeshi OHKAWA, Masahiro SEGAMI, and Masao HOTTA. "A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique." IEICE Transactions on Electronics E93-C, no. 3 (2010): 288–94. http://dx.doi.org/10.1587/transele.e93.c.288.

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Khanaki, Korosh, Adel Fekri, Mahmood Abedinzade, Ekram Mohammadi, and Fakhroddin Aghajanpour. "Potential anti-inflammatory effect of Lamium album extract through caspase-3 and cyclooxygenase-2 genes expression in a rat model of middle cerebral artery occlusion." Folia Medica 64, no. 2 (2022): 275–82. http://dx.doi.org/10.3897/folmed.64.e60562.

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Introduction: Stroke is one of the most common causes of death worldwide. Inflammation and apoptosis play an important role in the cascade of ischemic stroke. Aim: The aim of the present study was to evaluate the pretreatment effects of Lamium album (L. album) extract on caspase-3 and cyclooxygenase-2 (COX-2) expression, infarct volume, and neurological deficit score in a rat model of middle cerebral artery occlusion (MCAO). Materials and methods: Wistar male rats were randomly divided into three groups: 1) MCAO group (1 h after MCAO, reperfusion was allowed for 24 h by retracting the thread);

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Zhao, Wenzhuo. "Comparison Of Three CMOS Amplifiers Used in Communication." Highlights in Science, Engineering and Technology 111 (August 19, 2024): 18–23. http://dx.doi.org/10.54097/pkmmt761.

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With the rapid development of wireless communication technology, the low power consumption, low cost, and high efficiency of wireless communication equipment have become the development trend. Because of the increasing problems caused by power consumption, to meet the needs of people and the market, people should first understand the principle of low-power amplifiers and scientific research results to get inspiration. This paper summarizes the advantages and disadvantages of three kinds of amplifiers and draws some conclusions to better understand the low-power amplifier. Ultra-low power low n

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Han, Jingyu, Yu Jiang, Guiliang Guo, and Xu Cheng. "A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process." Electronics 9, no. 5 (2020): 831. http://dx.doi.org/10.3390/electronics9050831.

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A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generato

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Hadded, Ahmed, Mossaad Ben Ayed, and Shaya A. Alshaya. "An FPGA-Based SiNW-FET Biosensing System for Real-Time Viral Detection: Hardware Amplification and 1D CNN for Adaptive Noise Reduction." Sensors 25, no. 1 (2025): 236. https://doi.org/10.3390/s25010236.

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Impedance-based biosensing has emerged as a critical technology for high-sensitivity biomolecular detection, yet traditional approaches often rely on bulky, costly impedance analyzers, limiting their portability and usability in point-of-care applications. Addressing these limitations, this paper proposes an advanced biosensing system integrating a Silicon Nanowire Field-Effect Transistor (SiNW-FET) biosensor with a high-gain amplification circuit and a 1D Convolutional Neural Network (CNN) implemented on FPGA hardware. This attempt combines SiNW-FET biosensing technology with FPGA-implemented

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Swati, Kundra, Soni Priyanka, and Kundra Anshul. "LOW POWER FOLDED CASCODE OTA." February 29, 2012. https://doi.org/10.5121/vlsic.2012.3111.

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Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS tec

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Meysam, Akbari. "INPUT REFERRED NOISE REDUCTION TECHNIQUE FOR TRANSCONDUCTANCE AMPLIFIERS." December 30, 2015. https://doi.org/10.5281/zenodo.1209510.

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In this paper, a useful procedure to design folded cascode (FC) and recycling folded cascode (RFC) OTAs is presented. The proposed procedure is based on a simplified equation of input voltage noise in strong and weak inversion regions. The presented method considerably decreases the input referred noise of amplifiers in weak, moderate and strong inversion. The proposed amplifiers were simulated in 0.18µm CMOS technology, achieving 36% and 25% reduction of input voltage noise @ 1Hz in strong and weak inversion, respectively, compared to the conventional FC, without increasing power consum

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., Sudhakar, Imran Ullah Khan, and Nupur Mittal. "DESIGN AND SIMULATION OF LOW POWER, HIGH GAIN AND HIGH BANDWIDTH CMOS FOLDED CASCODE OTA USING RECYCLING AND gm/ID TECHNIQUE." International Research Journal of Computer Science, March 31, 2021, 41–45. http://dx.doi.org/10.26562/irjcs.2021.v0803.001.

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This paper includes the design of Enhanced Recycling folded cascode Operational Transconductance Amplifier (ERFC OTA) in both strong inversion and moderate inversion. The primary motivation for the design is from standard folded cascade (FC) OTA. The biased current sources are not contributing to the Transconductance (Gm) of the OTA in the usual FC OTA. In the Recycling FC OTA, the currents are recycled and the biased current sources are made to contribute to the Gm of the OTA and so the Gm is increased. Gm is further enhanced in Improved RFC OTA by creating one more high impedance dc path to

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"An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology." Al-Salam Journal for Engineering and Technology, January 29, 2023, 123–33. http://dx.doi.org/10.55145/ajest.2023.01.01.015.

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This project describes in detail the process of designing and simulating at first a one stage folded cascode operational amplifier using 0.25 um CMOS Technology with the self-biasing scheme for the NMOS differential input stage is discussed here. The design of the required circuits is done using the LTspice simulator. We will see that the simulation results approximately matches with the desired and theoretically calculated performance values. We are changing width values to bring all the transistors of the circuit in saturation. Then two Stage Folded Cascode Operational Amplifier with Miller

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