Dissertations / Theses on the topic 'Folded cascode'

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (leaves 67-68).
by Allison Margaret Marino.
M.S.

A tendência mundial em torno de sistemas SoC – System on Chip – baseados em processo CMOS – Complementary Metal Oxide Semiconductor – digital, apresenta cada vez mais desafios aos projetistas de circuitos integrados. Em especial se observa que enquanto os projetistas de circuitos digitais podem contar com bibliotecas cada vez mais completas de células digitais semi-prontas e ferramentas cada vez mais poderosas para o aprimoramento do projeto, os projetistas analógicos não contam com tais facilidades, sendo necessário realizar o projeto de novas células analógicas para cada especificação recebida. Este trabalho apresenta uma contribuição para a automatização do projeto de blocos analógicos e, para isso, foi escolhido um bloco essencial em muitos projetos analógicos: o amplificador operacional – ampOp. A idéia inicial por trás dessa escolha foi um conjunto de especificações fornecido pela empresa Freescale Semiconductors, para o projeto um préamplificador de áudio realizado no âmbito do Programa Nacional de Microeletrônica – PNM. A topologia escolhida para o amplificador operacional, retirada de [1], foi analisada e utilizada para projeto do amplificador para áudio. Além disso, um software de auxílio ao projeto para este amplificador foi escrito em linguagem C, e seu objetivo é auxiliar no reprojeto do ampOp para atender à especificações diversas. Para isso o software recebe como entradas as próprias especificações e um primeiro projeto do ampOp, realizado com equações simplificadas de projeto. O software então, em conjunto com um simulador elétrico, reprojeta o amplificador, retirando alguns parâmetros relevantes dos arquivos de simulação e utilizando equações de projeto mais completas. Ao final do trabalho, um exemplo de ampOp foi fabricado e caracterizado, sendo os resultados obtidos analisados.
The world trend towards SoC – System on Chip – based on digital CMOS – Complementary Metal Oxide Semiconductor – process presents more and more challenges to the IC designer. One can observe that while digital designers may rely on digital core libraries that are more and more complete, and design tools that are increasingly powerful and capable of optimizing the digital design, analog designers do not have such privileges available, becoming necessary to design such analog cores each time a new set of specifications is received. This work presents a contribution to the automatization of the design of analog cores and, in order to do that, an essential core was chosen: the operational amplifier. The choice for the operational amplifier was made in order to attend to a set of specifications provided by Freescale Semiconductors. This set was applied in the design of an audio pre-amplifier performed in the scope of the National Microelectronics Program – PNM. A topology chosen for the amplifier, extracted from [1], was analysed and applied to design the audio pre-amplifier. Additionaliy, a software for this specific amplifier was written, and its goal is to aid the redesign of the amplifier to comply with a set of specifications. In order to do this, the software receives, as input parameters, the set of specifications and the results of a first amplifier design, done by the analog designer using simplified equations. Then, together with an electrical simulator, the software redesigns the amplifier, reading some relevant information from the output file of the simulation and using more complete relations. At the end of this work, an example of amplifier was manufactured and characterized, and the final results were analyzed.

Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.

Analog-to-digital converters are inevitable in the modern communication systems and there is always a need for the design of low-power converters. There are different A/D architectures to achieve medium resolution at medium speeds and among all those Cyclic/Algorithmic structure stands out due to its low hardware complexity and less die area costs. This thesis aims at discussing the ongoing trend in Cyclic/Algorithmic ADCs and their functionality. Some design techniques are studied on how to implement low power high resolution A/D converters. Also, non-ideal effects of SC implementation for Cyclic A/D converters are explored. Two kinds of Cyclic A/D architectures are compared. One is the conventional Cyclic ADC with RSD technique and the other is Cyclic ADC with Correlated Level Shift (CLS) technique. This ADC is a part of IMST Design + Systems International GmbH project work and was designed and simulated at IMST GmbH. This thesis presents the design of a 12-bit, 1 Msps, Cyclic/Algorithmic Analog-to-Digital Converter (ADC) using the “Redundant Signed Digit (RSD)” algorithm or 1.5-bit/stage architecture with switched-capacitor (SC) implementation. The design was carried out in 130nm CMOS process with a 1.5 V power supply. This ADC dissipates a power of 1.6  mW when run at full speed and works for full-scale input dynamic range. The op-amp used in the Cyclic ADC is a two-stage folded cascode structure with Class A output stage. This op-amp in typical corner dissipates 631 uW power at 1.5 V power supply and achieves a gain of 77 dB with a phase margin of 64° and a GBW of 54 MHz at 2 pF load.

The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.

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Este presente trabalho descreve uma implementação CMOS em tecnologia ON 0.5 µm de um amplificador operacional de transcondutância (OTA) Folded Cascode projetado para gerar ruído referenciado à entrada (Input Referred Noise) mínimo para aplicações em arrays de sistemas integrados em chip (SoC) destinados a medições em eletroencefalogramas. É também descrita uma rede de realimentação proporcional, integral e derivativa (PID), imple_ mentada em pequena área de Silício, utilizando-se de um pseudo-resistor pMOS de alta resistência e pequenas capacitâncias de integração para controle de ganho em malha fechada através de chaves nMOS insensíveis a parasitas. Resultados de simulações pos layout mostram que o amplificador neural desenvolvido atinge em torno de 2.2 µVrms de ruído referenciado à entrada para 6 µA de corrente drenada total para uma tensão de alimentação de ± 1.8 V, obtendo assim um fator de eficiência à ruído (NEF) de 4.55 para uma largura de banda de 1.96 kHz e ganho central de 40.22 dB.

The present work deals with issues of a design of operational transconductance amplifier in technology CMOS AMIS 0,7 um. The aim of the work is to design a accurate operational amplifier with a low input differential voltage.

This diploma thesis deals with the design of eight-bit digital to analog coverter with fully differential outputs in technology I3T25 of ON Semiconductor company. The work contains the description of basic structures and characteristics of digital to analog converters. The main focus of the work is to design a converter and auxiliary circuits at the transistor level. The functionality of designed circuits is verified by simulation environment Cadence.

This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter.

A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type.

The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase.

The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.

碩士
國立雲林科技大學
電子工程系
104
This study presented an improved recycling folded cascode amplifier and it significantly improves the DC gain and gain bandwidth of traditional recycling folded cascode amplifier. To enhance the circuit performance, the nested Miller compensation technique has been applied to improve the traditional recycling folded cascode amplifier. The proposed circuit has been implemented and verified using TSMC 0.18um 1P6M CMOS process with 1.8V power supply and 5.6pF capacitor load. From the simulation results, the propose amplifier can achieve 135dB DC gain, 〖65〗^° phase margin, and 12MHz gain bandwidth.

碩士
國立雲林科技大學
電子與資訊工程研究所
93
In this dissertation, we discuss general low-voltage low noise amplifier principle and design. It includes nowadays dual band and ultra wideband low noise amplifier principle and design. Finally, we compare simulation results with measurement values. We adopt a low-voltage folded cascode topology to design the circuits of low noise amplifier for the receiver path of WLAN and WPAN. The circuits of low noise amplifier are based on 0.18um TSMC CMOS technology. In WLAN application, measurement data shows that the amplifier achieves maximum power gain of 9.2 dB, input return loss of -9.6 dB, output return loss of -21.5 dB, and minimal noise figure of 3.1 dB on the 5.7 GHz while consuming 7 mW, For the dual-band LNA, simulation results get a power gain of 18.24 dB and 14.2 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure is less than 3 dB at both 2.4 GHz and 5.2 GHz bands. In WPAN application, the maximum and minimum power gain of ultra wideband LNA are 13.16 dB and 10.44 dB, respectively. The -3dB bandwidth ranges between 3 GHz to 10 GHz in the circuit of the ultra wideband LNA. The minimum noise figure is also 2.67 dB owing to folded cascode technique. Hence, the noise figure is less than 3.9 dB within the range between 3 GHz to 10 GHz. In these circuits, the relatively high linearity was achieved without compromising power dissipation, gain and noise figure. The simulation is performed by the Agilent Advance Design System (ADS) sofeware. The circuit layout and verification is fished by Cadance.

碩士
國立高雄海洋科技大學
微電子工程研究所
102
Using TSMC 0.18 μm 1P6M technology, a low-power wide-bandwidth fully differential in/ differential out folded cascode OTA was designed. To ensure circuit stability at various temperatures (-40oC to 125oC) and process corners (SS,TT and FF), three time continuous common mode feedback(TC-CMFB) circuits were added. HSPICE simulations indicate that voltage gain 87 dB, phase margin 64 degree, unity gain bandwidth (UGBW) 1.08GHz, output swing -0.5V~0.54V, slew rate 112V/us, settling time 15ns, input common mode range(ICMR) -0.6V~0.2V, power supply reject ratio(PSRR) PSRR+ 121.1dB, PSRR- 121.3dB at 1kHz and average power dissipation 5.2mW. On-chip measurements indicate that experiment results are in line with simulated data that include output swing, common mode input range at DC and closed-loop gain measurements at 100kHz. However, offset voltage is 10mV higher than simulation due mainly to the chip layout, bonding wires and test setup effects. The as-designed OTA was further verified using a first-order delta-sigma(△Σ) modulator. Preliminary results show that using a 5kHz sinusoidal test signal, the △Σ modulator achieves 35dB dynamic range with a total average power dissipation of 5.5mW at a 2.56-M Sample/s Nyquist conversion rate.

碩士
大同工學院
電機工程學系
85
Design considerations for high frequency continuous-time current-mode filters are presented in the thesis. The basic building block is a fully-balanced folded cascode integrator which has high gain, high linearity,low harmonic distortion, and low power supply. Replacing the ideal current source with temperature-independent current bias source, the unity gain of the integrator will not vary with process and temperature. Consequently, the filter will not be tuned. For ladder filters derived from doubly terminated LC prototypes, HSPICE simulations predict a -3 dB bandwidth of 30 Mhz for a fifth-order Chebyshev low-pass filter. Power dissipation is 3.2 mW/pole with a 3.3 V power supply.

碩士
義守大學
電子工程學系
89
In this thesis, a fully differential folded cascode amplifier which can be implemented by standard digital CMOS process is presented.The design of the circuit’s architecture and it’s characteristic, is for the circuit architecture, the effects of different circuit architectures is analyzed, and the effect of the bias circuit is also analyzed. For circuit characteristics one section looks at a fully differential characteristic and the other at single ended output characteristic. To prevent noise capability of fully differential circuit is better than the single ended output circuit. A fully differential folded cascode amplifier, a single ended output amplifier, feedback network amplifiers, a fully differential non-reset switch-capacitor sample and hold circuit, a single ended output non-reset switch-capacitor sample and hold circuit, and a fully differential multiple resistor stage digital-to-analog converter circuit are designed and implemented.

Recent high-resolution seismic imaging has allowed detailed reconstruction of the relationship between fold development and crestal faulting of the Chinook and Cascade folds in the deepwater Gulf of Mexico. Using 3-D seismic and biostratigraphic data, we have found that (1) short wavelength (~2300m), small amplitude folds (~540m) within the upper Cretaceous and upper Jurassic stratigraphic sequences took place no later than the late Jurassic, (2) large wavelength and amplitude fold growth, starting in the early Cretaceous, was produced by salt withdrawal, and (3) periods of increased sedimentation, fold growth, and fault slip occurred during the middle Miocene and late Miocene. Although the dominant stage of long wavelength, large amplitude fold growth started around early Cretaceous, the development of the Cascade and Chinook structures was continuous, punctuated by episodes of accelerated growth during the middle Miocene at rates of 337 and 235 m/Ma in the Cascade and 203 and 230 m/Ma in the Chinook. A later event of accelerated growth occurred during the late Miocene at rates of 1038 m/Ma in the Cascade and 1189 m/Ma in the Chinook. Accompanying fold growth was sedimentation, which was highest at 1949 m/Ma in the Cascade and 2585 m/Ma in the Chinook. Although limb tilt rates varied through fold growth, the highest rates also occurred during the middle Miocene at 0.330 and 0.196 degree/Ma for the Cascade and Chinook, respectively with the development of crestal faults at maximum slip rates of 88 and 90 m/Ma.