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Journal articles on the topic 'Folded cascode'

Author: Grafiati

Published: 4 June 2021

Last updated: 2 February 2022

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1

Assaad, Rida S., and Jose Silva-Martinez. "The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier." IEEE Journal of Solid-State Circuits 44, no. 9 (September 2009): 2535–42. http://dx.doi.org/10.1109/jssc.2009.2024819.

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2

Song, Ming Xin, Yue Li, and Meng Meng Xu. "Design of High Gain CMOS Folded Cascode Operational Amplifier." Applied Mechanics and Materials 389 (August 2013): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.389.573.

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A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

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3

Kundra, Swati. "Low Power Folded Cascode OTA." International Journal of VLSI Design & Communication Systems 3, no. 1 (February 29, 2012): 127–36. http://dx.doi.org/10.5121/vlsic.2012.3111.

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4

Dan, Song, and Zhang Xiaolin. "Low-voltage CMOS Folded-cascode Mixer." Chinese Journal of Aeronautics 23, no. 2 (April 2010): 198–203. http://dx.doi.org/10.1016/s1000-9361(09)60205-3.

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5

Assaad, Rida, and Jose Silva-Martinez. "Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers." VLSI Design 2009 (July 28, 2009): 1–11. http://dx.doi.org/10.1155/2009/323595.

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Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

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6

Yosefi, Ghader. "The high recycling folded cascode (HRFC): A general enhancement of the recycling folded cascode operational amplifier." Microelectronics Journal 89 (July 2019): 70–90. http://dx.doi.org/10.1016/j.mejo.2019.04.016.

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7

Yan, Zushu, Pui-In Mak, and R. P. Martins. "Double recycling technique for folded-cascode OTA." Analog Integrated Circuits and Signal Processing 71, no. 1 (August 28, 2011): 137–41. http://dx.doi.org/10.1007/s10470-011-9762-y.

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8

Li, Xiang, Qi Wei, Bin Zhou, Zhiyong Chen, and Rong Zhang. "Data-driven complementary recycling folded cascode OTA." Journal of Physics: Conference Series 1074 (September 2018): 012083. http://dx.doi.org/10.1088/1742-6596/1074/1/012083.

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9

Garde, M. Pilar, Antonio Lopez-Martin, Ramon Gonzalez Carvajal, and Jaime Ramirez-Angulo. "Super Class-AB Recycling Folded Cascode OTA." IEEE Journal of Solid-State Circuits 53, no. 9 (September 2018): 2614–23. http://dx.doi.org/10.1109/jssc.2018.2844371.

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10

Espinosa-Flores-Verdad, G., and R. Salinas-Cruz. "Symmetrically compensated fully differential folded-cascode OTA." Electronics Letters 35, no. 19 (1999): 1603. http://dx.doi.org/10.1049/el:19991125.

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11

Choi, Gyuri, Hyunwoo Heo, Donggeun You, Hyungseup Kim, Kyeongsik Nam, Mookyoung Yoo, Sangmin Lee, and Hyoungho Ko. "A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier." Applied Sciences 11, no. 17 (August 28, 2021): 7982. http://dx.doi.org/10.3390/app11177982.

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In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

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12

Yavari, Mohammad. "A new class AB folded-cascode operational amplifier." IEICE Electronics Express 6, no. 7 (2009): 395–402. http://dx.doi.org/10.1587/elex.6.395.

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13

Koonapalli, Harish, and V. N. Ramakrishnan. "Design of Radiation Hardened Complementary Folded Cascode Amplifier." Materials Today: Proceedings 24 (2020): 1766–76. http://dx.doi.org/10.1016/j.matpr.2020.03.601.

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14

Mandal, Pradip, and V. Visvanathan. "Self-biasing of folded cascode CMOS op-amps." International Journal of Electronics 87, no. 7 (July 2000): 795–808. http://dx.doi.org/10.1080/00207210050028733.

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15

Zhao, Xiao, Huajun Fang, and Jun Xu. "A power-efficient improved recycling folded cascode amplifier." International Journal of Electronics 100, no. 12 (December 2013): 1660–66. http://dx.doi.org/10.1080/00207217.2012.752040.

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16

Nakamura, K., and L. R. Carley. "An enhanced fully differential folded-cascode op amp." IEEE Journal of Solid-State Circuits 27, no. 4 (April 1992): 563–68. http://dx.doi.org/10.1109/4.126544.

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17

Rezaei, M., E. Zhian-Tabasy, and S. J. Ashtiani. "Slew rate enhancement method for folded-cascode amplifiers." Electronics Letters 44, no. 21 (2008): 1226. http://dx.doi.org/10.1049/el:20082200.

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18

Raman, J., P. Rombouts, and L. Weyten. "Folded-cascode amplifier with efficient feedforward gain-boosting." Electronics Letters 46, no. 21 (2010): 1425. http://dx.doi.org/10.1049/el.2010.2543.

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19

Greer, N. P. J., and P. B. Denyer. "New folded cascode transconductor for bandpass ladder filters." IEE Proceedings G Circuits, Devices and Systems 138, no. 5 (1991): 551. http://dx.doi.org/10.1049/ip-g-2.1991.0090.

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20

Kanthi, T., and D. Sharath Babu Rao. "Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 143. http://dx.doi.org/10.11591/ijres.v7.i3.pp143-150.

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This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

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21

Kanthi, T., and D. Sharath Babu Rao. "Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 149. http://dx.doi.org/10.11591/ijres.v7.i3.pp149-156.

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This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

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22

Lv, Xiaolong, Xiao Zhao, Yongqing Wang, and Boran Wen. "An improved non-linear current recycling folded cascode OTA with cascode self-biasing." AEU - International Journal of Electronics and Communications 101 (March 2019): 182–91. http://dx.doi.org/10.1016/j.aeue.2019.01.023.

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23

Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (March 4, 2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

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24

Yavari, Mohammad, and Omid Shoaei. "A novel fully-differential class AB folded-cascode OTA." IEICE Electronics Express 1, no. 13 (2004): 358–62. http://dx.doi.org/10.1587/elex.1.358.

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25

Lv, Xiaolong, Xiao Zhao, Yongqing Wang, and Dawei Jia. "Super class AB-AB bulk-driven folded cascode OTA." Integration 63 (September 2018): 196–203. http://dx.doi.org/10.1016/j.vlsi.2018.07.009.

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26

Zhao, Xiao, Huajun Fang, and Jun Xu. "Phase-margin enhancement technique for recycling folded cascode amplifier." Analog Integrated Circuits and Signal Processing 74, no. 2 (December 18, 2012): 479–83. http://dx.doi.org/10.1007/s10470-012-0011-9.

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27

Zhao, Xiao, Huajun Fang, and Jun Xu. "A transconductance enhanced recycling structure for folded cascode amplifier." Analog Integrated Circuits and Signal Processing 72, no. 1 (February 19, 2012): 259–63. http://dx.doi.org/10.1007/s10470-012-9843-6.

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28

Nagulapalli, R., K. Hayatleh, S. Barker, B. Yassine, S. Zourob, S. Raparthy, and N. Yassine. "A Start-up Assisted Fully Differential Folded Cascode Opamp." Journal of Circuits, Systems and Computers 28, no. 10 (September 2019): 1950164. http://dx.doi.org/10.1142/s0218126619501640.

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This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87[Formula: see text]dB, 250[Formula: see text]MHz unity gain bandwidth amplifier has been developed in 65[Formula: see text]nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126[Formula: see text][Formula: see text]A from a 1.2[Formula: see text]V supply and occupies the 2184[Formula: see text][Formula: see text]m2 area.

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29

Vallee, R. E., and E. I. El-Masry. "A very high-frequency CMOS complementary folded cascode amplifier." IEEE Journal of Solid-State Circuits 29, no. 2 (1994): 130–33. http://dx.doi.org/10.1109/4.272117.

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30

Kargaran, Ehsan, Yasser Mafinejad, Khalil Mafinezhad, and Hooman Nabovati. "A new gm-boosting current reuse CMOS folded cascode LNA." IEICE Electronics Express 10, no. 24 (2013): 20130264. http://dx.doi.org/10.1587/elex.10.20130264.

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31

Wang, Zhe Fei, Yi Jiang Cao, and Ju Meng Feng. "A Design of High Performance CMOS Folded Cascode Operational Amplifier." Advanced Materials Research 981 (July 2014): 31–35. http://dx.doi.org/10.4028/www.scientific.net/amr.981.31.

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This paper describes a kind of folded cascode amplifier, which not only has high gain, large output swing characteristics, and its outputs can be self-compensation, it has a strong suppression capability with voltage noise. Based on a 0.5μm CMOS process uses two operational amplifiers. Through software emulation corrected the error which was caused by theoretical calculation. Has good performance in gain, noise, swing, phase margin, common mode rejection ratio and other parameters.

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32

Sharma, Sanjeev, Pawandeep Kaur, and Tapsi Singh. "Design and Analysis of Gain Boosted Recycling Folded Cascode OTA." International Journal of Computer Applications 76, no. 7 (August 23, 2013): 8–13. http://dx.doi.org/10.5120/13257-0735.

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33

Chan, P. K., L. S. Ng, L. Siek, and K. T. Lau. "Designing CMOS folded-cascode operational amplifier with flicker noise minimisation." Microelectronics Journal 32, no. 1 (January 2001): 69–73. http://dx.doi.org/10.1016/s0026-2692(00)00105-1.

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34

Khemchandani, Sunil L., Dailos Ramos-Valido, Hugo García-Vázquez, Ruben Pulido-Medina, and Javier del Pino. "A low voltage folded cascode LNA for ultra-wideband applications." Microwave and Optical Technology Letters 52, no. 11 (August 17, 2010): 2495–500. http://dx.doi.org/10.1002/mop.25530.

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35

Assaad, R., and J. Silva-Martinez. "Enhancing general performance of folded cascode amplifier by recycling current." Electronics Letters 43, no. 23 (2007): 1243. http://dx.doi.org/10.1049/el:20072031.

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36

Li, Yilei, Kefeng Han, Na Yan, Xi Tan, and Hao Min. "Analysis and implementation of an improved recycling folded cascode amplifier." Journal of Semiconductors 33, no. 2 (February 2012): 025002. http://dx.doi.org/10.1088/1674-4926/33/2/025002.

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37

Su, C., B. J. Blalock, S. K. Islam, L. Zuo, and L. M. Tolbert. "A High-Temperature Folded-Cascode Operational Transconductance Amplifier in 0.8-μm BCD-on-SOI." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000083–88. http://dx.doi.org/10.4071/hitec-csu-ta26.

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The rapid growth of the hybrid electric vehicles (HEVs) has been driving the demand of high temperature automotive electronics target for the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. An operational transconductance amplifier (OTA) is an essential building block of various analog circuits such as data converters, instrumentation systems, linear regulators, etc. This work presents a high temperature folded cascode operational transconductance amplifier designed and fabricated in a commercially available 0.8-μm BCD-on-SOI process. SOI processes offer several orders of magnitude smaller junction leakage current than bulk-CMOS processes at temperatures beyond 150°C. This amplifier is designed for a high temperature linear voltage regulator; the higher open-loop gain of this amplifier will enhance the overall performance of a linear regulator. In addition, the lower current consumption of the OTA is critical for improving the current efficiency of the linear regulator and reducing the power dissipation at elevated temperature. A PMOS input pair folded cascode OTA topology had been selected in this work, PMOS input pair offers wider ICMR (input common-mode range) and empirically lower flicker noise compared to its NMOS counterpart. By cascoding current mirror load at the output node, the folded cascode OTA obtains higher voltage gain than the symmetrical OTA topology. The PSRR (power supply rejection ratio) is also improved. A on-chip temperature stable current reference is employed to bias the amplifier. The amplifier consumes less than 65μA bias current at 175°C. The core layout area of the amplifier is 0.16mm2 (400 μm × 400 μm).

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38

Bendre, Varsha S., A. K. Kureshi, and Saurabh Waykole. "Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier." Journal of Nanotechnology 2018 (December 4, 2018): 1–15. http://dx.doi.org/10.1155/2018/2301421.

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Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

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39

Ibarra, F. Sandoval, V. H. Arzate Palma, and S. D. Cárdenas Castellón. "Design of a Fully Differential CMOS OTA Folded Cascode for Modulation." International Journal of Emerging Technology and Advanced Engineering 10, no. 11 (November 30, 2020): 1–6. http://dx.doi.org/10.46338/ijetae1120_01.

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In this paper, the design and experimental results of a fully-differential folded-cascode operational amplifier of transconductance (OTA) is presented. This active circuit is for the use in a  low-pass modulator. The structure of the OTA is for obtaining a transition frequency of 1.0GHz. From the circuit synthesis, the OTA can handle the signals with the peak-to-peak amplitude of 300mV, and consumes 1.5mA from 1.2V supply. The OTA is fabricated in 130nm standard CMOS technology.

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40

KIHARA, Takao, Hae-Ju PARK, Isao TAKOBE, Fumiaki YAMASHITA, Toshimasa MATSUOKA, and Kenji TANIGUCHI. "A 0.5V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier." IEICE Transactions on Electronics E92-C, no. 4 (2009): 564–75. http://dx.doi.org/10.1587/transele.e92.c.564.

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41

Kaur, Jasbir, and Neha Shukla. "Analysis of Two Stage Folded Cascode Operational Amplifier in 90nm Technology." IJIREEICE 5, no. 6 (June 15, 2017): 149–56. http://dx.doi.org/10.17148/ijireeice.2017.5626.

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42

Zhao, Xiao, Yongqing Wang, and Liyuan Dong. "Super current recycling folded cascode amplifier with ultra-high current efficiency." Integration 62 (June 2018): 322–28. http://dx.doi.org/10.1016/j.vlsi.2018.03.019.

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43

Akbari, Meysam, Sadegh Biabanifard, Shahrouz Asadi, and Mustapha C. E. Yagoub. "High performance folded cascode OTA using positive feedback and recycling structure." Analog Integrated Circuits and Signal Processing 82, no. 1 (December 10, 2014): 217–27. http://dx.doi.org/10.1007/s10470-014-0464-0.

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44

Roewer, F., and U. Kleine. "A novel class of complementary folded-cascode opamps for low voltage." IEEE Journal of Solid-State Circuits 37, no. 8 (August 2002): 1080–83. http://dx.doi.org/10.1109/jssc.2002.800949.

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45

Lopez-Martin, Antonio J., M. Pilar Garde, Jose M. Algueta, Carlos A. de la Cruz Blas, Ramon G. Carvajal, and Jaime Ramirez-Angulo. "Enhanced Single-Stage Folded Cascode OTA Suitable for Large Capacitive Loads." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 4 (April 2018): 441–45. http://dx.doi.org/10.1109/tcsii.2017.2700060.

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46

Akbari, M., and O. Hashemipour. "Enhancing transconductance of ultra‐low‐power two‐stage folded cascode OTA." Electronics Letters 50, no. 21 (October 2014): 1514–16. http://dx.doi.org/10.1049/el.2014.2399.

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47

Akbari, M. "Single‐stage fully recycling folded cascode OTA for switched‐capacitor circuits." Electronics Letters 51, no. 13 (June 2015): 977–79. http://dx.doi.org/10.1049/el.2015.1053.

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48

Mallya, S., and J. H. Nevin. "Design procedures for a fully differential folded-cascode CMOS operational amplifier." IEEE Journal of Solid-State Circuits 24, no. 6 (1989): 1737–40. http://dx.doi.org/10.1109/4.45013.

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49

Atkinson, Blaine, Kauppila, Armstrong, T. Daniel Loveless, Hooten, Holman, Massengill, and Warner. "RHBD Technique for Single-Event Charge Cancellation in Folded-Cascode Amplifiers." IEEE Transactions on Nuclear Science 60, no. 4 (August 2013): 2756–61. http://dx.doi.org/10.1109/tns.2013.2240316.

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50

VENISHETTY, Sudheer Raja, and Kumaravel SUNDARAM. "Modified recycling folded cascode OTA with enhancement in transconductanceand output impedance." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 27, no. 6 (November 26, 2019): 4472–85. http://dx.doi.org/10.3906/elk-1902-82.

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