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Journal articles on the topic 'Folding ADC'

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Published: 4 June 2021
Last updated: 15 February 2022

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1

van Valburg, J., and R. J. van de Plassche. "An 8-b 650-MHz folding ADC." IEEE Journal of Solid-State Circuits 27, no. 12 (1992): 1662–66. http://dx.doi.org/10.1109/4.173091.

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2

Moldsvor, Oystein, and Geir S. Ostrem. "8-bit, 200 MSPS folding and interpolating ADC." Computer Standards & Interfaces 21, no. 2 (June 1999): 103. http://dx.doi.org/10.1016/s0920-5489(99)91940-2.

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3

Le, Binh Son, Trong Tu Bui, and Duc Hung Le. "A Design of 10-b 100-MS/s Pipelined Folding ADC with Distributed Track-and-Hold Preprocessing." Science and Technology Development Journal 17, no. 1 (March 31, 2014): 39–51. http://dx.doi.org/10.32508/stdj.v17i1.1241.

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This paper presents a 10-b ADC designed in a 0.18-μm CMOS technology. The ADC achieves 10-b resolution by using the cascaded folding technique in both the fine and coarse converters. Folding stages are pipelined to improve the settling time. As a result, this ADC can achieve the sampling rate up to 100MS/s. Moreover, instead of using a costly single track-and-hold circuit, a distributed track-and-hold circuit is used to reduce the chip area and the power consumption. This also allows utilizing the open-loop architecture of the folding technique, thus improving the performance of the system. The simulation results show that with a 49 MHz sine-wave input, the ADC consumes 66 mW and the effective number of bit (ENOB) is 9.28-b. Taking into account of process variations by using a Monte Carlo simulation, the DNL varies from ±0.45LSB to ±0.25LSB. The layout of the ADC occupies 1.2 mm2 die area.
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4

Kobayashi, Haruo, Toshiya Mizuta, Kenji Uchida, Hiroyuki Matsuura, Akira Miura, Tsuyoshi Yakihara, Sadaharu Oka, and Daisuke Murata. "Design consideration for folding/interpolation ADC with SiGe HBT." Computer Standards & Interfaces 21, no. 2 (June 1999): 115. http://dx.doi.org/10.1016/s0920-5489(99)91988-8.

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5

Zhang, Yi, Qiao Meng, Changchun Zhang, Ying Zhang, Yufeng Guo, Youtao Zhang, Xiaopeng Li, and Lei Yang. "A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology." Journal of Sensors 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/3984526.

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A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.
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6

Ahn, Cheol-Min, and Young-Sik Kim. "A 8-bit 10-MSample/s Folding & Interpolation ADC using Preamplifier Sharing Method." Journal of IKEEE 17, no. 3 (September 30, 2013): 275–83. http://dx.doi.org/10.7471/ikeee.2013.17.3.275.

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7

Vorenkamp, Pieter, and Raf Roovers. "12-B, 60-MSample/S cascaded folding and interpolating ADC." Computer Standards & Interfaces 21, no. 2 (June 1999): 105. http://dx.doi.org/10.1016/s0920-5489(99)91948-7.

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8

van de Grift, R., I. W. J. M. Rutten, and M. van der Veen. "An 8-bit video ADC incorporating folding and interpolation techniques." IEEE Journal of Solid-State Circuits 22, no. 6 (December 1987): 944–53. http://dx.doi.org/10.1109/jssc.1987.1052842.

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9

Myung-Jun Choe, Bang-Sup Song, and K. Bacrania. "An 8-b 100-MSample/s CMOS pipelined folding ADC." IEEE Journal of Solid-State Circuits 36, no. 2 (2001): 184–94. http://dx.doi.org/10.1109/4.902759.

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10

Gao, Yu Han, Ru Zhang Li, Dong Bing Fu, Yong Lu Wang, and Zheng Ping Zhang. "An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC." Advanced Materials Research 1049-1050 (October 2014): 687–90. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.687.

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High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.
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11

Han, Jing Lei, Wen Lian Zhang, and Zhi Biao Shao. "A Novel Pre-Amplifier for DTH in Folding and Interpolating ADC." Applied Mechanics and Materials 321-324 (June 2013): 367–71. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.367.

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A pre-amplifier for distributed track and hold (DTH) circuit in high speed and high resolution folding and interpolating analog-to-digital converter (ADC) is proposed. This scheme resolves several limitations of conventional differential difference pre-amplifier (DDPA) in low voltage supply, compared to the conventional DDPA, the proposed scheme increases the input range so that all DDPAs of DTH can operate effectively, improves the averaging effect of average network, saves the random offset voltage from device mismatch, decreases the gain error of DTH, reduces the output common-mode (CM) deviation of DTH, and enhances the CM rejection of DTH. Based on SMIC 0.18μm CMOS technology and 1.8V power supply, over the input range, results from spectre shows dummy DDPAs of DTH operate effectively, the offset of output CM voltage of DTH decrease to less than 2mV, gain error decrease to less than 1%, the gain of middle novel pre-amplifier and boundary novel pre-amplifier are both 2.5, bandwidths are all above 1.9GHZ, while power dissipation of each DDPA is 3.22mW. The high CM rejection and low gain error decrease the quantification error effectively, and enhance the performance of ADC. The design meets the requirement of ADC applied to software defined radio (SDR).
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12

Mortazavi, Seyed Yahya, and Abdolreza Nabavi. "A New folding & interpolating ADC structure with reduced DNL/INL." IEICE Electronics Express 6, no. 2 (2009): 90–97. http://dx.doi.org/10.1587/elex.6.90.

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13

Lai, Yen-Tai, and Chia-Nan Yeh. "A folding technique for reducing circuit complexity of flash ADC decoders." Analog Integrated Circuits and Signal Processing 63, no. 2 (October 15, 2009): 339–48. http://dx.doi.org/10.1007/s10470-009-9404-9.

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14

Vorenkamp, P., and R. Roovers. "A 12-b, 60-MSample/s cascaded folding and interpolating ADC." IEEE Journal of Solid-State Circuits 32, no. 12 (1997): 1876–86. http://dx.doi.org/10.1109/4.643646.

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15

Flynn, M. P., and B. Sheahan. "A 400-Msample/s, 6-b CMOS folding and interpolating ADC." IEEE Journal of Solid-State Circuits 33, no. 12 (1998): 1932–38. http://dx.doi.org/10.1109/4.735533.

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16

Choi, Donggwi, Daeyun Kim, and Minkyu Song. "A 8b 1GS/s Fractional Folding-Interpolation ADC with a Novel Digital Encoding Technique." Journal of the Institute of Electronics and Information Engineers 50, no. 1 (January 25, 2013): 137–47. http://dx.doi.org/10.5573/ieek.2013.50.1.137.

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17

Yan, Lu, Lin Li, Xia Jiefeng, Ye Fan, and Ren Junyan. "An 8-b 300MS/S folding and interpolating ADC for embedded applications." Journal of Semiconductors 31, no. 6 (June 2010): 065015. http://dx.doi.org/10.1088/1674-4926/31/6/065015.

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18

Chen, Cheng, and Junyan Ren. "An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25 mm2." Analog Integrated Circuits and Signal Processing 47, no. 2 (February 27, 2006): 203–6. http://dx.doi.org/10.1007/s10470-006-4619-5.

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19

Agrawal, Niket, and Roy Paily. "A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS." Analog Integrated Circuits and Signal Processing 63, no. 2 (September 22, 2009): 273–81. http://dx.doi.org/10.1007/s10470-009-9388-5.

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20

Gao, Yu Han, Yong Lu Wang, Guang Bin Chen, Zheng Ping Zhang, Can Zhu, Lei Zhang, Rong Ke Ye, and Rong Bin Hu. "An 8-bit 5-Gsample/s Time-Interleaved Analog-to-Digital Converter Used for Optical Communication." Advanced Materials Research 756-759 (September 2013): 205–8. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.205.

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In this paper, we present an 8-bit 5 Gsample/s time-interleaved analog-to-digital converter (TI ADC). A 4-phase low jitter clock is designed to control four 1.25 Gsample/s sub-ADCs which is implemented using folding and interpolating architecture. Digital calibration is used to adjust the offset error and gain error of sub-ADCs. Meanwhile, serial peripheral interface (SPI) is adopted to adjust mismatch of gain and sample time between sub-ADCs. The whole TI ADC is designed using a 0.18m SiGe BiCMOS process. The whole ADC has a SNR of about 45 dB at the input frequency of 495 MHZ and an equivalent ENOB of 7.2 bits.
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21

Liu, Huasen, Danyu Wu, Lei Zhou, Jian Luan, Xuan Guo, Dong Wang, Jin Wu, and Xinyu Liu. "A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm." IEICE Electronics Express 16, no. 7 (2019): 20181150. http://dx.doi.org/10.1587/elex.16.20181150.

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22

Lin, Li, Junyan Ren, Kai Zhu, and Fan Ye. "A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS." Analog Integrated Circuits and Signal Processing 58, no. 1 (October 29, 2008): 71–76. http://dx.doi.org/10.1007/s10470-008-9222-5.

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23

Myung-Jun Choe, Bang-Sup Song, and K. Bacrania. "A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming." IEEE Journal of Solid-State Circuits 35, no. 12 (December 2000): 1781–90. http://dx.doi.org/10.1109/4.890291.

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24

Zhen, Liu, Jia Song, Wang Yuan, Ji Lijiu, and Zhang Xing. "Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit." Journal of Semiconductors 30, no. 12 (December 2009): 125013. http://dx.doi.org/10.1088/1674-4926/30/12/125013.

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25

He, Wenwei, Qiao Meng, Yi Zhang, and Kai Tang. "A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS." Journal of Semiconductors 35, no. 8 (August 2014): 085004. http://dx.doi.org/10.1088/1674-4926/35/8/085004.

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26

Jiang, Fan, DanYu Wu, Lei Zhou, Jin Wu, Zhi Jin, and XinYu Liu. "A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC." Science China Information Sciences 57, no. 1 (November 30, 2013): 1–6. http://dx.doi.org/10.1007/s11432-013-5019-y.

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27

Wang, Mingshuo, Fan Ye, Wei Li, and Junyan Ren. "A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth." IEICE Electronics Express 11, no. 2 (2014): 20130986. http://dx.doi.org/10.1587/elex.11.20130986.

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28

ONO, Koichi, Takeshi OHKAWA, Masahiro SEGAMI, and Masao HOTTA. "A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique." IEICE Transactions on Electronics E93-C, no. 3 (2010): 288–94. http://dx.doi.org/10.1587/transele.e93.c.288.

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29

Jiang, Fan, Danyu Wu, Lei Zhou, Jin Wu, Zhi Jin, and Xinyu Liu. "An 8-bit 1 GS/s folding and interpolating ADC with a base-4 architecture." Analog Integrated Circuits and Signal Processing 76, no. 1 (May 7, 2013): 139–46. http://dx.doi.org/10.1007/s10470-013-0072-4.

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30

Movahedian Attar, Hamid, and Mehrdad Sharif Bakhtiar. "Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range." Analog Integrated Circuits and Signal Processing 61, no. 2 (February 10, 2009): 181–89. http://dx.doi.org/10.1007/s10470-009-9282-1.

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31

Pace, P. E., D. Styer, and I. A. Akin. "A folding ADC preprocessing architecture employing a robust symmetrical number system with gray-code properties." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47, no. 5 (May 2000): 462–67. http://dx.doi.org/10.1109/82.842114.

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32

Yunchu Li and E. Sanchez-Sinencio. "A wide input bandwidth 7-bit 300-msample/s folding and current-mode interpolating adc." IEEE Journal of Solid-State Circuits 38, no. 8 (August 2003): 1405–10. http://dx.doi.org/10.1109/jssc.2003.814429.

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33

Upton, David W., Richard P. Haigh, Peter J. Mather, Pavlos I. Lazaridis, Keyur K. Mistry, Zaharias D. Zaharis, Christos Tachtatzis, and Robert C. Atkinson. "Gated Pipelined Folding ADC-Based Low Power Sensor for Large-Scale Radiometric Partial Discharge Monitoring." IEEE Sensors Journal 20, no. 14 (July 15, 2020): 7826–36. http://dx.doi.org/10.1109/jsen.2020.2982576.

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34

Wang, Linfeng, Qiao Meng, Wenwei He, Daoyuan Zhang, and Hengfei Ma. "Digital encoding calibrated unit used in 8 bit 1 GS/s folding and interpolating ADC." Electronics Letters 52, no. 5 (March 2016): 344–46. http://dx.doi.org/10.1049/el.2015.3934.

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35

Nakajima, Yuji, Akemi Sakaguchi, Toshio Ohkido, Norihito Kato, Tetsuya Matsumoto, and Michio Yotsuyanagi. "A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture." IEEE Journal of Solid-State Circuits 45, no. 4 (April 2010): 707–18. http://dx.doi.org/10.1109/jssc.2010.2042249.

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36

Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, and Franco Maloberti. "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS." IEEE Journal of Solid-State Circuits 48, no. 9 (September 2013): 2154–69. http://dx.doi.org/10.1109/jssc.2013.2264617.

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37

Li, Rui, and Dian Ren Chen. "Multicomponent Signal Detection and Parameter Estimation Algorithm of Synchronization Nyquist Folding Receiver." Applied Mechanics and Materials 568-570 (June 2014): 218–22. http://dx.doi.org/10.4028/www.scientific.net/amm.568-570.218.

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Nyquist Folding Receiver is a novel reconnaissance receiver structure which is able to use single ADC to sample Ultra-wideband signals. And the Synchronous Nyquist Folding Receiver (SNYFR) is an improved structure of NYFR. When input is multicomponent single-frequency signal, with the consideration of the characteristics of the output we propose an algorithm of Nyquist Zone(NZ) judgment and parameters estimation based on scaling search in Fractional Fourier Transform (FRFT) domain to avoid detection error occurring when the input signal components locate in the NZ fuzzy area. Computer simulation show that when SNR beyond, the Probability of Correct Decision(PCD) of signal detection can be achieved 100% and the mean square error of parameters estimation can be approached Cramer-Rao Bound(CRB) simultaneously.
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38

Wang, Dong, Jian Luan, Xuan Guo, Lei Zhou, Danyu Wu, Huasen Liu, Hao Ding, Jin Wu, and Xinyu Liu. "A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology." Electronics 8, no. 2 (February 25, 2019): 253. http://dx.doi.org/10.3390/electronics8020253.

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A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.
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39

PETRELLIS, N., G. ADAM, and D. VENTZAS. "MONOTONIC ERROR ELIMINATION IN SUBRANGE A/D CONVERTERS." Journal of Circuits, Systems and Computers 22, no. 01 (January 2013): 1250073. http://dx.doi.org/10.1142/s0218126612500739.

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Monotonic errors cause severe errors and are inherent in several A/D Converter (ADC) architectures. Moreover, several error correcting and ADC output processing methods require a monotonic behavior for a successful operation. Based on the features of asynchronous ADCs, an architecture for the elimination of monotonic errors is presented. This monotonic error correcting module is connected at the output of an ADC and does not require any modification in its internal circuits. It controls an output buffering stage that discards output codes with monotonic errors and this correcting procedure is triggered by changes in specific output bits of the ADC. Simulation results show an improvement by 8 dB or 25% maximum, in the signal-to-noise and distortion ratio (SNDR) of an 8-bit ADC if this monotonic error elimination method is used alone and a further improvement by 1–5 dB if it is combined with a post processing method developed by the authors. Similar improvement can also be achieved in several other architectures like Subrange or Folding ADCs that operate in relatively high oversampling ratio and suffer from monotonic errors with specific features.
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40

Liu, Huasen, Danyu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, and Xinyu Liu. "A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS." IEICE Electronics Express 16, no. 3 (2019): 20181079. http://dx.doi.org/10.1587/elex.16.20181079.

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41

Zhang, Guohe, Bo Wang, Feng Liang, and Zhibiao Shao. "A low-kickback-noise and low-voltage latched comparator for high-speed folding and interpolating ADC." IEICE Electronics Express 5, no. 22 (2008): 943–48. http://dx.doi.org/10.1587/elex.5.943.

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42

Verbruggen, Bob, Jan Craninckx, Maarten Kuijk, Piet Wambacq, and Geert Van der Plas. "A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS." IEEE Journal of Solid-State Circuits 44, no. 3 (March 2009): 874–82. http://dx.doi.org/10.1109/jssc.2009.2012449.

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43

Huang, Yu Sheng. "The Implemention of a Digital SSB Modulator Based on Folding Transformation." Applied Mechanics and Materials 543-547 (March 2014): 524–27. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.524.

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Single-Sideband (SSB) modulation is now widely used for its high band efficiency and low power consumption. In anolog SSB systems, it is usually hard to achieve high performance due to many nonideal factors of anolog components and circuits, such as the I/Q channel mismatch and temperature drift. To overcome these disadvantages, a digtal SSB modulation system based on the Weaver method is designed in this paper. In this system we creatively use the onchip ADC of the ARM processor for audio sampling. Besides, the CORDIC algorithm and the folding transformation are also utilized to reduce hardware costs in the FPGA implemention. This paper mainly discusses the theory and implemention of the Weaver SSB modulation system, and shows the experimental results on actual hardware.
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44

Wang, Mingshuo, Li Lin, Fan Ye, and Junyan Ren. "A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding." IEICE Electronics Express 11, no. 12 (2014): 20140371. http://dx.doi.org/10.1587/elex.11.20140371.

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45

Wang, Luke, Marc-Andre LaCroix, and Anthony Chan Carusone. "A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET." IEEE Transactions on Circuits and Systems II: Express Briefs 64, no. 12 (December 2017): 1367–71. http://dx.doi.org/10.1109/tcsii.2017.2726063.

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46

Liu, Shubin, Haolin Han, Yi Shen, and Zhangming Zhu. "A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 8 (August 2020): 2602–11. http://dx.doi.org/10.1109/tcsi.2020.2982913.

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47

Ming-Huang Liu and Shen-Iuan Liu. "An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique." IEEE Journal of Solid-State Circuits 36, no. 1 (2001): 122–28. http://dx.doi.org/10.1109/4.896236.

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48

Taft, R. C., C. A. Menkus, M. R. Tursi, O. Hidri, and V. Pons. "A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency." IEEE Journal of Solid-State Circuits 39, no. 12 (December 2004): 2107–15. http://dx.doi.org/10.1109/jssc.2004.836242.

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49

Li, Lin, Ren Junyan, and Ye Fan. "A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS." Journal of Semiconductors 31, no. 2 (February 2010): 025009. http://dx.doi.org/10.1088/1674-4926/31/2/025009.

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50

Wang, Tongxi, Min-Woong Seo, Keita Yasutomi, and Shoji Kawahito. "A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors." IEICE Electronics Express 14, no. 2 (2017): 20161199. http://dx.doi.org/10.1587/elex.14.20161199.

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